/* SPDX-License-Identifier: GPL-2.0+ */ /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $ * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver. * * Copyright (C) 2004 Sun Microsystems Inc. * Copyright (c) 2003 Adrian Sun ([email protected]) * * vendor id: 0x108E (Sun Microsystems, Inc.) * device id: 0xabba (Cassini) * revision ids: 0x01 = Cassini * 0x02 = Cassini rev 2 * 0x10 = Cassini+ * 0x11 = Cassini+ 0.2u * * vendor id: 0x100b (National Semiconductor) * device id: 0x0035 (DP83065/Saturn) * revision ids: 0x30 = Saturn B2 * * rings are all offset from 0. * * there are two clock domains: * PCI: 33/66MHz clock * chip: 125MHz clock */ #ifndef _CASSINI_H #define _CASSINI_H /* cassini register map: 2M memory mapped in 32-bit memory space accessible as * 32-bit words. there is no i/o port access. REG_ addresses are * shared between cassini and cassini+. REG_PLUS_ addresses only * appear in cassini+. REG_MINUS_ addresses only appear in cassini. */ #define CAS_ID_REV2 … #define CAS_ID_REVPLUS … #define CAS_ID_REVPLUS02u … #define CAS_ID_REVSATURNB2 … /** global resources **/ /* this register sets the weights for the weighted round robin arbiter. e.g., * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit * for its next turn to access the pci bus. * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 * DEFAULT: 0x0, SIZE: 5 bits */ #define REG_CAWR … #define CAWR_RX_DMA_WEIGHT_SHIFT … #define CAWR_RX_DMA_WEIGHT_MASK … #define CAWR_TX_DMA_WEIGHT_SHIFT … #define CAWR_TX_DMA_WEIGHT_MASK … #define CAWR_RR_DIS … /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst * sizes determined by length of packet or descriptor transfer and the * max length allowed by the target. * DEFAULT: 0x0, SIZE: 1 bit */ #define REG_INF_BURST … #define INF_BURST_EN … /* top level interrupts [0-9] are auto-cleared to 0 when the status * register is read. second level interrupts [13 - 18] are cleared at * the source. tx completion register 3 is replicated in [19 - 31] * DEFAULT: 0x00000000, SIZE: 29 bits */ #define REG_INTR_STATUS … #define INTR_TX_INTME … #define INTR_TX_ALL … #define INTR_TX_DONE … #define INTR_TX_TAG_ERROR … #define INTR_RX_DONE … #define INTR_RX_BUF_UNAVAIL … #define INTR_RX_TAG_ERROR … #define INTR_RX_COMP_FULL … #define INTR_RX_BUF_AE … #define INTR_RX_COMP_AF … #define INTR_RX_LEN_MISMATCH … #define INTR_SUMMARY … #define INTR_PCS_STATUS … #define INTR_TX_MAC_STATUS … #define INTR_RX_MAC_STATUS … #define INTR_MAC_CTRL_STATUS … #define INTR_MIF_STATUS … #define INTR_PCI_ERROR_STATUS … #define INTR_TX_COMP_3_MASK … #define INTR_TX_COMP_3_SHIFT … #define INTR_ERROR_MASK … /* determines which status events will cause an interrupt. layout same * as REG_INTR_STATUS. * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits */ #define REG_INTR_MASK … /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS. * useful when driver is polling for interrupts. layout same as REG_INTR_MASK. * DEFAULT: 0x00000000, SIZE: 12 bits */ #define REG_ALIAS_CLEAR … /* same as REG_INTR_STATUS except that only bits cleared are those selected by * REG_ALIAS_CLEAR * DEFAULT: 0x00000000, SIZE: 29 bits */ #define REG_INTR_STATUS_ALIAS … /* DEFAULT: 0x0, SIZE: 3 bits */ #define REG_PCI_ERR_STATUS … #define PCI_ERR_BADACK … #define PCI_ERR_DTRTO … #define PCI_ERR_OTHER … #define PCI_ERR_BIM_DMA_WRITE … #define PCI_ERR_BIM_DMA_READ … #define PCI_ERR_BIM_DMA_TIMEOUT … /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event * causes an interrupt to be generated. * DEFAULT: 0x7, SIZE: 3 bits */ #define REG_PCI_ERR_STATUS_MASK … /* used to configure PCI related parameters that are not in PCI config space. * DEFAULT: 0bxx000, SIZE: 5 bits */ #define REG_BIM_CFG … #define BIM_CFG_RESERVED0 … #define BIM_CFG_RESERVED1 … #define BIM_CFG_64BIT_DISABLE … #define BIM_CFG_66MHZ … #define BIM_CFG_32BIT … #define BIM_CFG_DPAR_INTR_ENABLE … #define BIM_CFG_RMA_INTR_ENABLE … #define BIM_CFG_RTA_INTR_ENABLE … #define BIM_CFG_RESERVED2 … #define BIM_CFG_BIM_DISABLE … #define BIM_CFG_BIM_STATUS … #define BIM_CFG_PERROR_BLOCK … /* DEFAULT: 0x00000000, SIZE: 32 bits */ #define REG_BIM_DIAG … #define BIM_DIAG_MSTR_SM_MASK … #define BIM_DIAG_BRST_SM_MASK … /* writing to SW_RESET_TX and SW_RESET_RX will issue a global * reset. poll until TX and RX read back as 0's for completion. */ #define REG_SW_RESET … #define SW_RESET_TX … #define SW_RESET_RX … #define SW_RESET_RSTOUT … #define SW_RESET_BLOCK_PCS_SLINK … #define SW_RESET_BREQ_SM_MASK … #define SW_RESET_PCIARB_SM_MASK … #define SW_RESET_RDPCI_SM_MASK … #define SW_RESET_RDARB_SM_MASK … #define SW_RESET_WRPCI_SM_MASK … #define SW_RESET_WRARB_SM_MASK … /* Cassini only. 64-bit register used to check PCI datapath. when read, * value written has both lower and upper 32-bit halves rotated to the right * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF */ #define REG_MINUS_BIM_DATAPATH_TEST … /* output enables are provided for each device's chip select and for the rest * of the outputs from cassini to its local bus devices. two sw programmable * bits are connected to general purpus control/status bits. * DEFAULT: 0x7 */ #define REG_BIM_LOCAL_DEV_EN … #define BIM_LOCAL_DEV_PAD … #define BIM_LOCAL_DEV_PROM … #define BIM_LOCAL_DEV_EXT … #define BIM_LOCAL_DEV_SOFT_0 … #define BIM_LOCAL_DEV_SOFT_1 … #define BIM_LOCAL_DEV_HW_RESET … /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI. * _DATA_HI should be the last access of the sequence. * DEFAULT: undefined */ #define REG_BIM_BUFFER_ADDR … #define BIM_BUFFER_ADDR_MASK … #define BIM_BUFFER_WR_SELECT … /* DEFAULT: undefined */ #define REG_BIM_BUFFER_DATA_LOW … #define REG_BIM_BUFFER_DATA_HI … /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer. * bit auto-clears when done with status read from _SUMMARY and _PASS bits. */ #define REG_BIM_RAM_BIST … #define BIM_RAM_BIST_RD_START … #define BIM_RAM_BIST_WR_START … #define BIM_RAM_BIST_RD_PASS … #define BIM_RAM_BIST_WR_PASS … #define BIM_RAM_BIST_RD_LOW_PASS … #define BIM_RAM_BIST_RD_HI_PASS … #define BIM_RAM_BIST_WR_LOW_PASS … #define BIM_RAM_BIST_WR_HI_PASS … /* ASUN: i'm not sure what this does as it's not in the spec. * DEFAULT: 0xFC */ #define REG_BIM_DIAG_MUX … /* enable probe monitoring mode and select data appearing on the P_A* bus. bit * values for _SEL_HI_MASK and _SEL_LOW_MASK: * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w, * wtc empty r, post pci) * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp, * pci rpkt comp, txdma wr req, txdma wr ack, * txdma wr rdy, txdma wr xfr done) * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd, * rd arb state, rd pci state) * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state, * wrpci state) * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8] * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24] * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40] * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56] * the following are not available in Cassini: * 0xc: rx probe[7:0] 0xd: tx probe[7:0] * 0xe: hp probe[7:0] 0xf: mac probe[7:0] */ #define REG_PLUS_PROBE_MUX_SELECT … #define PROBE_MUX_EN … #define PROBE_MUX_SUB_MUX_MASK … #define PROBE_MUX_SEL_HI_MASK … #define PROBE_MUX_SEL_LOW_MASK … /* values mean the same thing as REG_INTR_MASK excep that it's for INTB. DEFAULT: 0x1F */ #define REG_PLUS_INTR_MASK_1 … #define REG_PLUS_INTRN_MASK(x) … /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to * all of the alternate (2-4) INTR registers while _1 corresponds to only * _MASK_1 and _STATUS_1 registers. * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers */ #define INTR_RX_DONE_ALT … #define INTR_RX_COMP_FULL_ALT … #define INTR_RX_COMP_AF_ALT … #define INTR_RX_BUF_UNAVAIL_1 … #define INTR_RX_BUF_AE_1 … #define INTRN_MASK_RX_EN … #define INTRN_MASK_CLEAR_ALL … #define REG_PLUS_INTR_STATUS_1 … #define REG_PLUS_INTRN_STATUS(x) … #define INTR_STATUS_ALT_INTX_EN … #define REG_PLUS_ALIAS_CLEAR_1 … #define REG_PLUS_ALIASN_CLEAR(x) … #define REG_PLUS_INTR_STATUS_ALIAS_1 … #define REG_PLUS_INTRN_STATUS_ALIAS(x) … #define REG_SATURN_PCFG … #define SATURN_PCFG_TLA … #define SATURN_PCFG_FLA … #define SATURN_PCFG_CLA … #define SATURN_PCFG_LLA … #define SATURN_PCFG_RLA … #define SATURN_PCFG_PDS … #define SATURN_PCFG_MTP … #define SATURN_PCFG_GMO … #define SATURN_PCFG_FSI … #define SATURN_PCFG_LAD … /** transmit dma registers **/ #define MAX_TX_RINGS_SHIFT … #define MAX_TX_RINGS … #define MAX_TX_RINGS_MASK … /* TX configuration. * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8 * DEFAULT: 0x3F000001 */ #define REG_TX_CFG … #define TX_CFG_DMA_EN … #define TX_CFG_FIFO_PIO_SEL … #define TX_CFG_DESC_RING0_MASK … #define TX_CFG_DESC_RING0_SHIFT … #define TX_CFG_DESC_RINGN_MASK(a) … #define TX_CFG_DESC_RINGN_SHIFT(a) … #define TX_CFG_PACED_MODE … #define TX_CFG_DMA_RDPIPE_DIS … #define TX_CFG_COMPWB_Q1 … #define TX_CFG_COMPWB_Q2 … #define TX_CFG_COMPWB_Q3 … #define TX_CFG_COMPWB_Q4 … #define TX_CFG_INTR_COMPWB_DIS … #define TX_CFG_CTX_SEL_MASK … #define TX_CFG_CTX_SEL_SHIFT … /* 11-bit counters that point to next location in FIFO to be loaded/retrieved. * used for diagnostics only. */ #define REG_TX_FIFO_WRITE_PTR … #define REG_TX_FIFO_SHADOW_WRITE_PTR … #define REG_TX_FIFO_READ_PTR … #define REG_TX_FIFO_SHADOW_READ_PTR … /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */ #define REG_TX_FIFO_PKT_CNT … /* current state of all state machines in TX */ #define REG_TX_SM_1 … #define TX_SM_1_CHAIN_MASK … #define TX_SM_1_CSUM_MASK … #define TX_SM_1_FIFO_LOAD_MASK … #define TX_SM_1_FIFO_UNLOAD_MASK … #define TX_SM_1_CACHE_MASK … #define TX_SM_1_CBQ_ARB_MASK … #define REG_TX_SM_2 … #define TX_SM_2_COMP_WB_MASK … #define TX_SM_2_SUB_LOAD_MASK … #define TX_SM_2_KICK_MASK … /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented * while the upper 23 bits are taken from the TX descriptor */ #define REG_TX_DATA_PTR_LOW … #define REG_TX_DATA_PTR_HI … /* 13 bit registers written by driver w/ descriptor value that follows * last valid xmit descriptor. kick # and complete # values are used by * the xmit dma engine to control tx descr fetching. if > 1 valid * tx descr is available within the cache line being read, cassini will * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro. */ #define REG_TX_KICK0 … #define REG_TX_KICKN(x) … #define REG_TX_COMP0 … #define REG_TX_COMPN(x) … /* values of TX_COMPLETE_1-4 are written. each completion register * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment. * NOTE: completion reg values are only written back prior to TX_INTME and * TX_ALL interrupts. at all other times, the most up-to-date index values * should be obtained from the REG_TX_COMPLETE_# registers. * here's the layout: * offset from base addr completion # byte * 0 TX_COMPLETE_1_MSB * 1 TX_COMPLETE_1_LSB * 2 TX_COMPLETE_2_MSB * 3 TX_COMPLETE_2_LSB * 4 TX_COMPLETE_3_MSB * 5 TX_COMPLETE_3_LSB * 6 TX_COMPLETE_4_MSB * 7 TX_COMPLETE_4_LSB */ #define TX_COMPWB_SIZE … #define REG_TX_COMPWB_DB_LOW … #define REG_TX_COMPWB_DB_HI … #define TX_COMPWB_MSB_MASK … #define TX_COMPWB_MSB_SHIFT … #define TX_COMPWB_LSB_MASK … #define TX_COMPWB_LSB_SHIFT … #define TX_COMPWB_NEXT(x) … /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must * be 2KB-aligned. */ #define REG_TX_DB0_LOW … #define REG_TX_DB0_HI … #define REG_TX_DBN_LOW(x) … #define REG_TX_DBN_HI(x) … /* 16-bit registers hold weights for the weighted round-robin of the * four CBQ TX descr rings. weights correspond to # bytes xferred from * host to TXFIFO in a round of WRR arbitration. can be set * dynamically with new weights set upon completion of the current * packet transfer from host memory to TXFIFO. a dummy write to any of * these registers causes a queue1 pre-emption with all historical bw * deficit data reset to 0 (useful when congestion requires a * pre-emption/re-allocation of network bandwidth */ #define REG_TX_MAXBURST_0 … #define REG_TX_MAXBURST_1 … #define REG_TX_MAXBURST_2 … #define REG_TX_MAXBURST_3 … /* diagnostics access to any TX FIFO location. every access is 65 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit. * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if * TX FIFO data integrity is desired, TX DMA should be * disabled. _DATA_HI_Tx should be the last access of the sequence. */ #define REG_TX_FIFO_ADDR … #define REG_TX_FIFO_TAG … #define REG_TX_FIFO_DATA_LOW … #define REG_TX_FIFO_DATA_HI_T1 … #define REG_TX_FIFO_DATA_HI_T0 … #define REG_TX_FIFO_SIZE … /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST * passed for the specified memory */ #define REG_TX_RAMBIST … #define TX_RAMBIST_STATE … #define TX_RAMBIST_RAM33A_PASS … #define TX_RAMBIST_RAM32A_PASS … #define TX_RAMBIST_RAM33B_PASS … #define TX_RAMBIST_RAM32B_PASS … #define TX_RAMBIST_SUMMARY … #define TX_RAMBIST_START … /** receive dma registers **/ #define MAX_RX_DESC_RINGS … #define MAX_RX_COMP_RINGS … /* receive DMA channel configuration. default: 0x80910 * free ring size = (1 << n)*32 -> [32 - 8k] * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9 * DEFAULT: 0x80910 */ #define REG_RX_CFG … #define RX_CFG_DMA_EN … #define RX_CFG_DESC_RING_MASK … #define RX_CFG_DESC_RING_SHIFT … #define RX_CFG_COMP_RING_MASK … #define RX_CFG_COMP_RING_SHIFT … #define RX_CFG_BATCH_DIS … #define RX_CFG_SWIVEL_MASK … #define RX_CFG_SWIVEL_SHIFT … /* cassini+ only */ #define RX_CFG_DESC_RING1_MASK … #define RX_CFG_DESC_RING1_SHIFT … /* the page size register allows cassini chips to do the following with * received data: * [--------------------------------------------------------------] page * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad] * |--------------| = PAGE_SIZE_BUFFER_STRIDE * page = PAGE_SIZE * offset = PAGE_SIZE_MTU_OFF * for the above example, MTU_BUFFER_COUNT = 4. * NOTE: as is apparent, you need to ensure that the following holds: * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE * DEFAULT: 0x48002002 (8k pages) */ #define REG_RX_PAGE_SIZE … #define RX_PAGE_SIZE_MASK … #define RX_PAGE_SIZE_SHIFT … #define RX_PAGE_SIZE_MTU_COUNT_MASK … #define RX_PAGE_SIZE_MTU_COUNT_SHIFT … #define RX_PAGE_SIZE_MTU_STRIDE_MASK … #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT … #define RX_PAGE_SIZE_MTU_OFF_MASK … #define RX_PAGE_SIZE_MTU_OFF_SHIFT … /* 11-bit counter points to next location in RX FIFO to be loaded/read. * shadow write pointers enable retries in case of early receive aborts. * DEFAULT: 0x0. generated on 64-bit boundaries. */ #define REG_RX_FIFO_WRITE_PTR … #define REG_RX_FIFO_READ_PTR … #define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR … #define REG_RX_IPP_FIFO_SHADOW_READ_PTR … #define REG_RX_IPP_FIFO_READ_PTR … /* current state of RX DMA state engines + other info * DEFAULT: 0x0 */ #define REG_RX_DEBUG … #define RX_DEBUG_LOAD_STATE_MASK … #define RX_DEBUG_LM_STATE_MASK … #define RX_DEBUG_FC_STATE_MASK … #define RX_DEBUG_DATA_STATE_MASK … #define RX_DEBUG_DESC_STATE_MASK … #define RX_DEBUG_INTR_READ_PTR_MASK … #define RX_DEBUG_INTR_WRITE_PTR_MASK … /* flow control frames are emitted using two PAUSE thresholds: * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes. * PAUSE thresholds defined in terms of FIFO occupancy and may be translated * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max * value is 0x6F. * DEFAULT: 0x00078 */ #define REG_RX_PAUSE_THRESH … #define RX_PAUSE_THRESH_QUANTUM … #define RX_PAUSE_THRESH_OFF_MASK … #define RX_PAUSE_THRESH_OFF_SHIFT … #define RX_PAUSE_THRESH_ON_MASK … #define RX_PAUSE_THRESH_ON_SHIFT … /* 13-bit register used to control RX desc fetching and intr generation. if 4+ * valid RX descriptors are available, Cassini will read 4 at a time. * writing N means that all desc up to *but* excluding N are available. N must * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned. * DEFAULT: 0 on reset */ #define REG_RX_KICK … /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings. * lower 13 bits of the low register are hard-wired to 0. */ #define REG_RX_DB_LOW … #define REG_RX_DB_HI … #define REG_RX_CB_LOW … #define REG_RX_CB_HI … /* 13-bit register indicate desc used by cassini for receive frames. used * for diagnostic purposes. * DEFAULT: 0 on reset */ #define REG_RX_COMP … /* HEAD and TAIL are used to control RX desc posting and interrupt * generation. hw moves the head register to pass ownership to sw. sw * moves the tail register to pass ownership back to hw. to give all * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no * more entries are available, DMA will pause and an interrupt will be * generated to indicate no more entries are available. sw can use * this interrupt to reduce the # of times it must update the * completion tail register. * DEFAULT: 0 on reset */ #define REG_RX_COMP_HEAD … #define REG_RX_COMP_TAIL … /* values used for receive interrupt blanking. loaded each time the ISR is read * DEFAULT: 0x00000000 */ #define REG_RX_BLANK … #define RX_BLANK_INTR_PKT_MASK … #define RX_BLANK_INTR_PKT_SHIFT … #define RX_BLANK_INTR_TIME_MASK … #define RX_BLANK_INTR_TIME_SHIFT … /* values used for interrupt generation based on threshold values of how * many free desc and completion entries are available for hw use. * DEFAULT: 0x00000000 */ #define REG_RX_AE_THRESH … #define RX_AE_THRESH_FREE_MASK … #define RX_AE_THRESH_FREE_SHIFT … #define RX_AE_THRESH_COMP_MASK … #define RX_AE_THRESH_COMP_SHIFT … /* probabilities for random early drop (RED) thresholds on a FIFO threshold * basis. probability should increase when the FIFO level increases. control * packets are never dropped and not counted in stats. probability programmed * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped. * DEFAULT: 0x00000000 */ #define REG_RX_RED … #define RX_RED_4K_6K_FIFO_MASK … #define RX_RED_6K_8K_FIFO_MASK … #define RX_RED_8K_10K_FIFO_MASK … #define RX_RED_10K_12K_FIFO_MASK … /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO. * RX control FIFO = # of packets in RX FIFO. * DEFAULT: 0x0 */ #define REG_RX_FIFO_FULLNESS … #define RX_FIFO_FULLNESS_RX_FIFO_MASK … #define RX_FIFO_FULLNESS_IPP_FIFO_MASK … #define RX_FIFO_FULLNESS_RX_PKT_MASK … #define REG_RX_IPP_PACKET_COUNT … #define REG_RX_WORK_DMA_PTR_LOW … #define REG_RX_WORK_DMA_PTR_HI … /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST * START/COMPLETE is writeable. START will clear when the BIST has completed * checking all 17 RAMS. * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0 */ #define REG_RX_BIST … #define RX_BIST_32A_PASS … #define RX_BIST_33A_PASS … #define RX_BIST_32B_PASS … #define RX_BIST_33B_PASS … #define RX_BIST_32C_PASS … #define RX_BIST_33C_PASS … #define RX_BIST_IPP_32A_PASS … #define RX_BIST_IPP_33A_PASS … #define RX_BIST_IPP_32B_PASS … #define RX_BIST_IPP_33B_PASS … #define RX_BIST_IPP_32C_PASS … #define RX_BIST_IPP_33C_PASS … #define RX_BIST_CTRL_32_PASS … #define RX_BIST_CTRL_33_PASS … #define RX_BIST_REAS_26A_PASS … #define RX_BIST_REAS_26B_PASS … #define RX_BIST_REAS_27_PASS … #define RX_BIST_STATE_MASK … #define RX_BIST_SUMMARY … #define RX_BIST_START … /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read * from to retrieve packet control info. * DEFAULT: 0 */ #define REG_RX_CTRL_FIFO_WRITE_PTR … #define REG_RX_CTRL_FIFO_READ_PTR … /* receive interrupt blanking. loaded each time interrupt alias register is * read. * DEFAULT: 0x0 */ #define REG_RX_BLANK_ALIAS_READ … #define RX_BAR_INTR_PACKET_MASK … #define RX_BAR_INTR_TIME_MASK … /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset * to normal operation after diagnostics, write to address location 0x0. * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should * be the last write access of a write sequence. * DEFAULT: undefined */ #define REG_RX_FIFO_ADDR … #define REG_RX_FIFO_TAG … #define REG_RX_FIFO_DATA_LOW … #define REG_RX_FIFO_DATA_HI_T0 … #define REG_RX_FIFO_DATA_HI_T1 … /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit * accesses. HI is 7-bits with 6-bit flow id and 1 bit control * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI * should be last write access of the write sequence. * DEFAULT: undefined */ #define REG_RX_CTRL_FIFO_ADDR … #define REG_RX_CTRL_FIFO_DATA_LOW … #define REG_RX_CTRL_FIFO_DATA_MID … #define REG_RX_CTRL_FIFO_DATA_HI … #define RX_CTRL_FIFO_DATA_HI_CTRL … #define RX_CTRL_FIFO_DATA_HI_FLOW_MASK … /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO. * DEFAULT: undefined */ #define REG_RX_IPP_FIFO_ADDR … #define REG_RX_IPP_FIFO_TAG … #define REG_RX_IPP_FIFO_DATA_LOW … #define REG_RX_IPP_FIFO_DATA_HI_T0 … #define REG_RX_IPP_FIFO_DATA_HI_T1 … /* 64-bit pointer to receive data buffer in host memory used for headers and * small packets. MSB in high register. loaded by DMA state machine and * increments as DMA writes receive data. only 50 LSB are incremented. top * 13 bits taken from RX descriptor. * DEFAULT: undefined */ #define REG_RX_HEADER_PAGE_PTR_LOW … #define REG_RX_HEADER_PAGE_PTR_HI … #define REG_RX_MTU_PAGE_PTR_LOW … #define REG_RX_MTU_PAGE_PTR_HI … /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of * one of the 64 byte locations in the Batching table. LOW holds 32 LSB. * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set * to 0 for PIO access. DATA_HIGH should be last write of write sequence. * layout: * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0] * DEFAULT: undefined */ #define REG_RX_TABLE_ADDR … #define RX_TABLE_ADDR_MASK … #define REG_RX_TABLE_DATA_LOW … #define REG_RX_TABLE_DATA_MID … #define REG_RX_TABLE_DATA_HI … /* cassini+ only */ /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to * 0. same semantics as primary desc/complete rings. */ #define REG_PLUS_RX_DB1_LOW … #define REG_PLUS_RX_DB1_HI … #define REG_PLUS_RX_CB1_LOW … #define REG_PLUS_RX_CB1_HI … #define REG_PLUS_RX_CBN_LOW(x) … #define REG_PLUS_RX_CBN_HI(x) … #define REG_PLUS_RX_KICK1 … #define REG_PLUS_RX_COMP1 … #define REG_PLUS_RX_COMP1_HEAD … #define REG_PLUS_RX_COMP1_TAIL … #define REG_PLUS_RX_COMPN_HEAD(x) … #define REG_PLUS_RX_COMPN_TAIL(x) … #define REG_PLUS_RX_AE1_THRESH … #define RX_AE1_THRESH_FREE_MASK … #define RX_AE1_THRESH_FREE_SHIFT … /** header parser registers **/ /* RX parser configuration register. * DEFAULT: 0x1651004 */ #define REG_HP_CFG … #define HP_CFG_PARSE_EN … #define HP_CFG_NUM_CPU_MASK … #define HP_CFG_NUM_CPU_SHIFT … #define HP_CFG_SYN_INC_MASK … #define HP_CFG_TCP_THRESH_MASK … #define HP_CFG_TCP_THRESH_SHIFT … /* access to RX Instruction RAM. 5-bit register/counter holds addr * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI. * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access * of sequence. * DEFAULT: undefined */ #define REG_HP_INSTR_RAM_ADDR … #define HP_INSTR_RAM_ADDR_MASK … #define REG_HP_INSTR_RAM_DATA_LOW … #define HP_INSTR_RAM_LOW_OUTMASK_MASK … #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT … #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK … #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT … #define HP_INSTR_RAM_LOW_OUTEN_MASK … #define HP_INSTR_RAM_LOW_OUTEN_SHIFT … #define HP_INSTR_RAM_LOW_OUTARG_MASK … #define HP_INSTR_RAM_LOW_OUTARG_SHIFT … #define REG_HP_INSTR_RAM_DATA_MID … #define HP_INSTR_RAM_MID_OUTARG_MASK … #define HP_INSTR_RAM_MID_OUTARG_SHIFT … #define HP_INSTR_RAM_MID_OUTOP_MASK … #define HP_INSTR_RAM_MID_OUTOP_SHIFT … #define HP_INSTR_RAM_MID_FNEXT_MASK … #define HP_INSTR_RAM_MID_FNEXT_SHIFT … #define HP_INSTR_RAM_MID_FOFF_MASK … #define HP_INSTR_RAM_MID_FOFF_SHIFT … #define HP_INSTR_RAM_MID_SNEXT_MASK … #define HP_INSTR_RAM_MID_SNEXT_SHIFT … #define HP_INSTR_RAM_MID_SOFF_MASK … #define HP_INSTR_RAM_MID_SOFF_SHIFT … #define HP_INSTR_RAM_MID_OP_MASK … #define HP_INSTR_RAM_MID_OP_SHIFT … #define REG_HP_INSTR_RAM_DATA_HI … #define HP_INSTR_RAM_HI_VAL_MASK … #define HP_INSTR_RAM_HI_VAL_SHIFT … #define HP_INSTR_RAM_HI_MASK_MASK … #define HP_INSTR_RAM_HI_MASK_SHIFT … /* PIO access into RX Header parser data RAM and flow database. * 11-bit register. Data fills the LSB portion of bus if less than 32 bits. * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM. * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120] * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access * flow database. * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg * should be the last write access of the write sequence. * DEFAULT: undefined */ #define REG_HP_DATA_RAM_FDB_ADDR … #define HP_DATA_RAM_FDB_DATA_MASK … #define HP_DATA_RAM_FDB_FDB_MASK … #define REG_HP_DATA_RAM_DATA … /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64] * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0] * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64] * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0] * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]} * FLOW_DB(10) = bit 0 has value for flow valid * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0] */ #define REG_HP_FLOW_DB0 … #define REG_HP_FLOW_DBN(x) … /* diagnostics for RX Header Parser block. * ASUN: the header parser state machine register is used for diagnostics * purposes. however, the spec doesn't have any details on it. */ #define REG_HP_STATE_MACHINE … #define REG_HP_STATUS0 … #define HP_STATUS0_SAP_MASK … #define HP_STATUS0_L3_OFF_MASK … #define HP_STATUS0_LB_CPUNUM_MASK … #define HP_STATUS0_HRP_OPCODE_MASK … #define REG_HP_STATUS1 … #define HP_STATUS1_ACCUR2_MASK … #define HP_STATUS1_FLOWID_MASK … #define HP_STATUS1_TCP_OFF_MASK … #define HP_STATUS1_TCP_SIZE_MASK … #define REG_HP_STATUS2 … #define HP_STATUS2_ACCUR2_MASK … #define HP_STATUS2_CSUM_OFF_MASK … #define HP_STATUS2_ACCUR1_MASK … #define HP_STATUS2_FORCE_DROP … #define HP_STATUS2_BWO_REASSM … #define HP_STATUS2_JH_SPLIT_EN … #define HP_STATUS2_FORCE_TCP_NOCHECK … #define HP_STATUS2_DATA_MASK_ZERO … #define HP_STATUS2_FORCE_TCP_CHECK … #define HP_STATUS2_MASK_TCP_THRESH … #define HP_STATUS2_NO_ASSIST … #define HP_STATUS2_CTRL_PACKET_FLAG … #define HP_STATUS2_TCP_FLAG_CHECK … #define HP_STATUS2_SYN_FLAG … #define HP_STATUS2_TCP_CHECK … #define HP_STATUS2_TCP_NOCHECK … /* BIST for header parser(HP) and flow database memories (FDBM). set _START * to start BIST. controller clears _START on completion. _START can also * be cleared to force termination of BIST. a bit set indicates that that * memory passed its BIST. */ #define REG_HP_RAM_BIST … #define HP_RAM_BIST_HP_DATA_PASS … #define HP_RAM_BIST_HP_INSTR0_PASS … #define HP_RAM_BIST_HP_INSTR1_PASS … #define HP_RAM_BIST_HP_INSTR2_PASS … #define HP_RAM_BIST_FDBM_AGE0_PASS … #define HP_RAM_BIST_FDBM_AGE1_PASS … #define HP_RAM_BIST_FDBM_FLOWID00_PASS … #define HP_RAM_BIST_FDBM_FLOWID10_PASS … #define HP_RAM_BIST_FDBM_FLOWID20_PASS … #define HP_RAM_BIST_FDBM_FLOWID30_PASS … #define HP_RAM_BIST_FDBM_FLOWID01_PASS … #define HP_RAM_BIST_FDBM_FLOWID11_PASS … #define HP_RAM_BIST_FDBM_FLOWID21_PASS … #define HP_RAM_BIST_FDBM_FLOWID31_PASS … #define HP_RAM_BIST_FDBM_TCPSEQ_PASS … #define HP_RAM_BIST_SUMMARY … #define HP_RAM_BIST_START … /** MAC registers. **/ /* reset bits are set using a PIO write and self-cleared after the command * execution has completed. */ #define REG_MAC_TX_RESET … #define REG_MAC_RX_RESET … /* execute a pause flow control frame transmission DEFAULT: 0x0XXXX */ #define REG_MAC_SEND_PAUSE … #define MAC_SEND_PAUSE_TIME_MASK … #define MAC_SEND_PAUSE_SEND … /* bit set indicates that event occurred. auto-cleared when status register * is read and have corresponding mask bits in mask register. events will * trigger an interrupt if the corresponding mask bit is 0. * status register default: 0x00000000 * mask register default = 0xFFFFFFFF on reset */ #define REG_MAC_TX_STATUS … #define MAC_TX_FRAME_XMIT … #define MAC_TX_UNDERRUN … #define MAC_TX_MAX_PACKET_ERR … #define MAC_TX_COLL_NORMAL … #define MAC_TX_COLL_EXCESS … #define MAC_TX_COLL_LATE … #define MAC_TX_COLL_FIRST … #define MAC_TX_DEFER_TIMER … #define MAC_TX_PEAK_ATTEMPTS … #define REG_MAC_RX_STATUS … #define MAC_RX_FRAME_RECV … #define MAC_RX_OVERFLOW … #define MAC_RX_FRAME_COUNT … #define MAC_RX_ALIGN_ERR … #define MAC_RX_CRC_ERR … #define MAC_RX_LEN_ERR … #define MAC_RX_VIOL_ERR … /* DEFAULT: 0xXXXX0000 on reset */ #define REG_MAC_CTRL_STATUS … #define MAC_CTRL_PAUSE_RECEIVED … #define MAC_CTRL_PAUSE_STATE … #define MAC_CTRL_NOPAUSE_STATE … #define MAC_CTRL_PAUSE_TIME_MASK … /* layout identical to TX MAC[8:0] */ #define REG_MAC_TX_MASK … /* layout identical to RX MAC[6:0] */ #define REG_MAC_RX_MASK … /* layout identical to CTRL MAC[2:0] */ #define REG_MAC_CTRL_MASK … /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay * imposed before writes to other bits in the TX_MAC_CFG register or any of * the MAC parameters is performed. delay dependent upon time required to * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g., * the delay for a 1518-byte frame on a 100Mbps network is 125us. * alternatively, just poll TX_CFG_EN until it reads back as 0. * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should * be 0x200 (slot time of 512 bytes) */ #define REG_MAC_TX_CFG … #define MAC_TX_CFG_EN … #define MAC_TX_CFG_IGNORE_CARRIER … #define MAC_TX_CFG_IGNORE_COLL … #define MAC_TX_CFG_IPG_EN … #define MAC_TX_CFG_NEVER_GIVE_UP_EN … #define MAC_TX_CFG_NEVER_GIVE_UP_LIM … #define MAC_TX_CFG_NO_BACKOFF … #define MAC_TX_CFG_SLOW_DOWN … #define MAC_TX_CFG_NO_FCS … #define MAC_TX_CFG_CARRIER_EXTEND … /* when CRC is not stripped, reassembly packets will not contain the CRC. * these will be stripped by HRP because it reassembles layer 4 data, and the * CRC is layer 2. however, non-reassembly packets will still contain the CRC * when passed to the host. to ensure proper operation, need to wait 3.2ms * after clearing RX_CFG_EN before writing to any other RX MAC registers * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same * restrictions as CFG_EN. */ #define REG_MAC_RX_CFG … #define MAC_RX_CFG_EN … #define MAC_RX_CFG_STRIP_PAD … #define MAC_RX_CFG_STRIP_FCS … #define MAC_RX_CFG_PROMISC_EN … #define MAC_RX_CFG_PROMISC_GROUP_EN … #define MAC_RX_CFG_HASH_FILTER_EN … #define MAC_RX_CFG_ADDR_FILTER_EN … #define MAC_RX_CFG_DISABLE_DISCARD … #define MAC_RX_CFG_CARRIER_EXTEND … /* DEFAULT: 0x0 */ #define REG_MAC_CTRL_CFG … #define MAC_CTRL_CFG_SEND_PAUSE_EN … #define MAC_CTRL_CFG_RECV_PAUSE_EN … #define MAC_CTRL_CFG_PASS_CTRL … /* to ensure proper operation, a global initialization sequence should be * performed when a loopback config is entered or exited. if programmed after * a hw or global sw reset, RX/TX MAC software reset and initialization * should be done to ensure stable clocking. * DEFAULT: 0x0 */ #define REG_MAC_XIF_CFG … #define MAC_XIF_TX_MII_OUTPUT_EN … #define MAC_XIF_MII_INT_LOOPBACK … #define MAC_XIF_DISABLE_ECHO … #define MAC_XIF_GMII_MODE … #define MAC_XIF_MII_BUFFER_OUTPUT_EN … #define MAC_XIF_LINK_LED … #define MAC_XIF_FDPLX_LED … #define REG_MAC_IPG0 … #define REG_MAC_IPG1 … #define REG_MAC_IPG2 … #define REG_MAC_SLOT_TIME … #define REG_MAC_FRAMESIZE_MIN … /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size. * recommended value: 0x2000.05EE */ #define REG_MAC_FRAMESIZE_MAX … #define MAC_FRAMESIZE_MAX_BURST_MASK … #define MAC_FRAMESIZE_MAX_BURST_SHIFT … #define MAC_FRAMESIZE_MAX_FRAME_MASK … #define MAC_FRAMESIZE_MAX_FRAME_SHIFT … #define REG_MAC_PA_SIZE … #define REG_MAC_JAM_SIZE … #define REG_MAC_ATTEMPT_LIMIT … #define REG_MAC_CTRL_TYPE … /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes. * register contains comparison * 0 16 MSB of primary MAC addr [47:32] of DA field * 1 16 middle bits "" [31:16] of DA field * 2 16 LSB "" [15:0] of DA field * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field * 4*x 16 middle bits "" [31:16] * 5*x 16 LSB "" [15:0] * 42 16 MSB of MAC CTRL addr [47:32] of DA. * 43 16 middle bits "" [31:16] * 44 16 LSB "" [15:0] * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. * if there is a match, MAC will set the bit for alternative address * filter pass [15] * here is the map of registers given MAC address notation: a:b:c:d:e:f * ab cd ef * primary addr reg 2 reg 1 reg 0 * alt addr 1 reg 5 reg 4 reg 3 * alt addr x reg 5*x reg 4*x reg 3*x * ctrl addr reg 44 reg 43 reg 42 */ #define REG_MAC_ADDR0 … #define REG_MAC_ADDRN(x) … #define REG_MAC_ADDR_FILTER0 … #define REG_MAC_ADDR_FILTER1 … #define REG_MAC_ADDR_FILTER2 … #define REG_MAC_ADDR_FILTER2_1_MASK … #define REG_MAC_ADDR_FILTER0_MASK … /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes * 16-bit registers contain bits of the hash table. * reg x -> [16*(15 - x) + 15 : 16*(15 - x)]. * e.g., 15 -> [15:0], 0 -> [255:240] */ #define REG_MAC_HASH_TABLE0 … #define REG_MAC_HASH_TABLEN(x) … /* statistics registers. these registers generate an interrupt on * overflow. recommended initialization: 0x0000. most are 16-bits except * for PEAK_ATTEMPTS register which is 8 bits. */ #define REG_MAC_COLL_NORMAL … #define REG_MAC_COLL_FIRST … #define REG_MAC_COLL_EXCESS … #define REG_MAC_COLL_LATE … #define REG_MAC_TIMER_DEFER … #define REG_MAC_ATTEMPTS_PEAK … #define REG_MAC_RECV_FRAME … #define REG_MAC_LEN_ERR … #define REG_MAC_ALIGN_ERR … #define REG_MAC_FCS_ERR … #define REG_MAC_RX_CODE_ERR … /* misc registers */ #define REG_MAC_RANDOM_SEED … /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address * map */ /* 27-bit register has the current state for key state machines in the MAC */ #define REG_MAC_STATE_MACHINE … #define MAC_SM_RLM_MASK … #define MAC_SM_RLM_SHIFT … #define MAC_SM_RX_FC_MASK … #define MAC_SM_RX_FC_SHIFT … #define MAC_SM_TLM_MASK … #define MAC_SM_TLM_SHIFT … #define MAC_SM_ENCAP_SM_MASK … #define MAC_SM_ENCAP_SM_SHIFT … #define MAC_SM_TX_REQ_MASK … #define MAC_SM_TX_REQ_SHIFT … #define MAC_SM_TX_FC_MASK … #define MAC_SM_TX_FC_SHIFT … #define MAC_SM_FIFO_WRITE_SEL_MASK … #define MAC_SM_FIFO_WRITE_SEL_SHIFT … #define MAC_SM_TX_FIFO_EMPTY_MASK … #define MAC_SM_TX_FIFO_EMPTY_SHIFT … /** MIF registers. the MIF can be programmed in either bit-bang or * frame mode. **/ #define REG_MIF_BIT_BANG_CLOCK … #define REG_MIF_BIT_BANG_DATA … #define REG_MIF_BIT_BANG_OUTPUT_EN … /* 32-bit register serves as an instruction register when the MIF is * programmed in frame mode. load this register w/ a valid instruction * (as per IEEE 802.3u MII spec). poll this register to check for instruction * execution completion. during a read operation, this register will also * contain the 16-bit data returned by the tranceiver. unless specified * otherwise, fields are considered "don't care" when polling for * completion. */ #define REG_MIF_FRAME … #define MIF_FRAME_START_MASK … #define MIF_FRAME_ST … #define MIF_FRAME_OPCODE_MASK … #define MIF_FRAME_OP_READ … #define MIF_FRAME_OP_WRITE … #define MIF_FRAME_PHY_ADDR_MASK … #define MIF_FRAME_PHY_ADDR_SHIFT … #define MIF_FRAME_REG_ADDR_MASK … #define MIF_FRAME_REG_ADDR_SHIFT … #define MIF_FRAME_TURN_AROUND_MSB … #define MIF_FRAME_TURN_AROUND_LSB … #define MIF_FRAME_DATA_MASK … #define REG_MIF_CFG … #define MIF_CFG_PHY_SELECT … #define MIF_CFG_POLL_EN … #define MIF_CFG_BB_MODE … #define MIF_CFG_POLL_REG_MASK … #define MIF_CFG_POLL_REG_SHIFT … #define MIF_CFG_MDIO_0 … #define MIF_CFG_MDIO_1 … #define MIF_CFG_POLL_PHY_MASK … #define MIF_CFG_POLL_PHY_SHIFT … /* 16-bit register used to determine which bits in the POLL_STATUS portion of * the MIF_STATUS register will cause an interrupt. if a mask bit is 0, * corresponding bit of the POLL_STATUS will generate a MIF interrupt when * set. DEFAULT: 0xFFFF */ #define REG_MIF_MASK … /* 32-bit register used when in poll mode. auto-cleared after being read */ #define REG_MIF_STATUS … #define MIF_STATUS_POLL_DATA_MASK … #define MIF_STATUS_POLL_DATA_SHIFT … #define MIF_STATUS_POLL_STATUS_MASK … #define MIF_STATUS_POLL_STATUS_SHIFT … /* 7-bit register has current state for all state machines in the MIF */ #define REG_MIF_STATE_MACHINE … #define MIF_SM_CONTROL_MASK … #define MIF_SM_EXECUTION_MASK … /** PCS/Serialink. the following registers are equivalent to the standard * MII management registers except that they're directly mapped in * Cassini's register space. **/ /* the auto-negotiation enable bit should be programmed the same at * the link partner as in the local device to enable auto-negotiation to * complete. when that bit is reprogrammed, auto-neg/manual config is * restarted automatically. * DEFAULT: 0x1040 */ #define REG_PCS_MII_CTRL … #define PCS_MII_CTRL_1000_SEL … #define PCS_MII_CTRL_COLLISION_TEST … #define PCS_MII_CTRL_DUPLEX … #define PCS_MII_RESTART_AUTONEG … #define PCS_MII_ISOLATE … #define PCS_MII_POWER_DOWN … #define PCS_MII_AUTONEG_EN … #define PCS_MII_10_100_SEL … #define PCS_MII_RESET … /* DEFAULT: 0x0108 */ #define REG_PCS_MII_STATUS … #define PCS_MII_STATUS_EXTEND_CAP … #define PCS_MII_STATUS_JABBER_DETECT … #define PCS_MII_STATUS_LINK_STATUS … #define PCS_MII_STATUS_AUTONEG_ABLE … #define PCS_MII_STATUS_REMOTE_FAULT … #define PCS_MII_STATUS_AUTONEG_COMP … #define PCS_MII_STATUS_EXTEND_STATUS … /* used during auto-negotiation. * DEFAULT: 0x00E0 */ #define REG_PCS_MII_ADVERT … #define PCS_MII_ADVERT_FD … #define PCS_MII_ADVERT_HD … #define PCS_MII_ADVERT_SYM_PAUSE … #define PCS_MII_ADVERT_ASYM_PAUSE … #define PCS_MII_ADVERT_RF_MASK … #define PCS_MII_ADVERT_ACK … #define PCS_MII_ADVERT_NEXT_PAGE … /* contents updated as a result of autonegotiation. layout and definitions * identical to PCS_MII_ADVERT */ #define REG_PCS_MII_LPA … #define PCS_MII_LPA_FD … #define PCS_MII_LPA_HD … #define PCS_MII_LPA_SYM_PAUSE … #define PCS_MII_LPA_ASYM_PAUSE … #define PCS_MII_LPA_RF_MASK … #define PCS_MII_LPA_ACK … #define PCS_MII_LPA_NEXT_PAGE … /* DEFAULT: 0x0 */ #define REG_PCS_CFG … #define PCS_CFG_EN … #define PCS_CFG_SD_OVERRIDE … #define PCS_CFG_SD_ACTIVE_LOW … #define PCS_CFG_JITTER_STUDY_MASK … #define PCS_CFG_10MS_TIMER_OVERRIDE … /* used for diagnostic purposes. bits 20-22 autoclear on read */ #define REG_PCS_STATE_MACHINE … #define PCS_SM_TX_STATE_MASK … #define PCS_SM_RX_STATE_MASK … #define PCS_SM_WORD_SYNC_STATE_MASK … #define PCS_SM_SEQ_DETECT_STATE_MASK … #define PCS_SM_LINK_STATE_MASK … #define SM_LINK_STATE_UP … #define PCS_SM_LOSS_LINK_C … #define PCS_SM_LOSS_LINK_SYNC … #define PCS_SM_LOSS_SIGNAL_DETECT … #define PCS_SM_NO_LINK_BREAKLINK … #define PCS_SM_NO_LINK_SERDES … #define PCS_SM_NO_LINK_C … #define PCS_SM_NO_LINK_SYNC … #define PCS_SM_NO_LINK_WAIT_C … #define PCS_SM_NO_LINK_NO_IDLE … /* this register indicates interrupt changes in specific PCS MII status bits. * PCS_INT may be masked at the ISR level. only a single bit is implemented * for link status change. */ #define REG_PCS_INTR_STATUS … #define PCS_INTR_STATUS_LINK_CHANGE … /* control which network interface is used. no more than one bit should * be set. * DEFAULT: none */ #define REG_PCS_DATAPATH_MODE … #define PCS_DATAPATH_MODE_MII … #define PCS_DATAPATH_MODE_SERDES … /* input to serdes chip or serialink block */ #define REG_PCS_SERDES_CTRL … #define PCS_SERDES_CTRL_LOOPBACK … #define PCS_SERDES_CTRL_SYNCD_EN … #define PCS_SERDES_CTRL_LOCKREF … /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins. * should be 0x0 for normal operations. * 0b000 normal operation, PROM address[3:0] selected * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read * 0b010 rxmac req, rx ack, rx tag, rx clk shared * 0b011 txmac req, tx ack, tx tag, tx retry req * 0b100 tx tp3, tx tp2, tx tp1, tx tp0 * 0b101 R period RX, R period TX, R period HP, R period BIM * DEFAULT: 0x0 */ #define REG_PCS_SHARED_OUTPUT_SEL … #define PCS_SOS_PROM_ADDR_MASK … /* used for diagnostics. this register indicates progress of the SERDES * boot up. * 0b00 undergoing reset * 0b01 waiting 500us while lockrefn is asserted * 0b10 waiting for comma detect * 0b11 receive data is synchronized * DEFAULT: 0x0 */ #define REG_PCS_SERDES_STATE … #define PCS_SERDES_STATE_MASK … /* used for diagnostics. indicates number of packets transmitted or received. * counters rollover w/out generating an interrupt. * DEFAULT: 0x0 */ #define REG_PCS_PACKET_COUNT … #define PCS_PACKET_COUNT_TX … #define PCS_PACKET_COUNT_RX … /** LocalBus Devices. the following provides run-time access to the * Cassini's PROM ***/ #define REG_EXPANSION_ROM_RUN_START … #define REG_EXPANSION_ROM_RUN_END … #define REG_SECOND_LOCALBUS_START … #define REG_SECOND_LOCALBUS_END … /* entropy device */ #define REG_ENTROPY_START … #define REG_ENTROPY_DATA … #define REG_ENTROPY_STATUS … #define ENTROPY_STATUS_DRDY … #define ENTROPY_STATUS_BUSY … #define ENTROPY_STATUS_CIPHER … #define ENTROPY_STATUS_BYPASS_MASK … #define REG_ENTROPY_MODE … #define ENTROPY_MODE_KEY_MASK … #define ENTROPY_MODE_ENCRYPT … #define REG_ENTROPY_RAND_REG … #define REG_ENTROPY_RESET … #define ENTROPY_RESET_DES_IO … #define ENTROPY_RESET_STC_MODE … #define ENTROPY_RESET_KEY_CACHE … #define ENTROPY_RESET_IV … #define REG_ENTROPY_IV … #define REG_ENTROPY_KEY0 … #define REG_ENTROPY_KEYN(x) … /* phys of interest w/ their special mii registers */ #define PHY_LUCENT_B0 … #define LUCENT_MII_REG … #define PHY_NS_DP83065 … #define DP83065_MII_MEM … #define DP83065_MII_REGD … #define DP83065_MII_REGE … #define PHY_BROADCOM_5411 … #define PHY_BROADCOM_B0 … #define BROADCOM_MII_REG4 … #define BROADCOM_MII_REG5 … #define BROADCOM_MII_REG7 … #define BROADCOM_MII_REG8 … #define CAS_MII_ANNPTR … #define CAS_MII_ANNPRR … #define CAS_MII_1000_CTRL … #define CAS_MII_1000_STATUS … #define CAS_MII_1000_EXTEND … #define CAS_BMSR_1000_EXTEND … /* * if autoneg is disabled, here's the table: * BMCR_SPEED100 = 100Mbps * BMCR_SPEED1000 = 1000Mbps * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps */ #define CAS_BMCR_SPEED1000 … #define CAS_ADVERTISE_1000HALF … #define CAS_ADVERTISE_1000FULL … #define CAS_ADVERTISE_PAUSE … #define CAS_ADVERTISE_ASYM_PAUSE … /* regular lpa register */ #define CAS_LPA_PAUSE … #define CAS_LPA_ASYM_PAUSE … /* 1000_STATUS register */ #define CAS_LPA_1000HALF … #define CAS_LPA_1000FULL … #define CAS_EXTEND_1000XFULL … #define CAS_EXTEND_1000XHALF … #define CAS_EXTEND_1000TFULL … #define CAS_EXTEND_1000THALF … /* cassini header parser firmware */ cas_hp_inst_t; /* comparison */ #define OP_EQ … #define OP_LT … #define OP_GT … #define OP_NP … /* output opcodes */ #define CL_REG … #define LD_FID … #define LD_SEQ … #define LD_CTL … #define LD_SAP … #define LD_R1 … #define LD_L3 … #define LD_SUM … #define LD_HDR … #define IM_FID … #define IM_SEQ … #define IM_SAP … #define IM_R1 … #define IM_CTL … #define LD_LEN … #define ST_FLG … /* match setp #s for IP4TCP4 */ #define S1_PCKT … #define S1_VLAN … #define S1_CFI … #define S1_8023 … #define S1_LLC … #define S1_LLCc … #define S1_IPV4 … #define S1_IPV4c … #define S1_IPV4F … #define S1_TCP44 … #define S1_IPV6 … #define S1_IPV6L … #define S1_IPV6c … #define S1_TCP64 … #define S1_TCPSQ … #define S1_TCPFG … #define S1_TCPHL … #define S1_TCPHc … #define S1_CLNP … #define S1_CLNP2 … #define S1_DROP … #define S2_HTTP … #define S1_ESP4 … #define S1_AH4 … #define S1_ESP6 … #define S1_AH6 … #define CAS_PROG_IP46TCP4_PREAMBLE … #ifdef USE_HP_IP46TCP4 static cas_hp_inst_t cas_prog_ip46tcp4tab[] = { CAS_PROG_IP46TCP4_PREAMBLE, { "TCP seq", /* DADDR should point to dest port */ 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, IM_CTL, 0x001, 3, 0x0, 0x0001}, { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x000, 0, 0x0, 0x0000}, { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff}, { NULL }, }; #ifdef HP_IP46TCP4_DEFAULT #define CAS_HP_FIRMWARE … #endif #endif /* * Alternate table load which excludes HTTP server traffic from reassembly. * It is substantially similar to the basic table, with one extra state * and a few extra compares. */ #ifdef USE_HP_IP46TCP4NOHTTP static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = { CAS_PROG_IP46TCP4_PREAMBLE, { "TCP seq", /* DADDR should point to dest port */ 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */ { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */ { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, IM_CTL, 0x001, 3, 0x0, 0x0001}, { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, CL_REG, 0x002, 3, 0x0, 0x0000}, { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff}, { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x044, 3, 0x0, 0xffff}, { NULL }, }; #ifdef HP_IP46TCP4NOHTTP_DEFAULT #define CAS_HP_FIRMWARE … #endif #endif /* match step #s for IP4FRAG */ #define S3_IPV6c … #define S3_TCP64 … #define S3_TCPSQ … #define S3_TCPFG … #define S3_TCPHL … #define S3_TCPHc … #define S3_FRAG … #define S3_FOFF … #define S3_CLNP … #ifdef USE_HP_IP4FRAG static cas_hp_inst_t cas_prog_ip4fragtab[] = { { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000}, { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, IM_CTL, 0x00a, 3, 0x0, 0xffff}, { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x0000}, { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, CL_REG, 0x000, 0, 0x0, 0x0000}, { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP, CL_REG, 0x000, 0, 0x0, 0x0000}, { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP, CL_REG, 0x000, 0, 0x0, 0x0000}, { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, LD_SAP, 0x100, 3, 0x0, 0xffff}, { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP, LD_SUM, 0x00a, 1, 0x0, 0x0000}, { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG, LD_LEN, 0x03e, 3, 0x0, 0xffff}, { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP, LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP, LD_SUM, 0x015, 1, 0x0, 0x0000}, { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP, LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP, LD_LEN, 0x03f, 1, 0x0, 0xffff}, { "TCP seq", /* DADDR should point to dest port */ 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ, 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0, S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */ { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, LD_SEQ, 0x040, 1, 0xD, 0xfff8}, { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x001, 3, 0x0, 0x0001}, { NULL }, }; #ifdef HP_IP4FRAG_DEFAULT #define CAS_HP_FIRMWARE … #endif #endif /* * Alternate table which does batching without reassembly */ #ifdef USE_HP_IP46TCP4BATCH static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = { CAS_PROG_IP46TCP4_PREAMBLE, { "TCP seq", /* DADDR should point to dest port */ 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ, 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */ { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */ { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x001, 3, 0x0, 0x0001}, { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff}, { NULL }, }; #ifdef HP_IP46TCP4BATCH_DEFAULT #define CAS_HP_FIRMWARE … #endif #endif /* Workaround for Cassini rev2 descriptor corruption problem. * Does batching without reassembly, and sets the SAP to a known * data pattern for all packets. */ #ifdef USE_HP_WORKAROUND static cas_hp_inst_t cas_prog_workaroundtab[] = …; #ifdef HP_WORKAROUND_DEFAULT #define CAS_HP_FIRMWARE … #endif #endif #ifdef USE_HP_ENCRYPT static cas_hp_inst_t cas_prog_encryptiontab[] = { { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000}, { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, IM_CTL, 0x00a, 3, 0x0, 0xffff}, #if 0 //"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */ //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00 00, #endif { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */ 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x0000}, { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, CL_REG, 0x000, 0, 0x0, 0x0000}, { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, CL_REG, 0x000, 0, 0x0, 0x0000}, { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, CL_REG, 0x000, 0, 0x0, 0x0000}, { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, LD_SAP, 0x100, 3, 0x0, 0xffff}, { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, LD_SUM, 0x00a, 1, 0x0, 0x0000}, { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, LD_LEN, 0x03e, 1, 0x0, 0xffff}, { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4, LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, LD_SUM, 0x015, 1, 0x0, 0x0000}, { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, IM_R1, 0x128, 1, 0x0, 0xffff}, { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ { "TCP64?", #if 0 //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff, #endif 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff}, { "TCP seq", /* 14:DADDR should point to dest port */ 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */ { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000} , { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, IM_CTL, 0x001, 3, 0x0, 0x0001}, { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, CL_REG, 0x002, 3, 0x0, 0x0000}, { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff}, { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, IM_CTL, 0x044, 3, 0x0, 0xffff}, { "IPV4 ESP encrypted?", /* S1_ESP4 */ 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL, 0x021, 1, 0x0, 0xffff}, { "IPV4 AH encrypted?", /* S1_AH4 */ 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff}, { "IPV6 ESP encrypted?", /* S1_ESP6 */ #if 0 //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff, #endif 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff}, { "IPV6 AH encrypted?", /* S1_AH6 */ #if 0 //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff, #endif 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff}, { NULL }, }; #ifdef HP_ENCRYPT_DEFAULT #define CAS_HP_FIRMWARE … #endif #endif static cas_hp_inst_t cas_prog_null[] = …; #ifdef HP_NULL_DEFAULT #define CAS_HP_FIRMWARE … #endif /* phy types */ #define CAS_PHY_UNKNOWN … #define CAS_PHY_SERDES … #define CAS_PHY_MII_MDIO0 … #define CAS_PHY_MII_MDIO1 … #define CAS_PHY_MII(x) … /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE * is the actual size. the default index for the various rings is * 8. NOTE: there a bunch of alignment constraints for the rings. to * deal with that, i just allocate rings to create the desired * alignment. here are the constraints: * RX DESC and COMP rings must be 8KB aligned * TX DESC must be 2KB aligned. * if you change the numbers, be cognizant of how the alignment will change * in INIT_BLOCK as well. */ #define DESC_RING_I_TO_S(x) … #define COMP_RING_I_TO_S(x) … #define TX_DESC_RING_INDEX … #define RX_DESC_RING_INDEX … #define RX_COMP_RING_INDEX … #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0) #error TX_DESC_RING_INDEX must be between 0 and 8 #endif #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0) #error RX_DESC_RING_INDEX must be between 0 and 8 #endif #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0) #error RX_COMP_RING_INDEX must be between 0 and 8 #endif #define N_TX_RINGS … #define N_TX_RINGS_MASK … #define N_RX_DESC_RINGS … #define N_RX_COMP_RINGS … /* number of flows that can go through re-assembly */ #define N_RX_FLOWS … #define TX_DESC_RING_SIZE … #define RX_DESC_RING_SIZE … #define RX_COMP_RING_SIZE … #define TX_DESC_RINGN_INDEX(x) … #define RX_DESC_RINGN_INDEX(x) … #define RX_COMP_RINGN_INDEX(x) … #define TX_DESC_RINGN_SIZE(x) … #define RX_DESC_RINGN_SIZE(x) … #define RX_COMP_RINGN_SIZE(x) … /* convert values */ #define CAS_BASE(x, y) … #define CAS_VAL(x, y) … #define CAS_TX_RINGN_BASE(y) … /* min is 2k, but we can't do jumbo frames unless it's at least 8k */ #define CAS_MIN_PAGE_SHIFT … #define CAS_JUMBO_PAGE_SHIFT … #define CAS_MAX_PAGE_SHIFT … #define TX_DESC_BUFLEN_MASK … #define TX_DESC_BUFLEN_SHIFT … #define TX_DESC_CSUM_START_MASK … #define TX_DESC_CSUM_START_SHIFT … #define TX_DESC_CSUM_STUFF_MASK … #define TX_DESC_CSUM_STUFF_SHIFT … #define TX_DESC_CSUM_EN … #define TX_DESC_EOF … #define TX_DESC_SOF … #define TX_DESC_INTME … #define TX_DESC_NO_CRC … struct cas_tx_desc { … }; /* descriptor ring for free buffers contains page-sized buffers. the index * value is not used by the hw in any way. it's just stored and returned in * the completion ring. */ struct cas_rx_desc { … }; /* received packets are put on the completion ring. */ /* word 1 */ #define RX_COMP1_DATA_SIZE_MASK … #define RX_COMP1_DATA_SIZE_SHIFT … #define RX_COMP1_DATA_OFF_MASK … #define RX_COMP1_DATA_OFF_SHIFT … #define RX_COMP1_DATA_INDEX_MASK … #define RX_COMP1_DATA_INDEX_SHIFT … #define RX_COMP1_SKIP_MASK … #define RX_COMP1_SKIP_SHIFT … #define RX_COMP1_RELEASE_NEXT … #define RX_COMP1_SPLIT_PKT … #define RX_COMP1_RELEASE_FLOW … #define RX_COMP1_RELEASE_DATA … #define RX_COMP1_RELEASE_HDR … #define RX_COMP1_TYPE_MASK … #define RX_COMP1_TYPE_SHIFT … /* word 2 */ #define RX_COMP2_NEXT_INDEX_MASK … #define RX_COMP2_NEXT_INDEX_SHIFT … #define RX_COMP2_HDR_SIZE_MASK … #define RX_COMP2_HDR_SIZE_SHIFT … #define RX_COMP2_HDR_OFF_MASK … #define RX_COMP2_HDR_OFF_SHIFT … #define RX_COMP2_HDR_INDEX_MASK … #define RX_COMP2_HDR_INDEX_SHIFT … /* word 3 */ #define RX_COMP3_SMALL_PKT … #define RX_COMP3_JUMBO_PKT … #define RX_COMP3_JUMBO_HDR_SPLIT_EN … #define RX_COMP3_CSUM_START_MASK … #define RX_COMP3_CSUM_START_SHIFT … #define RX_COMP3_FLOWID_MASK … #define RX_COMP3_FLOWID_SHIFT … #define RX_COMP3_OPCODE_MASK … #define RX_COMP3_OPCODE_SHIFT … #define RX_COMP3_FORCE_FLAG … #define RX_COMP3_NO_ASSIST … #define RX_COMP3_LOAD_BAL_MASK … #define RX_COMP3_LOAD_BAL_SHIFT … #define RX_PLUS_COMP3_ENC_PKT … #define RX_COMP3_L3_HEAD_OFF_MASK … #define RX_COMP3_L3_HEAD_OFF_SHIFT … #define RX_PLUS_COMP_L3_HEAD_OFF_MASK … #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT … #define RX_COMP3_SAP_MASK … #define RX_COMP3_SAP_SHIFT … /* word 4 */ #define RX_COMP4_TCP_CSUM_MASK … #define RX_COMP4_TCP_CSUM_SHIFT … #define RX_COMP4_PKT_LEN_MASK … #define RX_COMP4_PKT_LEN_SHIFT … #define RX_COMP4_PERFECT_MATCH_MASK … #define RX_COMP4_PERFECT_MATCH_SHIFT … #define RX_COMP4_ZERO … #define RX_COMP4_HASH_VAL_MASK … #define RX_COMP4_HASH_VAL_SHIFT … #define RX_COMP4_HASH_PASS … #define RX_COMP4_BAD … #define RX_COMP4_LEN_MISMATCH … /* we encode the following: ring/index/release. only 14 bits * are usable. * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and * MAX_RX_DESC_RINGS. */ #define RX_INDEX_NUM_MASK … #define RX_INDEX_NUM_SHIFT … #define RX_INDEX_RING_MASK … #define RX_INDEX_RING_SHIFT … #define RX_INDEX_RELEASE … struct cas_rx_comp { … }; enum link_state { … }; cas_page_t; /* some alignment constraints: * TX DESC, RX DESC, and RX COMP must each be 8K aligned. * TX COMPWB must be 8-byte aligned. * to accomplish this, here's what we do: * * INIT_BLOCK_RX_COMP = 64k (already aligned) * INIT_BLOCK_RX_DESC = 8k * INIT_BLOCK_TX = 8k * INIT_BLOCK_RX1_DESC = 8k * TX COMPWB */ #define INIT_BLOCK_TX … #define INIT_BLOCK_RX_DESC … #define INIT_BLOCK_RX_COMP … struct cas_init_block { … }; /* tiny buffers to deal with target abort issue. we allocate a bit * over so that we don't have target abort issues with these buffers * as well. */ #define TX_TINY_BUF_LEN … #define TX_TINY_BUF_BLOCK … struct cas_tiny_count { … }; struct cas { … }; #define TX_DESC_NEXT(r, x) … #define RX_DESC_ENTRY(r, x) … #define RX_COMP_ENTRY(r, x) … #define TX_BUFF_COUNT(r, x, y) … #define TX_BUFFS_AVAIL(cp, i) … #define CAS_ALIGN(addr, align) … #define RX_FIFO_SIZE … #define EXPANSION_ROM_SIZE … #define CAS_MC_EXACT_MATCH_SIZE … #define CAS_MC_HASH_SIZE … #define CAS_MC_HASH_MAX … #define TX_TARGET_ABORT_LEN … #define RX_SWIVEL_OFF_VAL … #define RX_AE_FREEN_VAL(x) … #define RX_AE_COMP_VAL … #define RX_BLANK_INTR_PKT_VAL … #define RX_BLANK_INTR_TIME_VAL … #define HP_TCP_THRESH_VAL … #define RX_SPARE_COUNT … #define RX_SPARE_RECOVER_VAL … #endif /* _CASSINI_H */
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