/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ #ifndef _TXGBE_TYPE_H_ #define _TXGBE_TYPE_H_ #include <linux/property.h> #include <linux/irq.h> /* Device IDs */ #define TXGBE_DEV_ID_SP1000 … #define TXGBE_DEV_ID_WX1820 … /* Subsystem IDs */ /* SFP */ #define TXGBE_ID_SP1000_SFP … #define TXGBE_ID_WX1820_SFP … #define TXGBE_ID_SFP … /* copper */ #define TXGBE_ID_SP1000_XAUI … #define TXGBE_ID_WX1820_XAUI … #define TXGBE_ID_XAUI … #define TXGBE_ID_SP1000_SGMII … #define TXGBE_ID_WX1820_SGMII … #define TXGBE_ID_SGMII … /* backplane */ #define TXGBE_ID_SP1000_KR_KX_KX4 … #define TXGBE_ID_WX1820_KR_KX_KX4 … #define TXGBE_ID_KR_KX_KX4 … /* MAC Interface */ #define TXGBE_ID_SP1000_MAC_XAUI … #define TXGBE_ID_WX1820_MAC_XAUI … #define TXGBE_ID_MAC_XAUI … #define TXGBE_ID_SP1000_MAC_SGMII … #define TXGBE_ID_WX1820_MAC_SGMII … #define TXGBE_ID_MAC_SGMII … /* Combined interface*/ #define TXGBE_ID_SFI_XAUI … /* Revision ID */ #define TXGBE_SP_MPW … /**************** SP Registers ****************************/ /* chip control Registers */ #define TXGBE_MIS_PRB_CTL … #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) … /* FMGR Registers */ #define TXGBE_SPI_ILDR_STATUS … #define TXGBE_SPI_ILDR_STATUS_PERST … #define TXGBE_SPI_ILDR_STATUS_PWRRST … #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) … /* Sensors for PVT(Process Voltage Temperature) */ #define TXGBE_TS_CTL … #define TXGBE_TS_CTL_EVAL_MD … /* GPIO register bit */ #define TXGBE_GPIOBIT_0 … #define TXGBE_GPIOBIT_1 … #define TXGBE_GPIOBIT_2 … #define TXGBE_GPIOBIT_3 … #define TXGBE_GPIOBIT_4 … #define TXGBE_GPIOBIT_5 … /* Extended Interrupt Enable Set */ #define TXGBE_PX_MISC_ETH_LKDN … #define TXGBE_PX_MISC_DEV_RST … #define TXGBE_PX_MISC_ETH_EVENT … #define TXGBE_PX_MISC_ETH_LK … #define TXGBE_PX_MISC_ETH_AN … #define TXGBE_PX_MISC_INT_ERR … #define TXGBE_PX_MISC_GPIO … #define TXGBE_PX_MISC_IEN_MASK … /* Port cfg registers */ #define TXGBE_CFG_PORT_ST … #define TXGBE_CFG_PORT_ST_LINK_UP … /* I2C registers */ #define TXGBE_I2C_BASE … /************************************** ETH PHY ******************************/ #define TXGBE_XPCS_IDA_ADDR … #define TXGBE_XPCS_IDA_DATA … /********************************* Flow Director *****************************/ #define TXGBE_RDB_FDIR_DROP_QUEUE … #define TXGBE_RDB_FDIR_CTL … #define TXGBE_RDB_FDIR_CTL_INIT_DONE … #define TXGBE_RDB_FDIR_CTL_PERFECT_MATCH … #define TXGBE_RDB_FDIR_CTL_DROP_Q(v) … #define TXGBE_RDB_FDIR_CTL_HASH_BITS(v) … #define TXGBE_RDB_FDIR_CTL_MAX_LENGTH(v) … #define TXGBE_RDB_FDIR_CTL_FULL_THRESH(v) … #define TXGBE_RDB_FDIR_IP6(_i) … #define TXGBE_RDB_FDIR_SA … #define TXGBE_RDB_FDIR_DA … #define TXGBE_RDB_FDIR_PORT … #define TXGBE_RDB_FDIR_PORT_DESTINATION_SHIFT … #define TXGBE_RDB_FDIR_FLEX … #define TXGBE_RDB_FDIR_FLEX_FLEX_SHIFT … #define TXGBE_RDB_FDIR_HASH … #define TXGBE_RDB_FDIR_HASH_SIG_SW_INDEX(v) … #define TXGBE_RDB_FDIR_HASH_BUCKET_VALID … #define TXGBE_RDB_FDIR_CMD … #define TXGBE_RDB_FDIR_CMD_CMD_MASK … #define TXGBE_RDB_FDIR_CMD_CMD(v) … #define TXGBE_RDB_FDIR_CMD_CMD_ADD_FLOW … #define TXGBE_RDB_FDIR_CMD_CMD_REMOVE_FLOW … #define TXGBE_RDB_FDIR_CMD_CMD_QUERY_REM_FILT … #define TXGBE_RDB_FDIR_CMD_FILTER_VALID … #define TXGBE_RDB_FDIR_CMD_FILTER_UPDATE … #define TXGBE_RDB_FDIR_CMD_FLOW_TYPE(v) … #define TXGBE_RDB_FDIR_CMD_DROP … #define TXGBE_RDB_FDIR_CMD_LAST … #define TXGBE_RDB_FDIR_CMD_QUEUE_EN … #define TXGBE_RDB_FDIR_CMD_RX_QUEUE(v) … #define TXGBE_RDB_FDIR_CMD_VT_POOL(v) … #define TXGBE_RDB_FDIR_DA4_MSK … #define TXGBE_RDB_FDIR_SA4_MSK … #define TXGBE_RDB_FDIR_TCP_MSK … #define TXGBE_RDB_FDIR_UDP_MSK … #define TXGBE_RDB_FDIR_SCTP_MSK … #define TXGBE_RDB_FDIR_HKEY … #define TXGBE_RDB_FDIR_SKEY … #define TXGBE_RDB_FDIR_OTHER_MSK … #define TXGBE_RDB_FDIR_OTHER_MSK_POOL … #define TXGBE_RDB_FDIR_OTHER_MSK_L4P … #define TXGBE_RDB_FDIR_FLEX_CFG(_i) … #define TXGBE_RDB_FDIR_FLEX_CFG_FIELD0 … #define TXGBE_RDB_FDIR_FLEX_CFG_BASE_MAC … #define TXGBE_RDB_FDIR_FLEX_CFG_MSK … #define TXGBE_RDB_FDIR_FLEX_CFG_OFST(v) … /* Checksum and EEPROM pointers */ #define TXGBE_EEPROM_LAST_WORD … #define TXGBE_EEPROM_CHECKSUM … #define TXGBE_EEPROM_SUM … #define TXGBE_EEPROM_VERSION_L … #define TXGBE_EEPROM_VERSION_H … #define TXGBE_ISCSI_BOOT_CONFIG … #define TXGBE_MAX_MSIX_VECTORS … #define TXGBE_MAX_FDIR_INDICES … #define TXGBE_MAX_RSS_INDICES … #define TXGBE_MAX_RX_QUEUES … #define TXGBE_MAX_TX_QUEUES … #define TXGBE_SP_MAX_TX_QUEUES … #define TXGBE_SP_MAX_RX_QUEUES … #define TXGBE_SP_RAR_ENTRIES … #define TXGBE_SP_MC_TBL_SIZE … #define TXGBE_SP_VFT_TBL_SIZE … #define TXGBE_SP_RX_PB_SIZE … #define TXGBE_SP_TDB_PB_SZ … #define TXGBE_DEFAULT_ATR_SAMPLE_RATE … /* Software ATR hash keys */ #define TXGBE_ATR_BUCKET_HASH_KEY … #define TXGBE_ATR_SIGNATURE_HASH_KEY … /* Software ATR input stream values and masks */ #define TXGBE_ATR_HASH_MASK … #define TXGBE_ATR_L4TYPE_MASK … #define TXGBE_ATR_L4TYPE_UDP … #define TXGBE_ATR_L4TYPE_TCP … #define TXGBE_ATR_L4TYPE_SCTP … #define TXGBE_ATR_L4TYPE_IPV6_MASK … #define TXGBE_ATR_L4TYPE_TUNNEL_MASK … enum txgbe_atr_flow_type { … }; /* Flow Director ATR input struct. */ txgbe_atr_input; /* Flow Director compressed ATR hash input struct */ txgbe_atr_hash_dword; enum txgbe_fdir_pballoc_type { … }; struct txgbe_fdir_filter { … }; /* TX/RX descriptor defines */ #define TXGBE_DEFAULT_TXD … #define TXGBE_DEFAULT_TX_WORK … #if (PAGE_SIZE < 8192) #define TXGBE_DEFAULT_RXD … #define TXGBE_DEFAULT_RX_WORK … #else #define TXGBE_DEFAULT_RXD … #define TXGBE_DEFAULT_RX_WORK … #endif #define TXGBE_INTR_MISC … #define TXGBE_INTR_QALL(A) … #define TXGBE_MAX_EITR … extern char txgbe_driver_name[]; void txgbe_down(struct wx *wx); void txgbe_up(struct wx *wx); int txgbe_setup_tc(struct net_device *dev, u8 tc); void txgbe_do_reset(struct net_device *netdev); #define NODE_PROP(_NAME, _PROP) … enum txgbe_swnodes { … }; struct txgbe_nodes { … }; enum txgbe_misc_irqs { … }; struct txgbe_irq { … }; struct txgbe { … }; #endif /* _TXGBE_TYPE_H_ */
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