/* SPDX-License-Identifier: GPL-2.0 */ #ifndef XILINX_LL_TEMAC_H #define XILINX_LL_TEMAC_H #include <linux/netdevice.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/spinlock.h> #ifdef CONFIG_PPC_DCR #include <asm/dcr.h> #include <asm/dcr-regs.h> #endif /* packet size info */ #define XTE_HDR_SIZE … #define XTE_TRL_SIZE … #define XTE_JUMBO_MTU … #define XTE_MAX_JUMBO_FRAME_SIZE … /* Configuration options */ /* Accept all incoming packets. * This option defaults to disabled (cleared) */ #define XTE_OPTION_PROMISC … /* Jumbo frame support for Tx & Rx. * This option defaults to disabled (cleared) */ #define XTE_OPTION_JUMBO … /* VLAN Rx & Tx frame support. * This option defaults to disabled (cleared) */ #define XTE_OPTION_VLAN … /* Enable recognition of flow control frames on Rx * This option defaults to enabled (set) */ #define XTE_OPTION_FLOW_CONTROL … /* Strip FCS and PAD from incoming frames. * Note: PAD from VLAN frames is not stripped. * This option defaults to disabled (set) */ #define XTE_OPTION_FCS_STRIP … /* Generate FCS field and add PAD automatically for outgoing frames. * This option defaults to enabled (set) */ #define XTE_OPTION_FCS_INSERT … /* Enable Length/Type error checking for incoming frames. When this option is * set, the MAC will filter frames that have a mismatched type/length field * and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these * types of frames are encountered. When this option is cleared, the MAC will * allow these types of frames to be received. * This option defaults to enabled (set) */ #define XTE_OPTION_LENTYPE_ERR … /* Enable the transmitter. * This option defaults to enabled (set) */ #define XTE_OPTION_TXEN … /* Enable the receiver * This option defaults to enabled (set) */ #define XTE_OPTION_RXEN … /* Default options set when device is initialized or reset */ #define XTE_OPTION_DEFAULTS … /* XPS_LL_TEMAC SDMA registers definition */ #define TX_NXTDESC_PTR … #define TX_CURBUF_ADDR … #define TX_CURBUF_LENGTH … #define TX_CURDESC_PTR … #define TX_TAILDESC_PTR … #define TX_CHNL_CTRL … /* * 0:7 24:31 IRQTimeout * 8:15 16:23 IRQCount * 16:20 11:15 Reserved * 21 10 0 * 22 9 UseIntOnEnd * 23 8 LdIRQCnt * 24 7 IRQEn * 25:28 3:6 Reserved * 29 2 IrqErrEn * 30 1 IrqDlyEn * 31 0 IrqCoalEn */ #define CHNL_CTRL_IRQ_IOE … #define CHNL_CTRL_IRQ_EN … #define CHNL_CTRL_IRQ_ERR_EN … #define CHNL_CTRL_IRQ_DLY_EN … #define CHNL_CTRL_IRQ_COAL_EN … #define TX_IRQ_REG … /* * 0:7 24:31 DltTmrValue * 8:15 16:23 ClscCntrValue * 16:17 14:15 Reserved * 18:21 10:13 ClscCnt * 22:23 8:9 DlyCnt * 24:28 3::7 Reserved * 29 2 ErrIrq * 30 1 DlyIrq * 31 0 CoalIrq */ #define TX_CHNL_STS … /* * 0:9 22:31 Reserved * 10 21 TailPErr * 11 20 CmpErr * 12 19 AddrErr * 13 18 NxtPErr * 14 17 CurPErr * 15 16 BsyWr * 16:23 8:15 Reserved * 24 7 Error * 25 6 IOE * 26 5 SOE * 27 4 Cmplt * 28 3 SOP * 29 2 EOP * 30 1 EngBusy * 31 0 Reserved */ #define RX_NXTDESC_PTR … #define RX_CURBUF_ADDR … #define RX_CURBUF_LENGTH … #define RX_CURDESC_PTR … #define RX_TAILDESC_PTR … #define RX_CHNL_CTRL … /* * 0:7 24:31 IRQTimeout * 8:15 16:23 IRQCount * 16:20 11:15 Reserved * 21 10 0 * 22 9 UseIntOnEnd * 23 8 LdIRQCnt * 24 7 IRQEn * 25:28 3:6 Reserved * 29 2 IrqErrEn * 30 1 IrqDlyEn * 31 0 IrqCoalEn */ #define RX_IRQ_REG … #define IRQ_COAL … #define IRQ_DLY … #define IRQ_ERR … #define IRQ_DMAERR … /* * 0:7 24:31 DltTmrValue * 8:15 16:23 ClscCntrValue * 16:17 14:15 Reserved * 18:21 10:13 ClscCnt * 22:23 8:9 DlyCnt * 24:28 3::7 Reserved */ #define RX_CHNL_STS … #define CHNL_STS_ENGBUSY … #define CHNL_STS_EOP … #define CHNL_STS_SOP … #define CHNL_STS_CMPLT … #define CHNL_STS_SOE … #define CHNL_STS_IOE … #define CHNL_STS_ERR … #define CHNL_STS_BSYWR … #define CHNL_STS_CURPERR … #define CHNL_STS_NXTPERR … #define CHNL_STS_ADDRERR … #define CHNL_STS_CMPERR … #define CHNL_STS_TAILERR … /* * 0:9 22:31 Reserved * 10 21 TailPErr * 11 20 CmpErr * 12 19 AddrErr * 13 18 NxtPErr * 14 17 CurPErr * 15 16 BsyWr * 16:23 8:15 Reserved * 24 7 Error * 25 6 IOE * 26 5 SOE * 27 4 Cmplt * 28 3 SOP * 29 2 EOP * 30 1 EngBusy * 31 0 Reserved */ #define DMA_CONTROL_REG … #define DMA_CONTROL_RST … #define DMA_TAIL_ENABLE … /* XPS_LL_TEMAC direct registers definition */ #define XTE_RAF0_OFFSET … #define RAF0_RST … #define RAF0_MCSTREJ … #define RAF0_BCSTREJ … #define XTE_TPF0_OFFSET … #define XTE_IFGP0_OFFSET … #define XTE_ISR0_OFFSET … #define ISR0_HARDACSCMPLT … #define ISR0_AUTONEG … #define ISR0_RXCMPLT … #define ISR0_RXREJ … #define ISR0_RXFIFOOVR … #define ISR0_TXCMPLT … #define ISR0_RXDCMLCK … #define XTE_IPR0_OFFSET … #define XTE_IER0_OFFSET … #define XTE_MSW0_OFFSET … #define XTE_LSW0_OFFSET … #define XTE_CTL0_OFFSET … #define XTE_RDY0_OFFSET … #define XTE_RSE_MIIM_RR_MASK … #define XTE_RSE_MIIM_WR_MASK … #define XTE_RSE_CFG_RR_MASK … #define XTE_RSE_CFG_WR_MASK … #define XTE_RDY0_HARD_ACS_RDY_MASK … /* XPS_LL_TEMAC indirect registers offset definition */ #define XTE_RXC0_OFFSET … #define XTE_RXC1_OFFSET … #define XTE_RXC1_RXRST_MASK … #define XTE_RXC1_RXJMBO_MASK … #define XTE_RXC1_RXFCS_MASK … #define XTE_RXC1_RXEN_MASK … #define XTE_RXC1_RXVLAN_MASK … #define XTE_RXC1_RXHD_MASK … #define XTE_RXC1_RXLT_MASK … #define XTE_TXC_OFFSET … #define XTE_TXC_TXRST_MASK … #define XTE_TXC_TXJMBO_MASK … #define XTE_TXC_TXFCS_MASK … #define XTE_TXC_TXEN_MASK … #define XTE_TXC_TXVLAN_MASK … #define XTE_TXC_TXHD_MASK … #define XTE_FCC_OFFSET … #define XTE_FCC_RXFLO_MASK … #define XTE_FCC_TXFLO_MASK … #define XTE_EMCFG_OFFSET … #define XTE_EMCFG_LINKSPD_MASK … #define XTE_EMCFG_HOSTEN_MASK … #define XTE_EMCFG_LINKSPD_10 … #define XTE_EMCFG_LINKSPD_100 … #define XTE_EMCFG_LINKSPD_1000 … #define XTE_GMIC_OFFSET … #define XTE_MC_OFFSET … #define XTE_UAW0_OFFSET … #define XTE_UAW1_OFFSET … #define XTE_MAW0_OFFSET … #define XTE_MAW1_OFFSET … #define XTE_AFM_OFFSET … #define XTE_AFM_EPPRM_MASK … /* Interrupt Request status */ #define XTE_TIS_OFFSET … #define TIS_FRIS … #define TIS_MRIS … #define TIS_MWIS … #define TIS_ARIS … #define TIS_AWIS … #define TIS_CRIS … #define TIS_CWIS … #define XTE_TIE_OFFSET … /* MII Management Control register (MGTCR) */ #define XTE_MGTDR_OFFSET … #define XTE_MIIMAI_OFFSET … #define CNTLREG_WRITE_ENABLE_MASK … #define CNTLREG_EMAC1SEL_MASK … #define CNTLREG_ADDRESSCODE_MASK … /* CDMAC descriptor status bit definitions */ #define STS_CTRL_APP0_ERR … #define STS_CTRL_APP0_IRQONEND … /* undocumented */ #define STS_CTRL_APP0_STOPONEND … #define STS_CTRL_APP0_CMPLT … #define STS_CTRL_APP0_SOP … #define STS_CTRL_APP0_EOP … #define STS_CTRL_APP0_ENGBUSY … /* undocumented */ #define STS_CTRL_APP0_ENGRST … #define TX_CONTROL_CALC_CSUM_MASK … #define MULTICAST_CAM_TABLE_NUM … /* TEMAC Synthesis features */ #define TEMAC_FEATURE_RX_CSUM … #define TEMAC_FEATURE_TX_CSUM … /* TX/RX CURDESC_PTR points to first descriptor */ /* TX/RX TAILDESC_PTR points to last descriptor in linked list */ /** * struct cdmac_bd - LocalLink buffer descriptor format * * app0 bits: * 0 Error * 1 IrqOnEnd generate an interrupt at completion of DMA op * 2 reserved * 3 completed Current descriptor completed * 4 SOP TX - marks first desc/ RX marks first desct * 5 EOP TX marks last desc/RX marks last desc * 6 EngBusy DMA is processing * 7 reserved * 8:31 application specific */ struct cdmac_bd { … }; struct temac_local { … }; /* Wrappers for temac_ior()/temac_iow() function pointers above */ #define temac_ior(lp, o) … #define temac_iow(lp, o, v) … /* xilinx_temac.c */ int temac_indirect_busywait(struct temac_local *lp); u32 temac_indirect_in32(struct temac_local *lp, int reg); u32 temac_indirect_in32_locked(struct temac_local *lp, int reg); void temac_indirect_out32(struct temac_local *lp, int reg, u32 value); void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value); /* xilinx_temac_mdio.c */ int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev); void temac_mdio_teardown(struct temac_local *lp); #endif /* XILINX_LL_TEMAC_H */
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