/* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for Xilinx Axi Ethernet device driver. * * Copyright (c) 2009 Secret Lab Technologies, Ltd. * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. */ #ifndef XILINX_AXIENET_H #define XILINX_AXIENET_H #include <linux/netdevice.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/if_vlan.h> #include <linux/phylink.h> #include <linux/skbuff.h> /* Packet size info */ #define XAE_HDR_SIZE … #define XAE_TRL_SIZE … #define XAE_MTU … #define XAE_JUMBO_MTU … #define XAE_MAX_FRAME_SIZE … #define XAE_MAX_VLAN_FRAME_SIZE … #define XAE_MAX_JUMBO_FRAME_SIZE … /* Configuration options */ /* Accept all incoming packets. Default: disabled (cleared) */ #define XAE_OPTION_PROMISC … /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */ #define XAE_OPTION_JUMBO … /* VLAN Rx & Tx frame support. Default: disabled (cleared) */ #define XAE_OPTION_VLAN … /* Enable recognition of flow control frames on Rx. Default: enabled (set) */ #define XAE_OPTION_FLOW_CONTROL … /* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not * stripped. Default: disabled (set) */ #define XAE_OPTION_FCS_STRIP … /* Generate FCS field and add PAD automatically for outgoing frames. * Default: enabled (set) */ #define XAE_OPTION_FCS_INSERT … /* Enable Length/Type error checking for incoming frames. When this option is * set, the MAC will filter frames that have a mismatched type/length field * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these * types of frames are encountered. When this option is cleared, the MAC will * allow these types of frames to be received. Default: enabled (set) */ #define XAE_OPTION_LENTYPE_ERR … /* Enable the transmitter. Default: enabled (set) */ #define XAE_OPTION_TXEN … /* Enable the receiver. Default: enabled (set) */ #define XAE_OPTION_RXEN … /* Default options set when device is initialized or reset */ #define XAE_OPTION_DEFAULTS … /* Axi DMA Register definitions */ #define XAXIDMA_TX_CR_OFFSET … #define XAXIDMA_TX_SR_OFFSET … #define XAXIDMA_TX_CDESC_OFFSET … #define XAXIDMA_TX_TDESC_OFFSET … #define XAXIDMA_RX_CR_OFFSET … #define XAXIDMA_RX_SR_OFFSET … #define XAXIDMA_RX_CDESC_OFFSET … #define XAXIDMA_RX_TDESC_OFFSET … #define XAXIDMA_CR_RUNSTOP_MASK … #define XAXIDMA_CR_RESET_MASK … #define XAXIDMA_SR_HALT_MASK … #define XAXIDMA_BD_NDESC_OFFSET … #define XAXIDMA_BD_BUFA_OFFSET … #define XAXIDMA_BD_CTRL_LEN_OFFSET … #define XAXIDMA_BD_STS_OFFSET … #define XAXIDMA_BD_USR0_OFFSET … #define XAXIDMA_BD_USR1_OFFSET … #define XAXIDMA_BD_USR2_OFFSET … #define XAXIDMA_BD_USR3_OFFSET … #define XAXIDMA_BD_USR4_OFFSET … #define XAXIDMA_BD_ID_OFFSET … #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET … #define XAXIDMA_BD_HAS_DRE_OFFSET … #define XAXIDMA_BD_HAS_DRE_SHIFT … #define XAXIDMA_BD_HAS_DRE_MASK … #define XAXIDMA_BD_WORDLEN_MASK … #define XAXIDMA_BD_CTRL_LENGTH_MASK … #define XAXIDMA_BD_CTRL_TXSOF_MASK … #define XAXIDMA_BD_CTRL_TXEOF_MASK … #define XAXIDMA_BD_CTRL_ALL_MASK … #define XAXIDMA_DELAY_MASK … #define XAXIDMA_COALESCE_MASK … #define XAXIDMA_DELAY_SHIFT … #define XAXIDMA_COALESCE_SHIFT … #define XAXIDMA_IRQ_IOC_MASK … #define XAXIDMA_IRQ_DELAY_MASK … #define XAXIDMA_IRQ_ERROR_MASK … #define XAXIDMA_IRQ_ALL_MASK … /* Default TX/RX Threshold and delay timer values for SGDMA mode */ #define XAXIDMA_DFT_TX_THRESHOLD … #define XAXIDMA_DFT_TX_USEC … #define XAXIDMA_DFT_RX_THRESHOLD … #define XAXIDMA_DFT_RX_USEC … #define XAXIDMA_BD_CTRL_TXSOF_MASK … #define XAXIDMA_BD_CTRL_TXEOF_MASK … #define XAXIDMA_BD_CTRL_ALL_MASK … #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK … #define XAXIDMA_BD_STS_COMPLETE_MASK … #define XAXIDMA_BD_STS_DEC_ERR_MASK … #define XAXIDMA_BD_STS_SLV_ERR_MASK … #define XAXIDMA_BD_STS_INT_ERR_MASK … #define XAXIDMA_BD_STS_ALL_ERR_MASK … #define XAXIDMA_BD_STS_RXSOF_MASK … #define XAXIDMA_BD_STS_RXEOF_MASK … #define XAXIDMA_BD_STS_ALL_MASK … #define XAXIDMA_BD_MINIMUM_ALIGNMENT … /* Axi Ethernet registers definition */ #define XAE_RAF_OFFSET … #define XAE_TPF_OFFSET … #define XAE_IFGP_OFFSET … #define XAE_IS_OFFSET … #define XAE_IP_OFFSET … #define XAE_IE_OFFSET … #define XAE_TTAG_OFFSET … #define XAE_RTAG_OFFSET … #define XAE_UAWL_OFFSET … #define XAE_UAWU_OFFSET … #define XAE_TPID0_OFFSET … #define XAE_TPID1_OFFSET … #define XAE_PPST_OFFSET … #define XAE_RCW0_OFFSET … #define XAE_RCW1_OFFSET … #define XAE_TC_OFFSET … #define XAE_FCC_OFFSET … #define XAE_EMMC_OFFSET … #define XAE_PHYC_OFFSET … #define XAE_ID_OFFSET … #define XAE_MDIO_MC_OFFSET … #define XAE_MDIO_MCR_OFFSET … #define XAE_MDIO_MWD_OFFSET … #define XAE_MDIO_MRD_OFFSET … #define XAE_UAW0_OFFSET … #define XAE_UAW1_OFFSET … #define XAE_FMI_OFFSET … #define XAE_AF0_OFFSET … #define XAE_AF1_OFFSET … #define XAE_TX_VLAN_DATA_OFFSET … #define XAE_RX_VLAN_DATA_OFFSET … #define XAE_MCAST_TABLE_OFFSET … /* Bit Masks for Axi Ethernet RAF register */ /* Reject receive multicast destination address */ #define XAE_RAF_MCSTREJ_MASK … /* Reject receive broadcast destination address */ #define XAE_RAF_BCSTREJ_MASK … #define XAE_RAF_TXVTAGMODE_MASK … #define XAE_RAF_RXVTAGMODE_MASK … #define XAE_RAF_TXVSTRPMODE_MASK … #define XAE_RAF_RXVSTRPMODE_MASK … #define XAE_RAF_NEWFNCENBL_MASK … /* Extended Multicast Filtering mode */ #define XAE_RAF_EMULTIFLTRENBL_MASK … #define XAE_RAF_STATSRST_MASK … #define XAE_RAF_RXBADFRMEN_MASK … #define XAE_RAF_TXVTAGMODE_SHIFT … #define XAE_RAF_RXVTAGMODE_SHIFT … #define XAE_RAF_TXVSTRPMODE_SHIFT … #define XAE_RAF_RXVSTRPMODE_SHIFT … /* Bit Masks for Axi Ethernet TPF and IFGP registers */ #define XAE_TPF_TPFV_MASK … /* Transmit inter-frame gap adjustment value */ #define XAE_IFGP0_IFGP_MASK … /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply * for all 3 registers. */ /* Hard register access complete */ #define XAE_INT_HARDACSCMPLT_MASK … /* Auto negotiation complete */ #define XAE_INT_AUTONEG_MASK … #define XAE_INT_RXCMPIT_MASK … #define XAE_INT_RXRJECT_MASK … #define XAE_INT_RXFIFOOVR_MASK … #define XAE_INT_TXCMPIT_MASK … #define XAE_INT_RXDCMLOCK_MASK … #define XAE_INT_MGTRDY_MASK … #define XAE_INT_PHYRSTCMPLT_MASK … #define XAE_INT_ALL_MASK … /* INT bits that indicate receive errors */ #define XAE_INT_RECV_ERROR_MASK … /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */ #define XAE_TPID_0_MASK … #define XAE_TPID_1_MASK … /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */ #define XAE_TPID_2_MASK … #define XAE_TPID_3_MASK … /* Bit masks for Axi Ethernet RCW1 register */ #define XAE_RCW1_RST_MASK … #define XAE_RCW1_JUM_MASK … /* In-Band FCS enable (FCS not stripped) */ #define XAE_RCW1_FCS_MASK … #define XAE_RCW1_RX_MASK … #define XAE_RCW1_VLAN_MASK … /* Length/type field valid check disable */ #define XAE_RCW1_LT_DIS_MASK … /* Control frame Length check disable */ #define XAE_RCW1_CL_DIS_MASK … /* Pause frame source address bits [47:32]. Bits [31:0] are * stored in register RCW0 */ #define XAE_RCW1_PAUSEADDR_MASK … /* Bit masks for Axi Ethernet TC register */ #define XAE_TC_RST_MASK … #define XAE_TC_JUM_MASK … /* In-Band FCS enable (FCS not generated) */ #define XAE_TC_FCS_MASK … #define XAE_TC_TX_MASK … #define XAE_TC_VLAN_MASK … /* Inter-frame gap adjustment enable */ #define XAE_TC_IFG_MASK … /* Bit masks for Axi Ethernet FCC register */ #define XAE_FCC_FCRX_MASK … #define XAE_FCC_FCTX_MASK … /* Bit masks for Axi Ethernet EMMC register */ #define XAE_EMMC_LINKSPEED_MASK … #define XAE_EMMC_RGMII_MASK … #define XAE_EMMC_SGMII_MASK … #define XAE_EMMC_GPCS_MASK … #define XAE_EMMC_HOST_MASK … #define XAE_EMMC_TX16BIT … #define XAE_EMMC_RX16BIT … #define XAE_EMMC_LINKSPD_10 … #define XAE_EMMC_LINKSPD_100 … #define XAE_EMMC_LINKSPD_1000 … /* Bit masks for Axi Ethernet PHYC register */ #define XAE_PHYC_SGMIILINKSPEED_MASK … #define XAE_PHYC_RGMIILINKSPEED_MASK … #define XAE_PHYC_RGMIIHD_MASK … #define XAE_PHYC_RGMIILINK_MASK … #define XAE_PHYC_RGLINKSPD_10 … #define XAE_PHYC_RGLINKSPD_100 … #define XAE_PHYC_RGLINKSPD_1000 … #define XAE_PHYC_SGLINKSPD_10 … #define XAE_PHYC_SGLINKSPD_100 … #define XAE_PHYC_SGLINKSPD_1000 … /* Bit masks for Axi Ethernet MDIO interface MC register */ #define XAE_MDIO_MC_MDIOEN_MASK … #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX … /* Bit masks for Axi Ethernet MDIO interface MCR register */ #define XAE_MDIO_MCR_PHYAD_MASK … #define XAE_MDIO_MCR_PHYAD_SHIFT … #define XAE_MDIO_MCR_REGAD_MASK … #define XAE_MDIO_MCR_REGAD_SHIFT … #define XAE_MDIO_MCR_OP_MASK … #define XAE_MDIO_MCR_OP_SHIFT … #define XAE_MDIO_MCR_OP_READ_MASK … #define XAE_MDIO_MCR_OP_WRITE_MASK … #define XAE_MDIO_MCR_INITIATE_MASK … #define XAE_MDIO_MCR_READY_MASK … /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */ #define XAE_MDIO_INT_MIIM_RDY_MASK … /* Bit masks for Axi Ethernet UAW1 register */ /* Station address bits [47:32]; Station address * bits [31:0] are stored in register UAW0 */ #define XAE_UAW1_UNICASTADDR_MASK … /* Bit masks for Axi Ethernet FMI register */ #define XAE_FMI_PM_MASK … #define XAE_FMI_IND_MASK … #define XAE_MDIO_DIV_DFT … /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */ #define XAE_PHY_TYPE_MII … #define XAE_PHY_TYPE_GMII … #define XAE_PHY_TYPE_RGMII_1_3 … #define XAE_PHY_TYPE_RGMII_2_0 … #define XAE_PHY_TYPE_SGMII … #define XAE_PHY_TYPE_1000BASE_X … /* Total number of entries in the hardware multicast table. */ #define XAE_MULTICAST_CAM_TABLE_NUM … /* Axi Ethernet Synthesis features */ #define XAE_FEATURE_PARTIAL_RX_CSUM … #define XAE_FEATURE_PARTIAL_TX_CSUM … #define XAE_FEATURE_FULL_RX_CSUM … #define XAE_FEATURE_FULL_TX_CSUM … #define XAE_FEATURE_DMA_64BIT … #define XAE_NO_CSUM_OFFLOAD … #define XAE_FULL_CSUM_STATUS_MASK … #define XAE_IP_UDP_CSUM_VALIDATED … #define XAE_IP_TCP_CSUM_VALIDATED … #define DELAY_OF_ONE_MILLISEC … /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */ #define XLNX_MII_STD_SELECT_REG … #define XLNX_MII_STD_SELECT_SGMII … /** * struct axidma_bd - Axi Dma buffer descriptor layout * @next: MM2S/S2MM Next Descriptor Pointer * @next_msb: MM2S/S2MM Next Descriptor Pointer (high 32 bits) * @phys: MM2S/S2MM Buffer Address * @phys_msb: MM2S/S2MM Buffer Address (high 32 bits) * @reserved3: Reserved and not used * @reserved4: Reserved and not used * @cntrl: MM2S/S2MM Control value * @status: MM2S/S2MM Status value * @app0: MM2S/S2MM User Application Field 0. * @app1: MM2S/S2MM User Application Field 1. * @app2: MM2S/S2MM User Application Field 2. * @app3: MM2S/S2MM User Application Field 3. * @app4: MM2S/S2MM User Application Field 4. * @skb: Pointer to SKB transferred using DMA */ struct axidma_bd { … } __aligned(…); #define XAE_NUM_MISC_CLOCKS … /** * struct skbuf_dma_descriptor - skb for each dma descriptor * @sgl: Pointer for sglist. * @desc: Pointer to dma descriptor. * @dma_address: dma address of sglist. * @skb: Pointer to SKB transferred using DMA * @sg_len: number of entries in the sglist. */ struct skbuf_dma_descriptor { … }; /** * struct axienet_local - axienet private per device data * @ndev: Pointer for net_device to which it will be attached. * @dev: Pointer to device structure * @phylink: Pointer to phylink instance * @phylink_config: phylink configuration settings * @pcs_phy: Reference to PCS/PMA PHY if used * @pcs: phylink pcs structure for PCS PHY * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core * @axi_clk: AXI4-Lite bus clock * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks) * @mii_bus: Pointer to MII bus structure * @mii_clk_div: MII bus clock divider value * @regs_start: Resource start for axienet device addresses * @regs: Base address for the axienet_local device address space * @dma_regs: Base address for the axidma device address space * @napi_rx: NAPI RX control structure * @rx_dma_cr: Nominal content of RX DMA control register * @rx_bd_v: Virtual address of the RX buffer descriptor ring * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring * @rx_bd_num: Size of RX buffer descriptor ring * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being * accessed currently. * @rx_packets: RX packet count for statistics * @rx_bytes: RX byte count for statistics * @rx_stat_sync: Synchronization object for RX stats * @napi_tx: NAPI TX control structure * @tx_dma_cr: Nominal content of TX DMA control register * @tx_bd_v: Virtual address of the TX buffer descriptor ring * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring * @tx_bd_num: Size of TX buffer descriptor ring * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be * complete. Only updated at runtime by TX NAPI poll. * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring * to be populated. * @tx_packets: TX packet count for statistics * @tx_bytes: TX byte count for statistics * @tx_stat_sync: Synchronization object for TX stats * @dma_err_task: Work structure to process Axi DMA errors * @tx_irq: Axidma TX IRQ number * @rx_irq: Axidma RX IRQ number * @eth_irq: Ethernet core IRQ number * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X * @options: AxiEthernet option word * @features: Stores the extended features supported by the axienet hw * @max_frm_size: Stores the maximum size of the frame that can be that * Txed/Rxed in the existing hardware. If jumbo option is * supported, the maximum frame size would be 9k. Else it is * 1522 bytes (assuming support for basic VLAN) * @rxmem: Stores rx memory size for jumbo frame handling. * @csum_offload_on_tx_path: Stores the checksum selection on TX side. * @csum_offload_on_rx_path: Stores the checksum selection on RX side. * @coalesce_count_rx: Store the irq coalesce on RX side. * @coalesce_usec_rx: IRQ coalesce delay for RX * @coalesce_count_tx: Store the irq coalesce on TX side. * @coalesce_usec_tx: IRQ coalesce delay for TX * @use_dmaengine: flag to check dmaengine framework usage. * @tx_chan: TX DMA channel. * @rx_chan: RX DMA channel. * @tx_skb_ring: Pointer to TX skb ring buffer array. * @rx_skb_ring: Pointer to RX skb ring buffer array. * @tx_ring_head: TX skb ring buffer head index. * @tx_ring_tail: TX skb ring buffer tail index. * @rx_ring_head: RX skb ring buffer head index. * @rx_ring_tail: RX skb ring buffer tail index. */ struct axienet_local { … }; /** * struct axienet_option - Used to set axi ethernet hardware options * @opt: Option to be set. * @reg: Register offset to be written for setting the option * @m_or: Mask to be ORed for setting the option in the register */ struct axienet_option { … }; /** * axienet_ior - Memory mapped Axi Ethernet register read * @lp: Pointer to axienet local structure * @offset: Address offset from the base address of Axi Ethernet core * * Return: The contents of the Axi Ethernet register * * This function returns the contents of the corresponding register. */ static inline u32 axienet_ior(struct axienet_local *lp, off_t offset) { … } static inline u32 axinet_ior_read_mcr(struct axienet_local *lp) { … } static inline void axienet_lock_mii(struct axienet_local *lp) { … } static inline void axienet_unlock_mii(struct axienet_local *lp) { … } /** * axienet_iow - Memory mapped Axi Ethernet register write * @lp: Pointer to axienet local structure * @offset: Address offset from the base address of Axi Ethernet core * @value: Value to be written into the Axi Ethernet register * * This function writes the desired value into the corresponding Axi Ethernet * register. */ static inline void axienet_iow(struct axienet_local *lp, off_t offset, u32 value) { … } /** * axienet_dma_out32 - Memory mapped Axi DMA register write. * @lp: Pointer to axienet local structure * @reg: Address offset from the base address of the Axi DMA core * @value: Value to be written into the Axi DMA register * * This function writes the desired value into the corresponding Axi DMA * register. */ static inline void axienet_dma_out32(struct axienet_local *lp, off_t reg, u32 value) { … } #if defined(CONFIG_64BIT) && defined(iowrite64) /** * axienet_dma_out64 - Memory mapped Axi DMA register write. * @lp: Pointer to axienet local structure * @reg: Address offset from the base address of the Axi DMA core * @value: Value to be written into the Axi DMA register * * This function writes the desired value into the corresponding Axi DMA * register. */ static inline void axienet_dma_out64(struct axienet_local *lp, off_t reg, u64 value) { iowrite64(value, lp->dma_regs + reg); } static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, dma_addr_t addr) { if (lp->features & XAE_FEATURE_DMA_64BIT) axienet_dma_out64(lp, reg, addr); else axienet_dma_out32(lp, reg, lower_32_bits(addr)); } #else /* CONFIG_64BIT */ static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, dma_addr_t addr) { … } #endif /* CONFIG_64BIT */ /* Function prototypes visible in xilinx_axienet_mdio.c for other files */ int axienet_mdio_setup(struct axienet_local *lp); void axienet_mdio_teardown(struct axienet_local *lp); #endif /* XILINX_AXI_ENET_H */
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