linux/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MDIO bus driver for the Xilinx Axi Ethernet device
 *
 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
 * Copyright (c) 2010 - 2011 Michal Simek <[email protected]>
 * Copyright (c) 2010 - 2011 PetaLogix
 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/jiffies.h>
#include <linux/iopoll.h>

#include "xilinx_axienet.h"

#define DEFAULT_MDIO_FREQ …
#define DEFAULT_HOST_CLOCK …

/**
 * axienet_mdio_wait_until_ready - MDIO wait function
 * @lp:	Pointer to axienet local data structure.
 *
 * Return :	0 on success, Negative value on errors
 *
 * Wait till MDIO interface is ready to accept a new transaction.
 */
static int axienet_mdio_wait_until_ready(struct axienet_local *lp)
{ … }

/**
 * axienet_mdio_mdc_enable - MDIO MDC enable function
 * @lp:	Pointer to axienet local data structure.
 *
 * Enable the MDIO MDC. Called prior to a read/write operation
 */
static void axienet_mdio_mdc_enable(struct axienet_local *lp)
{ … }

/**
 * axienet_mdio_mdc_disable - MDIO MDC disable function
 * @lp:	Pointer to axienet local data structure.
 *
 * Disable the MDIO MDC. Called after a read/write operation
 */
static void axienet_mdio_mdc_disable(struct axienet_local *lp)
{ … }

/**
 * axienet_mdio_read - MDIO interface read function
 * @bus:	Pointer to mii bus structure
 * @phy_id:	Address of the PHY device
 * @reg:	PHY register to read
 *
 * Return:	The register contents on success, -ETIMEDOUT on a timeout
 *
 * Reads the contents of the requested register from the requested PHY
 * address by first writing the details into MCR register. After a while
 * the register MRD is read to obtain the PHY register content.
 */
static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
{ … }

/**
 * axienet_mdio_write - MDIO interface write function
 * @bus:	Pointer to mii bus structure
 * @phy_id:	Address of the PHY device
 * @reg:	PHY register to write to
 * @val:	Value to be written into the register
 *
 * Return:	0 on success, -ETIMEDOUT on a timeout
 *
 * Writes the value to the requested register by first writing the value
 * into MWD register. The MCR register is then appropriately setup
 * to finish the write operation.
 */
static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
			      u16 val)
{ … }

/**
 * axienet_mdio_enable - MDIO hardware setup function
 * @lp:		Pointer to axienet local data structure.
 * @np:		Pointer to mdio device tree node.
 *
 * Return:	0 on success, -ETIMEDOUT on a timeout, -EOVERFLOW on a clock
 *		divisor overflow.
 *
 * Sets up the MDIO interface by initializing the MDIO clock and enabling the
 * MDIO interface in hardware.
 **/
static int axienet_mdio_enable(struct axienet_local *lp, struct device_node *np)
{ … }

/**
 * axienet_mdio_setup - MDIO setup function
 * @lp:		Pointer to axienet local data structure.
 *
 * Return:	0 on success, -ETIMEDOUT on a timeout, -EOVERFLOW on a clock
 *		divisor overflow, -ENOMEM when mdiobus_alloc (to allocate
 *		memory for mii bus structure) fails.
 *
 * Sets up the MDIO interface by initializing the MDIO clock.
 * Register the MDIO interface.
 **/
int axienet_mdio_setup(struct axienet_local *lp)
{ … }

/**
 * axienet_mdio_teardown - MDIO remove function
 * @lp:		Pointer to axienet local data structure.
 *
 * Unregisters the MDIO and frees any associate memory for mii bus.
 */
void axienet_mdio_teardown(struct axienet_local *lp)
{ … }