/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ /* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */ #ifndef IONIC_REGS_H #define IONIC_REGS_H #include <linux/io.h> /** struct ionic_intr - interrupt control register set. * @coal_init: coalesce timer initial value. * @mask: interrupt mask value. * @credits: interrupt credit count and return. * @mask_assert: interrupt mask value on assert. * @coal: coalesce timer time remaining. */ struct ionic_intr { … }; #define IONIC_INTR_CTRL_REGS_MAX … #define IONIC_INTR_CTRL_COAL_MAX … /** enum ionic_intr_mask_vals - valid values for mask and mask_assert. * @IONIC_INTR_MASK_CLEAR: unmask interrupt. * @IONIC_INTR_MASK_SET: mask interrupt. */ enum ionic_intr_mask_vals { … }; /** enum ionic_intr_credits_bits - bitwise composition of credits values. * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed. * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit. * @IONIC_INTR_CRED_UNMASK: unmask the interrupt. * @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer. * @IONIC_INTR_CRED_REARM: unmask the and reset the timer. */ enum ionic_intr_credits_bits { … }; static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl, int intr_idx, u32 coal) { … } static inline void ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl, int intr_idx, u32 mask) { … } static inline void ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl, int intr_idx, u32 cred, u32 flags) { … } static inline void ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl, int intr_idx) { … } static inline void ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl, int intr_idx, u32 mask) { … } /** enum ionic_dbell_bits - bitwise composition of dbell values. * * @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits. * @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value. * @IONIC_DBELL_QID: macro to build QID component of dbell value. * * @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits. * @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value. * @IONIC_DBELL_RING: macro to build ring component of dbell value. * * @IONIC_DBELL_RING_0: ring zero dbell component value. * @IONIC_DBELL_RING_1: ring one dbell component value. * @IONIC_DBELL_RING_2: ring two dbell component value. * @IONIC_DBELL_RING_3: ring three dbell component value. * * @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed. */ enum ionic_dbell_bits { … }; static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val) { … } #endif /* IONIC_REGS_H */
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