/* SPDX-License-Identifier: GPL-2.0-or-later */ /****************************************************************************** * * (C)Copyright 1998,1999 SysKonnect, * a business unit of Schneider & Koch & Co. Datensysteme GmbH. * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ #ifndef _SKFBI_H_ #define _SKFBI_H_ /* * FDDI-Fx (x := {I(SA), P(CI)}) * address calculation & function defines */ /*--------------------------------------------------------------------------*/ #ifdef PCI /* * (DV) = only defined for Da Vinci * (ML) = only defined for Monalisa */ /* * I2C Address (PCI Config) * * Note: The temperature and voltage sensors are relocated on a different * I2C bus. */ #define I2C_ADDR_VPD … /* * Control Register File: * Bank 0 */ #define B0_RAP … /* 0x0001 - 0x0003: reserved */ #define B0_CTRL … #define B0_DAS … #define B0_LED … #define B0_TST_CTRL … #define B0_ISRC … #define B0_IMSK … /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ #define B0_CMDREG1 … #define B0_CMDREG2 … #define B0_ST1U … #define B0_ST1L … #define B0_ST2U … #define B0_ST2L … #define B0_MARR … #define B0_MARW … #define B0_MDRU … #define B0_MDRL … #define B0_MDREG3 … #define B0_ST3U … #define B0_ST3L … #define B0_IMSK3U … #define B0_IMSK3L … #define B0_IVR … #define B0_IMR … /* 0x4c Hidden */ #define B0_CNTRL_A … #define B0_CNTRL_B … #define B0_INTR_MASK … #define B0_XMIT_VECTOR … #define B0_STATUS_A … #define B0_STATUS_B … #define B0_CNTRL_C … #define B0_MDREG1 … #define B0_R1_CSR … #define B0_R2_CSR … #define B0_XA_CSR … #define B0_XS_CSR … /* * Bank 1 * - completely empty (this is the RAP Block window) * Note: if RAP = 1 this page is reserved */ /* * Bank 2 */ #define B2_MAC_0 … #define B2_MAC_1 … #define B2_MAC_2 … #define B2_MAC_3 … #define B2_MAC_4 … #define B2_MAC_5 … #define B2_MAC_6 … #define B2_MAC_7 … #define B2_CONN_TYP … #define B2_PMD_TYP … /* 0x010a - 0x010b: reserved */ /* Eprom registers are currently of no use */ #define B2_E_0 … #define B2_E_1 … #define B2_E_2 … #define B2_E_3 … #define B2_FAR … #define B2_FDP … /* 0x0115 - 0x0117: reserved */ #define B2_LD_CRTL … #define B2_LD_TEST … /* 0x011a - 0x011f: reserved */ #define B2_TI_INI … #define B2_TI_VAL … #define B2_TI_CRTL … #define B2_TI_TEST … /* 0x012a - 0x012f: reserved */ #define B2_WDOG_INI … #define B2_WDOG_VAL … #define B2_WDOG_CRTL … #define B2_WDOG_TEST … /* 0x013a - 0x013f: reserved */ #define B2_RTM_INI … #define B2_RTM_VAL … #define B2_RTM_CRTL … #define B2_RTM_TEST … #define B2_TOK_COUNT … #define B2_DESC_ADDR_H … #define B2_CTRL_2 … #define B2_IFACE_REG … /* 0x0156: reserved */ #define B2_TST_CTRL_2 … #define B2_I2C_CTRL … #define B2_I2C_DATA … #define B2_IRQ_MOD_INI … #define B2_IRQ_MOD_VAL … #define B2_IRQ_MOD_CTRL … #define B2_IRQ_MOD_TEST … /* 0x016a - 0x017f: reserved */ /* * Bank 3 */ /* * This is a copy of the Configuration register file (lower half) */ #define B3_CFG_SPC … /* * Bank 4 */ #define B4_R1_D … #define B4_R1_DA … #define B4_R1_AC … #define B4_R1_BC … #define B4_R1_CSR … #define B4_R1_F … #define B4_R1_T1 … #define B4_R1_T1_TR … #define B4_R1_T1_WR … #define B4_R1_T1_RD … #define B4_R1_T1_SV … #define B4_R1_T2 … #define B4_R1_T3 … #define B4_R1_DA_H … #define B4_R1_AC_H … /* 0x0238 - 0x023f: reserved */ /* Receive queue 2 is removed on Monalisa */ #define B4_R2_D … #define B4_R2_DA … #define B4_R2_AC … #define B4_R2_BC … #define B4_R2_CSR … #define B4_R2_F … #define B4_R2_T1 … #define B4_R2_T1_TR … #define B4_R2_T1_WR … #define B4_R2_T1_RD … #define B4_R2_T1_SV … #define B4_R2_T2 … #define B4_R2_T3 … /* 0x0270 - 0x027c: reserved */ /* * Bank 5 */ #define B5_XA_D … #define B5_XA_DA … #define B5_XA_AC … #define B5_XA_BC … #define B5_XA_CSR … #define B5_XA_F … #define B5_XA_T1 … #define B5_XA_T1_TR … #define B5_XA_T1_WR … #define B5_XA_T1_RD … #define B5_XA_T1_SV … #define B5_XA_T2 … #define B5_XA_T3 … #define B5_XA_DA_H … #define B5_XA_AC_H … /* 0x02b8 - 0x02bc: reserved */ #define B5_XS_D … #define B5_XS_DA … #define B5_XS_AC … #define B5_XS_BC … #define B5_XS_CSR … #define B5_XS_F … #define B5_XS_T1 … #define B5_XS_T1_TR … #define B5_XS_T1_WR … #define B5_XS_T1_RD … #define B5_XS_T1_SV … #define B5_XS_T2 … #define B5_XS_T3 … #define B5_XS_DA_H … #define B5_XS_AC_H … /* 0x02f8 - 0x02fc: reserved */ /* * Bank 6 */ /* External PLC-S registers (SN2 compatibility for DV) */ /* External registers (ML) */ #define B6_EXT_REG … /* * Bank 7 */ /* DAS PLC-S Registers */ /* * Bank 8 - 15 */ /* IFCP registers */ /*---------------------------------------------------------------------------*/ /* Definitions of the Bits in the registers */ /* B0_RAP 16 bit register address port */ #define RAP_RAP … /* B0_CTRL 8 bit control register */ #define CTRL_FDDI_CLR … #define CTRL_FDDI_SET … #define CTRL_HPI_CLR … #define CTRL_HPI_SET … #define CTRL_MRST_CLR … #define CTRL_MRST_SET … #define CTRL_RST_CLR … #define CTRL_RST_SET … /* B0_DAS 8 Bit control register (DAS) */ #define BUS_CLOCK … #define BUS_SLOT_SZ … /* Bit 5..4: reserved */ #define DAS_AVAIL … #define DAS_BYP_ST … #define DAS_BYP_INS … #define DAS_BYP_RMV … /* B0_LED 8 Bit LED register */ /* Bit 7..6: reserved */ #define LED_2_ON … #define LED_2_OFF … #define LED_1_ON … #define LED_1_OFF … #define LED_0_ON … #define LED_0_OFF … /* This hardware defines are very ugly therefore we define some others */ #define LED_GA_ON … #define LED_GA_OFF … #define LED_MY_ON … #define LED_MY_OFF … #define LED_GB_ON … #define LED_GB_OFF … /* B0_TST_CTRL 8 bit test control register */ #define TST_FRC_DPERR_MR … #define TST_FRC_DPERR_MW … #define TST_FRC_DPERR_TR … #define TST_FRC_DPERR_TW … #define TST_FRC_APERR_M … #define TST_FRC_APERR_T … #define TST_CFG_WRITE_ON … #define TST_CFG_WRITE_OFF … /* B0_ISRC 32 bit Interrupt source register */ /* Bit 31..28: reserved */ #define IS_I2C_READY … #define IS_IRQ_SW … #define IS_EXT_REG … #define IS_IRQ_STAT … /* PERR, RMABORT, RTABORT DATAPERR */ #define IS_IRQ_MST_ERR … /* RMABORT, RTABORT, DATAPERR */ #define IS_TIMINT … #define IS_TOKEN … /* * Note: The DAS is our First Port (!=PA) */ #define IS_PLINT1 … #define IS_PLINT2 … #define IS_MINTR3 … #define IS_MINTR2 … #define IS_MINTR1 … /* Receive Queue 1 */ #define IS_R1_P … #define IS_R1_B … #define IS_R1_F … #define IS_R1_C … /* Receive Queue 2 */ #define IS_R2_P … #define IS_R2_B … #define IS_R2_F … #define IS_R2_C … /* Asynchronous Transmit queue */ /* Bit 7: reserved */ #define IS_XA_B … #define IS_XA_F … #define IS_XA_C … /* Synchronous Transmit queue */ /* Bit 3: reserved */ #define IS_XS_B … #define IS_XS_F … #define IS_XS_C … /* * Define all valid interrupt source Bits from GET_ISR () */ #define ALL_IRSR … #define ALL_IRSR_ML … /* B0_IMSK 32 bit Interrupt mask register */ /* * The Bit definnition of this register are the same as of the interrupt * source register. These definition are directly derived from the Hardware * spec. */ /* Bit 31..28: reserved */ #define IRQ_I2C_READY … #define IRQ_SW … #define IRQ_EXT_REG … #define IRQ_STAT … /* PERR, RMABORT, RTABORT DATAPERR */ #define IRQ_MST_ERR … /* RMABORT, RTABORT, DATAPERR */ #define IRQ_TIMER … #define IRQ_RTM … #define IRQ_DAS … #define IRQ_IFCP_4 … #define IRQ_IFCP_3 … #define IRQ_IFCP_2 … #define IRQ_IFCP_1 … /* Receive Queue 1 */ #define IRQ_R1_P … #define IRQ_R1_B … #define IRQ_R1_F … #define IRQ_R1_C … /* Receive Queue 2 */ #define IRQ_R2_P … #define IRQ_R2_B … #define IRQ_R2_F … #define IRQ_R2_C … /* Asynchronous Transmit queue */ /* Bit 7: reserved */ #define IRQ_XA_B … #define IRQ_XA_F … #define IRQ_XA_C … /* Synchronous Transmit queue */ /* Bit 3: reserved */ #define IRQ_XS_B … #define IRQ_XS_F … #define IRQ_XS_C … /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ /* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */ /* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */ /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */ /* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */ /* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */ /* B2_MAC_0 8 bit MAC address Byte 0 */ /* B2_MAC_1 8 bit MAC address Byte 1 */ /* B2_MAC_2 8 bit MAC address Byte 2 */ /* B2_MAC_3 8 bit MAC address Byte 3 */ /* B2_MAC_4 8 bit MAC address Byte 4 */ /* B2_MAC_5 8 bit MAC address Byte 5 */ /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */ /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */ /* B2_CONN_TYP 8 bit Connector type */ /* B2_PMD_TYP 8 bit PMD type */ /* Values of connector and PMD type comply to SysKonnect internal std */ /* The EPROM register are currently of no use */ /* B2_E_0 8 bit EPROM Byte 0 */ /* B2_E_1 8 bit EPROM Byte 1 */ /* B2_E_2 8 bit EPROM Byte 2 */ /* B2_E_3 8 bit EPROM Byte 3 */ /* B2_FAR 32 bit Flash-Prom Address Register/Counter */ #define FAR_ADDR … /* B2_FDP 8 bit Flash-Prom Data Port */ /* B2_LD_CRTL 8 bit loader control */ /* Bits are currently reserved */ /* B2_LD_TEST 8 bit loader test */ #define LD_T_ON … #define LD_T_OFF … #define LD_T_STEP … #define LD_START … /* B2_TI_INI 32 bit Timer init value */ /* B2_TI_VAL 32 bit Timer value */ /* B2_TI_CRTL 8 bit Timer control */ /* B2_TI_TEST 8 Bit Timer Test */ /* B2_WDOG_INI 32 bit Watchdog init value */ /* B2_WDOG_VAL 32 bit Watchdog value */ /* B2_WDOG_CRTL 8 bit Watchdog control */ /* B2_WDOG_TEST 8 Bit Watchdog Test */ /* B2_RTM_INI 32 bit RTM init value */ /* B2_RTM_VAL 32 bit RTM value */ /* B2_RTM_CRTL 8 bit RTM control */ /* B2_RTM_TEST 8 Bit RTM Test */ /* B2_<TIM>_CRTL 8 bit <TIM> control */ /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */ /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */ /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */ /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */ #define GET_TOK_CT … #define TIM_RES_TOK … #define TIM_ALARM … #define TIM_START … #define TIM_STOP … #define TIM_CL_IRQ … /* B2_<TIM>_TEST 8 Bit <TIM> Test */ #define TIM_T_ON … #define TIM_T_OFF … #define TIM_T_STEP … /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */ /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */ /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */ /* Bit 7..5: reserved */ #define CTRL_CL_I2C_IRQ … #define CTRL_ST_SW_IRQ … #define CTRL_CL_SW_IRQ … #define CTRL_STOP_DONE … #define CTRL_STOP_MAST … /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */ /* Bit 7..3: reserved */ #define IF_I2C_DATA_DIR … #define IF_I2C_DATA … #define IF_I2C_CLK … /* 0x0156: reserved */ /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */ /* Bit 7..4: reserved */ /* force the following error on */ /* the next master read/write */ #define TST_FRC_DPERR_MR64 … #define TST_FRC_DPERR_MW64 … #define TST_FRC_APERR_1M64 … #define TST_FRC_APERR_2M64 … /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */ #define I2C_FLAG … #define I2C_ADDR … #define I2C_DEV_SEL … /* Bit 5.. 8: reserved */ #define I2C_BURST_LEN … #define I2C_DEV_SIZE … #define I2C_025K_DEV … #define I2C_05K_DEV … #define I2C_1K_DEV … #define I2C_2K_DEV … #define I2C_4K_DEV … #define I2C_8K_DEV … #define I2C_16K_DEV … #define I2C_32K_DEV … #define I2C_STOP_BIT … /* * I2C Addresses * * The temperature sensor and the voltage sensor are on the same I2C bus. * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1 * in PCI_OUR_REG 1. */ #define I2C_ADDR_TEMP … /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */ /* B4_R1_D 4*32 bit current receive Descriptor (q1) */ /* B4_R1_DA 32 bit current rec desc address (q1) */ /* B4_R1_AC 32 bit current receive Address Count (q1) */ /* B4_R1_BC 32 bit current receive Byte Counter (q1) */ /* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */ /* B4_R1_F 32 bit flag register (q1) */ /* B4_R1_T1 32 bit Test Register 1 (q1) */ /* B4_R1_T2 32 bit Test Register 2 (q1) */ /* B4_R1_T3 32 bit Test Register 3 (q1) */ /* B4_R2_D 4*32 bit current receive Descriptor (q2) */ /* B4_R2_DA 32 bit current rec desc address (q2) */ /* B4_R2_AC 32 bit current receive Address Count (q2) */ /* B4_R2_BC 32 bit current receive Byte Counter (q2) */ /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */ /* B4_R2_F 32 bit flag register (q2) */ /* B4_R2_T1 32 bit Test Register 1 (q2) */ /* B4_R2_T2 32 bit Test Register 2 (q2) */ /* B4_R2_T3 32 bit Test Register 3 (q2) */ /* B5_XA_D 4*32 bit current receive Descriptor (xa) */ /* B5_XA_DA 32 bit current rec desc address (xa) */ /* B5_XA_AC 32 bit current receive Address Count (xa) */ /* B5_XA_BC 32 bit current receive Byte Counter (xa) */ /* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */ /* B5_XA_F 32 bit flag register (xa) */ /* B5_XA_T1 32 bit Test Register 1 (xa) */ /* B5_XA_T2 32 bit Test Register 2 (xa) */ /* B5_XA_T3 32 bit Test Register 3 (xa) */ /* B5_XS_D 4*32 bit current receive Descriptor (xs) */ /* B5_XS_DA 32 bit current rec desc address (xs) */ /* B5_XS_AC 32 bit current receive Address Count (xs) */ /* B5_XS_BC 32 bit current receive Byte Counter (xs) */ /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */ /* B5_XS_F 32 bit flag register (xs) */ /* B5_XS_T1 32 bit Test Register 1 (xs) */ /* B5_XS_T2 32 bit Test Register 2 (xs) */ /* B5_XS_T3 32 bit Test Register 3 (xs) */ /* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */ #define CSR_DESC_CLEAR … #define CSR_DESC_SET … #define CSR_FIFO_CLEAR … #define CSR_FIFO_SET … #define CSR_HPI_RUN … #define CSR_HPI_RST … #define CSR_SV_RUN … #define CSR_SV_RST … #define CSR_DREAD_RUN … #define CSR_DREAD_RST … #define CSR_DWRITE_RUN … #define CSR_DWRITE_RST … #define CSR_TRANS_RUN … #define CSR_TRANS_RST … /* Bit 7..5: reserved */ #define CSR_START … #define CSR_IRQ_CL_P … #define CSR_IRQ_CL_B … #define CSR_IRQ_CL_F … #define CSR_IRQ_CL_C … #define CSR_SET_RESET … #define CSR_CLR_RESET … /* B5_<xx>_F 32 bit flag register (xx) */ /* Bit 28..31: reserved */ #define F_ALM_FULL … #define F_FIFO_EOF … #define F_WM_REACHED … #define F_UP_DW_USED … /* Bit 23: reserved */ #define F_FIFO_LEVEL … /* Bit 8..15: reserved */ #define F_ML_WATER_M … #define FLAG_WATER … /* B5_<xx>_T1 32 bit Test Register 1 (xx) */ /* Holds four State Machine control Bytes */ #define SM_CRTL_SV … #define SM_CRTL_RD … #define SM_CRTL_WR … #define SM_CRTL_TR … /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */ /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */ /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */ /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */ /* The control status byte of each machine looks like ... */ #define SM_STATE … #define SM_LOAD … #define SM_TEST_ON … #define SM_TEST_OFF … #define SM_STEP … /* The coding of the states */ #define SM_SV_IDLE … #define SM_SV_RES_START … #define SM_SV_GET_DESC … #define SM_SV_CHECK … #define SM_SV_MOV_DATA … #define SM_SV_PUT_DESC … #define SM_SV_SET_IRQ … #define SM_RD_IDLE … #define SM_RD_LOAD … #define SM_RD_WAIT_TC … #define SM_RD_RST_EOF … #define SM_RD_WDONE_R … #define SM_RD_WDONE_T … #define SM_TR_IDLE … #define SM_TR_LOAD … #define SM_TR_LOAD_R_ML … #define SM_TR_WAIT_TC … #define SM_TR_WDONE … #define SM_WR_IDLE … #define SM_WR_ABLEN … #define SM_WR_LD_A4 … #define SM_WR_RES_OWN … #define SM_WR_WAIT_EOF … #define SM_WR_LD_N2C_R … #define SM_WR_WAIT_TC_R … #define SM_WR_WAIT_TC4 … #define SM_WR_LD_A_T … #define SM_WR_LD_A_R … #define SM_WR_WAIT_TC_T … #define SM_WR_LD_N2C_T … #define SM_WR_WDONE_T … #define SM_WR_WDONE_R … #define SM_WR_LD_D_AD … #define SM_WR_WAIT_D_TC … /* B5_<xx>_T2 32 bit Test Register 2 (xx) */ /* Note: This register is only defined for the transmit queues */ /* Bit 31..8: reserved */ #define AC_TEST_ON … #define AC_TEST_OFF … #define BC_TEST_ON … #define BC_TEST_OFF … #define TEST_STEP04 … #define TEST_STEP03 … #define TEST_STEP02 … #define TEST_STEP01 … /* B5_<xx>_T3 32 bit Test Register 3 (xx) */ /* Note: This register is only defined for the transmit queues */ /* Bit 31..8: reserved */ #define T3_MUX_2 … #define T3_VRAM_2 … #define T3_LOOP … #define T3_UNLOOP … #define T3_MUX … #define T3_VRAM … /* * address transmission from logical to physical offset address on board */ #define FMA(a) … #define P1(a) … #define P2(a) … #define PRA(a) … /* * FlashProm specification */ #define MAX_PAGES … #define MAX_FADDR … /* * Receive / Transmit Buffer Control word */ #define BMU_OWN … #define BMU_STF … #define BMU_EOF … #define BMU_EN_IRQ_EOB … #define BMU_EN_IRQ_EOF … #define BMU_DEV_0 … #define BMU_SMT_TX … #define BMU_ST_BUF … #define BMU_UNUSED … #define BMU_SW … #define BMU_CHECK … #define BMU_BBC … /* * physical address offset + IO-Port base address */ #ifdef MEM_MAPPED_IO #define ADDR(a) … #define ADDRS(smc,a) … #else #define ADDR … #define ADDRS … #endif /* * Define a macro to access the configuration space */ #define PCI_C(a) … #define EXT_R(a) … /* * Define some values needed for the MAC address (PROM) */ #define SA_MAC … #define PRA_OFF … #define SKFDDI_PSZ … #define FM_A(a) … #define P1_A(a) … #define P2_A(a) … #define PR_A(a) … /* * Macro to read the PROM */ #define READ_PROM(a) … #define GET_PAGE(bank) … #define VPP_ON() … #define VPP_OFF() … /* * Note: Values of the Interrupt Source Register are defined above */ #define ISR_A … #define GET_ISR() … #define GET_ISR_SMP(iop) … #define CHECK_ISR() … #define CHECK_ISR_SMP(iop) … #define BUS_CHECK() … /* * CLI_FBI: Disable Board Interrupts * STI_FBI: Enable Board Interrupts */ #ifndef UNIX #define CLI_FBI() … #else #define CLI_FBI … #endif #ifndef UNIX #define STI_FBI() … #else #define STI_FBI … #endif #define CLI_FBI_SMP(iop) … #define STI_FBI_SMP(smc,iop) … #endif /* PCI */ /*--------------------------------------------------------------------------*/ /* * 12 bit transfer (dword) counter: * (ISA: 2*trc = number of byte) * (EISA: 4*trc = number of byte) * (MCA: 4*trc = number of byte) */ #define MAX_TRANS … /* * PC PIC */ #define MST_8259 … #define SLV_8259 … #define TPS … /* * error timer defs */ #define TN … #define SNPPND_TIME … #define MAC_AD … #define MODR1 … #define MODR2 … #define CMDR1 … #define CMDR2 … /* * function defines */ #define CLEAR(io,mask) … #define SET(io,mask) … #define GET(io,mask) … #define SETMASK(io,val,mask) … /* * PHY Port A (PA) = PLC 1 * With SuperNet 3 PHY-A and PHY S are identical. */ #define PLC(np,reg) … /* * set memory address register for write and read */ #define MARW(ma) … #define MARR(ma) … /* * read/write from/to memory data register */ /* write double word */ #define MDRW(dd) … #ifndef WINNT /* read double word */ #define MDRR() … /* read FORMAC+ 32-bit status register */ #define GET_ST1() … #define GET_ST2() … #ifdef SUPERNET_3 #define GET_ST3 … #endif #else /* read double word */ #define MDRR … /* read FORMAC+ 32-bit status register */ #define GET_ST1 … #define GET_ST2 … #ifdef SUPERNET_3 #define GET_ST3 … #endif #endif /* Special timer macro for 82c54 */ /* timer access over data bus bit 8..15 */ #define OUT_82c54_TIMER(port,val) … #define IN_82c54_TIMER(port) … #ifdef DEBUG #define DB_MAC … #define DB_PLC … #define DB_TIMER … #else /* no DEBUG */ #define DB_MAC(mac,st) … #define DB_PLC(p,iev) … #define DB_TIMER() … #endif /* no DEBUG */ #define INC_PTR(sp,cp,ep) … /* * timer defs */ #define COUNT(t) … #define RW_OP(o) … #define TMODE(m) … #endif
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