linux/drivers/net/fddi/skfp/h/supern_2.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/******************************************************************************
 *
 *	(C)Copyright 1998,1999 SysKonnect,
 *	a business unit of Schneider & Koch & Co. Datensysteme GmbH.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

/*
	defines for AMD Supernet II chip set
	the chips are referred to as
		FPLUS	Formac Plus
		PLC	Physical Layer

	added defines for AMD Supernet III chip set
	added comments on differences between Supernet II and Supernet III
	added defines for the Motorola ELM (MOT_ELM)
*/

#ifndef	_SUPERNET_
#define _SUPERNET_

/*
 * Define Supernet 3 when used
 */
#ifdef	PCI
#ifndef	SUPERNET_3
#define SUPERNET_3
#endif
#define TAG
#endif

#define MB
#define MW
#define MD

/*
 * FORMAC frame status (rx_msext)
 */
#define FS_EI
#define FS_AI
#define FS_CI

#define FS_MSVALID
#define FS_MSRABT
#define FS_SSRCRTG
#define FS_SEAC2
#define FS_SEAC1
#define FS_SEAC0
#define FS_SFRMERR
#define FS_SADRRG
#define FS_SFRMTY2
#define FS_SFRMTY1
#define FS_SFRMTY0
#define FS_ERFBB1
#define FS_ERFBB0

/*
 * status frame type
 */
#define FRM_SMT
#define FRM_LLCA
#define FRM_IMPA	
#define FRM_MAC
#define FRM_LLCS
#define FRM_IMPS

/*
 * bits in rx_descr.i	(receive frame status word)
 */
#define RX_MSVALID
#define RX_MSRABT
#define RX_FS_E
#define RX_FS_A
#define RX_FS_C
#define RX_FS_CRC
#define RX_FS_ADDRESS
#define RX_FS_MAC
#define RX_FS_SMT
#define RX_FS_IMPL
#define RX_FS_LLC

/*
 * receive frame descriptor
 */
rx_descr ;

/* defines for Receive Frame Descriptor access */
#define RD_S_ERFBB
#define RD_S_RES2
#define RD_S_SFRMTY
#define RD_S_SADRRG
#define RD_S_SFRMERR
#define RD_S_SEAC
#define RD_S_SEAC0
#define RD_S_SEAC1
#define RD_S_SEAC2
#define RD_S_SSRCRTG
#define RD_S_RES1
#define RD_S_MSRABT
#define RD_S_MSVALID

#define RD_STATUS
#define RD_LENGTH

/* defines for Receive Frames Status Word values */
/*RD_S_SFRMTY*/
#define RD_FRM_SMT
#define RD_FRM_LLCA
#define RD_FRM_IMPA
#define RD_FRM_MAC
#define RD_FRM_LLCS
#define RD_FRM_IMPS

#define TX_DESCRIPTOR
#define TX_OFFSET_3

#define TXP1

/*
 * transmit frame descriptor
 */
tx_descr ;

/* defines for Transmit Descriptor access */
#define TD_C_MORE
#define TD_C_DESCR
#define TD_C_TXFBB
#define TD_C_XDONE
#define TD_C_NFCS
#define TD_C_XMTABT

#define TD_C_LNCNU	
#define TD_C_LNCNL
#define TD_C_LNCN
 
/*
 * transmit pointer
 */
tx_pointer ;

/* defines for Nontag Mode Pointer access */
#define TD_P_CNTRL
#define TD_P_RPXU
#define TD_P_RPXL
#define TD_P_RPX


#define TX_PATTERN
#define TX_POINTER_END
#define TX_INT_PATTERN

struct tx_queue {} ;

/*
	defines for FORMAC Plus (Am79C830)
*/

/*
 *  FORMAC+ read/write (r/w) registers
 */
#define FM_CMDREG1
#define FM_CMDREG2
#define FM_ST1U
#define FM_ST1L
#define FM_ST2U
#define FM_ST2L
#define FM_IMSK1U
#define FM_IMSK1L
#define FM_IMSK2U
#define FM_IMSK2L
#define FM_SAID
#define FM_LAIM
#define FM_LAIC
#define FM_LAIL
#define FM_SAGP
#define FM_LAGM
#define FM_LAGC
#define FM_LAGL
#define FM_MDREG1
#define FM_STMCHN
#define FM_MIR1
#define FM_MIR0
#define FM_TMAX
#define FM_TVX
#define FM_TRT
#define FM_THT
#define FM_TNEG
#define FM_TMRS
			/* F E D C  B A 9 8  7 6 5 4  3 2 1 0
			   x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
#define FM_TREQ0
#define FM_TREQ1
#define FM_PRI0
#define FM_PRI1
#define FM_PRI2
#define FM_TSYNC
#define FM_MDREG2
#define FM_FRMTHR
#define FM_EACB
#define FM_EARV
/* Supernet 3 */
#define FM_EARV1

#define FM_EAS
#define FM_EAA0
#define FM_EAA1
#define FM_EAA2
#define FM_SACL
#define FM_SABC
#define FM_WPXSF
#define FM_RPXSF
#define FM_RPR
#define FM_WPR
#define FM_SWPR
/* Supernet 3 */ 
#define FM_RPR1   
#define FM_WPR1 
#define FM_SWPR1

#define FM_WPXS
#define FM_WPXA0
#define FM_WPXA1
#define FM_WPXA2
#define FM_SWPXS
#define FM_SWPXA0
#define FM_SWPXA1
#define FM_SWPXA2
#define FM_RPXS
#define FM_RPXA0
#define FM_RPXA1
#define FM_RPXA2
#define FM_MARR
#define FM_MARW
#define FM_MDRU
#define FM_MDRL

/* following instructions relate to MAC counters and timer */
#define FM_TMSYNC
#define FM_FCNTR
#define FM_LCNTR
#define FM_ECNTR

/* Supernet 3:	extensions to old register block */
#define FM_FSCNTR
#define FM_FRSELREG

/* Supernet 3:	extensions for 2. receive queue etc. */
#define FM_MDREG3
#define FM_ST3U
#define FM_ST3L
#define FM_IMSK3U
#define FM_IMSK3L
#define FM_IVR
#define FM_IMR
/* 0x67	Hidden */
#define FM_RPR2
#define FM_WPR2
#define FM_SWPR2
#define FM_EARV2
#define FM_UNLCKDLY
					/* Bit 15-8: RECV2 unlock threshold */
					/* Bit  7-0: RECV1 unlock threshold */
/* 0x6f-0x73	Hidden */
#define FM_LTDPA1
/* 0x80-0x9a	PLCS registers of built-in PLCS  (Supernet 3 only) */

/* Supernet 3: Adderss Filter Registers */
#define FM_AFCMD
#define FM_AFSTAT
#define FM_AFBIST
#define FM_AFCOMP2
#define FM_AFCOMP1
#define FM_AFCOMP0
#define FM_AFMASK2
#define FM_AFMASK1
#define FM_AFMASK0
#define FM_AFPERS

/* Supernet 3: Orion (PDX?) Registers */
#define FM_ORBIST
#define FM_ORSTAT


/*
 * Mode Register 1 (MDREG1)
 */
#define FM_RES0
					/* SN3: other definition */
#define FM_XMTINH_HOLD
					/* SN3: other definition */
#define FM_HOFLXI
#define FM_FULL_HALF
#define FM_LOCKTX
#define FM_EXGPA0
#define FM_EXGPA1
#define FM_DISCRY
					/* SN3: reserved */
#define FM_SELRA

#define FM_ADDET
#define FM_MDAMA
#define FM_MDASAMA
#define FM_MRNNSAFNMA
#define FM_MRNNSAF
#define FM_MDISRCV
#define FM_MRES0
#define FM_MLIMPROM
#define FM_MPROMISCOUS

#define FM_SELSA

#define FM_MMODE
#define FM_MINIT
#define FM_MMEMACT
#define FM_MONLINESP
#define FM_MONLINE
#define FM_MILOOP
#define FM_MRES1
#define FM_MRES2
#define FM_MELOOP

#define FM_SNGLFRM
					/* SN3: reserved */

#define MDR1INIT

/*
 * Mode Register 2 (MDREG2)
 */
#define FM_AFULL
#define FM_RCVERR
#define FM_SYMCTL
					/* SN3: reserved */
#define FM_SYNPRQ
#define FM_ENNPRQ
#define FM_ENHSRQ
#define FM_RXFBB01
#define FM_LSB
#define FM_PARITY
#define FM_CHKPAR
#define FM_STRPFCS
#define FM_BMMODE
					/* SN3: 1 = tag, 0 = modified tag */

/*
 * Status Register 1, Upper 16 Bits (ST1U)
 */
#define FM_STEFRMS
#define FM_STEFRMA0
#define FM_STEFRMA1
#define FM_STEFRMA2
					/* SN3: reserved */
#define FM_STECFRMS
					/* SN3: reserved */
#define FM_STECFRMA0
					/* SN3: reserved */
#define FM_STECFRMA1
					/* SN3: STECMDA1 */
#define FM_STECMDA1
#define FM_STECFRMA2
					/* SN3: reserved */
#define FM_STEXDONS
#define FM_STBFLA
#define FM_STBFLS
#define FM_STXABRS
#define FM_STXABRA0
#define FM_STXABRA1
#define FM_STXABRA2
					/* SN3: reserved */
#define FM_SXMTABT

/*
 * Status Register 1, Lower 16 Bits (ST1L)
 */
#define FM_SQLCKS
#define FM_SQLCKA0
#define FM_SQLCKA1
#define FM_SQLCKA2
					/* SN3: reserved */
#define FM_STXINFLS
					/* SN3: reserved */
#define FM_STXINFLA0
					/* SN3: reserved */
#define FM_STXINFLA1
					/* SN3: reserved */
#define FM_STXINFLA2
					/* SN3: reserved */
#define FM_SPCEPDS
#define FM_SPCEPDA0
#define FM_SPCEPDA1
#define FM_SPCEPDA2
					/* SN3: reserved */
#define FM_STBURS
#define FM_STBURA0
#define FM_STBURA1
#define FM_STBURA2
					/* SN3: reserved */

/*
 * Status Register 2, Upper 16 Bits (ST2U)
 */
#define FM_SOTRBEC
#define FM_SMYBEC
#define FM_SBEC
#define FM_SLOCLM
#define FM_SHICLM
#define FM_SMYCLM
#define FM_SCLM
#define FM_SERRSF
#define FM_SNFSLD
#define FM_SRFRCTOV
					/* SN3: reserved */
#define FM_SRCVFRM
					/* SN3: reserved */
#define FM_SRCVOVR
#define FM_SRBFL
#define FM_SRABT
#define FM_SRBMT
#define FM_SRCOMP

/*
 * Status Register 2, Lower 16 Bits (ST2L)
 * Attention: SN3 docu shows these bits the other way around
 */
#define FM_SRES0
#define FM_SESTRIPTK
#define FM_STRTEXR
#define FM_SDUPCLM
#define FM_SSIFG
#define FM_SFRMCTR
#define FM_SERRCTR
#define FM_SLSTCTR
#define FM_SPHINV
#define FM_SADET
#define FM_SMISFRM
#define FM_STRTEXP
#define FM_STVXEXP
#define FM_STKISS
#define FM_STKERR
#define FM_SMULTDA
#define FM_SRNGOP

/*
 * Supernet 3:
 * Status Register 3, Upper 16 Bits (ST3U)
 */
#define FM_SRQUNLCK1
#define FM_SRQUNLCK2
#define FM_SRPERRQ1
#define FM_SRPERRQ2
					/* Bit 4-10: reserved */
#define FM_SRCVOVR2
#define FM_SRBFL2
#define FM_SRABT2
#define FM_SRBMT2
#define FM_SRCOMP2

/*
 * Supernet 3:
 * Status Register 3, Lower 16 Bits (ST3L)
 */
#define FM_AF_BIST_DONE
#define FM_PLC_BIST_DONE
#define FM_PDX_BIST_DONE
					/* Bit  3: reserved */
#define FM_SICAMDAMAT
#define FM_SICAMDAXACT
#define FM_SICAMSAMAT
#define FM_SICAMSAXACT

/*
 * MAC State-Machine Register FM_STMCHN
 */
#define FM_MDRTAG
#define FM_SNPPND
#define FM_TXSTAT
#define FM_RCSTAT
#define FM_TM01
#define FM_SIM
#define FM_REV

/*
 * Supernet 3
 * Mode Register 3
 */
#define FM_MENRS
#define FM_MENXS
#define FM_MENXCT
#define FM_MENAFULL
#define FM_MEIND
#define FM_MENQCTRL
#define FM_MENRQAUNLCK
#define FM_MENDAS
#define FM_MENPLCCST
#define FM_MENSGLINT
#define FM_MENDRCV
#define FM_MENFCLOC
#define FM_MENTRCMD
#define FM_MENTDLPBK

/*
 * Supernet 3
 * Frame Selection Register
 */
#define FM_RECV1
#define FM_RCV1_ALL
#define FM_RCV1_LLC
#define FM_RCV1_SMT
#define FM_RCV1_NSMT
#define FM_RCV1_IMP
#define FM_RCV1_MAC
#define FM_RCV1_SLLC
#define FM_RCV1_ALLC
#define FM_RCV1_VOID
#define FM_RCV1_ALSMT
#define FM_RECV2
#define FM_RCV2_ALL
#define FM_RCV2_LLC
#define FM_RCV2_SMT
#define FM_RCV2_NSMT
#define FM_RCV2_IMP
#define FM_RCV2_MAC
#define FM_RCV2_SLLC
#define FM_RCV2_ALLC
#define FM_RCV2_VOID
#define FM_RCV2_ALSMT
#define FM_ENXMTADSWAP
#define FM_ENRCVADSWAP

/*
 * Supernet 3:
 * Address Filter Command Register (AFCMD)
 */
#define FM_INST
#define FM_IINV_CAM
#define FM_IWRITE_CAM
#define FM_IREAD_CAM
#define FM_IRUN_BIST
#define FM_IFIND
#define FM_IINV
#define FM_ISKIP
#define FM_ICL_SKIP

/*
 * Supernet 3:
 * Address Filter Status Register (AFSTAT)
 */
					/* Bit  0-4: reserved */
#define FM_REV_NO
#define FM_BIST_DONE
#define FM_EMPTY
#define FM_ERROR
#define FM_MULT
#define FM_EXACT
#define FM_FOUND
#define FM_FULL
#define FM_DONE

/*
 * Supernet 3:
 * BIST Signature Register (AFBIST)
 */
#define AF_BIST_SIGNAT

/*
 * Supernet 3:
 * Personality Register (AFPERS)
 */
#define FM_VALID
#define FM_DA
#define FM_DAX
#define FM_SA
#define FM_SAX
#define FM_SKIP

/*
 * instruction set for command register 1 (NPADDR6-0 = 0x00)
 */
#define FM_IRESET
#define FM_IRMEMWI
#define FM_IRMEMWO
#define FM_IIL
#define FM_ICL
#define FM_IBL
#define FM_ILTVX
#define FM_INRTM
#define FM_IENTM
#define FM_IERTM
#define FM_IRTM
#define FM_ISURT
#define FM_ISRT
#define FM_ISIM
#define FM_IESIM
#define FM_ICLLS
#define FM_ICLLA0
#define FM_ICLLA1
#define FM_ICLLA2
					/* SN3: reserved */
#define FM_ICLLR
#define FM_ICLLR2
#define FM_ITRXBUS
#define FM_IDRXBUS
#define FM_ICLLAL

/*
 * instruction set for command register 2 (NPADDR6-0 = 0x01)
 */
#define FM_ITRS
					/* SN3: reserved */
#define FM_ITRA0
					/* SN3: reserved */
#define FM_ITRA1
					/* SN3: reserved */
#define FM_ITRA2
					/* SN3: reserved */
#define FM_IACTR
#define FM_IRSTQ
#define FM_ISTTB
#define FM_IERSF
					/* SN3: reserved */
#define FM_ITR


/*
 *	defines for PLC (Am79C864)
 */

/*
 *  PLC read/write (r/w) registers
 */
#define PL_CNTRL_A
#define PL_CNTRL_B
#define PL_INTR_MASK
#define PL_XMIT_VECTOR
#define PL_VECTOR_LEN
#define PL_LE_THRESHOLD
#define PL_C_MIN
#define PL_TL_MIN
#define PL_TB_MIN
#define PL_T_OUT
#define PL_CNTRL_C
#define PL_LC_LENGTH
#define PL_T_SCRUB
#define PL_NS_MAX
#define PL_TPC_LOAD_V
#define PL_TNE_LOAD_V
#define PL_STATUS_A
#define PL_STATUS_B
#define PL_TPC
#define PL_TNE
#define PL_CLK_DIV
#define PL_BIST_SIGNAT
#define PL_RCV_VECTOR
#define PL_INTR_EVENT
#define PL_VIOL_SYM_CTR
#define PL_MIN_IDLE_CTR
#define PL_LINK_ERR_CTR
#ifdef	MOT_ELM
#define PL_T_FOT_ASS
#define PL_T_FOT_DEASS
#endif	/* MOT_ELM */

#ifdef	MOT_ELM
/*
 * Special Quad-Elm Registers.
 * A Quad-ELM consists of for ELMs and these additional registers.
 */
#define QELM_XBAR_W
#define QELM_XBAR_X
#define QELM_XBAR_Y
#define QELM_XBAR_Z
#define QELM_XBAR_P
#define QELM_XBAR_S
#define QELM_XBAR_R
#define QELM_WR_XBAR
#define QELM_CTR_W
#define QELM_CTR_X
#define QELM_CTR_Y
#define QELM_CTR_Z
#define QELM_INT_MASK
#define QELM_INT_DATA
#define QELM_ELMB
#define QELM_ELM_SIZE
#endif	/* MOT_ELM */
/*
 * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
 * It is used for timer configuration, specification of PCM MAINT state option,
 * counter interrupt frequency, PLC data path config. and Built In Self Test.
 */
#define PL_RUN_BIST
#define PL_RF_DISABLE
#define PL_SC_REM_LOOP
#define PL_SC_BYPASS
#define PL_LM_LOC_LOOP
#define PL_EB_LOC_LOOP
#define PL_FOT_OFF
#define PL_LOOPBACK
#define PL_MINI_CTR_INT
#define PL_VSYM_CTR_INT
#define PL_ENA_PAR_CHK
#define PL_REQ_SCRUB
#define PL_TPC_16BIT
#define PL_TNE_16BIT
#define PL_NOISE_TIMER

/*
 * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
 * It contains signals and requeste to direct the process of PCM and it is also
 * used to control the Line State Match interrupt.
 */
#define PL_PCM_CNTRL
#define PL_PCM_NAF
#define PL_PCM_START
#define PL_PCM_TRACE
#define PL_PCM_STOP

#define PL_MAINT
#define PL_LONG
#define PL_PC_JOIN

#define PL_PC_LOOP
#define PL_NOLCT
#define PL_TPDR
#define PL_TIDLE
#define PL_RLBP

#define PL_CLASS_S

#define PL_MAINT_LS
#define PL_M_QUI0
#define PL_M_IDLE
#define PL_M_HALT
#define PL_M_MASTR
#define PL_M_QUI1
#define PL_M_QUI2
#define PL_M_TPDR
#define PL_M_QUI3

#define PL_MATCH_LS
#define PL_I_ANY
#define PL_I_IDLE
#define PL_I_HALT
#define PL_I_MASTR
#define PL_I_QUIET

#define PL_CONFIG_CNTRL

/*
 * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
 * It contains the scrambling control registers (PLC-S only)
 */
#define PL_C_CIPHER_ENABLE
#define PL_C_CIPHER_LPBCK
#define PL_C_SDOFF_ENABLE
#define PL_C_SDON_ENABLE
#ifdef	MOT_ELM
#define PL_C_FOTOFF_CTRL
#define PL_C_FOTOFF_TIM
#define PL_C_FOTOFF_INA
#define PL_C_FOTOFF_ACT
#define PL_C_FOTOFF_SRCE
#define PL_C_RXDATA_EN
#define PL_C_SDNRZEN
#else	/* nMOT_ELM */
#define PL_C_FOTOFF_CTRL
#define PL_C_FOTOFF_0
#define PL_C_FOTOFF_30
#define PL_C_FOTOFF_50
#define PL_C_FOTOFF_NEVER
#define PL_C_SDON_TIMER
#define PL_C_SDON_084
#define PL_C_SDON_132
#define PL_C_SDON_252
#define PL_C_SDON_512
#define PL_C_SOFF_TIMER
#define PL_C_SOFF_076
#define PL_C_SOFF_132
#define PL_C_SOFF_252
#define PL_C_SOFF_512
#define PL_C_TSEL
#endif	/* nMOT_ELM */

/*
 * PLC status register A (PL_STATUS_A: log. addr. 0x10)
 * It is used to report status information to the Node Processor about the 
 * Line State Machine (LSM).
 */
#ifdef	MOT_ELM
#define PLC_INT_MASK
#define PLC_INT_C
#define PLC_INT_CAMEL
#define PLC_INT_QE
#define PLC_REV_MASK
#define PLC_REVISION_B
#define PLC_REVISION_QA
#else	/* nMOT_ELM */
#define PLC_REV_MASK
#define PLC_REVISION_A
#define PLC_REVISION_S
#define PLC_REV_SN3
#endif	/* nMOT_ELM */
#define PL_SYM_PR_CTR
#define PL_UNKN_LINE_ST
#define PL_LSM_STATE

#define PL_LINE_ST
#define PL_L_NLS
#define PL_L_ALS
#define PL_L_UND
#define PL_L_ILS4
#define PL_L_QLS
#define PL_L_MLS
#define PL_L_HLS
#define PL_L_ILS16

#define PL_PREV_LINE_ST
#define PL_P_QLS
#define PL_P_MLS
#define PL_P_HLS
#define PL_P_ILS16

#define PL_SIGNAL_DET


/*
 * PLC status register B (PL_STATUS_B: log. addr. 0x11)
 * It contains signals and status from the repeat filter and PCM state machine.
 */
#define PL_BREAK_REASON
#define PL_B_NOT
#define PL_B_PCS
#define PL_B_TPC
#define PL_B_TNE
#define PL_B_QLS
#define PL_B_ILS
#define PL_B_HLS

#define PL_TCF
#define PL_RCF
#define PL_LSF
#define PL_PCM_SIGNAL

#define PL_PCM_STATE
#define PL_PC0
#define PL_PC1
#define PL_PC2
#define PL_PC3
#define PL_PC4
#define PL_PC5
#define PL_PC6
#define PL_PC7
#define PL_PC8
#define PL_PC9

#define PL_PCI_SCRUB

#define PL_PCI_STATE
#define PL_CI_REMV
#define PL_CI_ISCR
#define PL_CI_RSCR
#define PL_CI_INS

#define PL_RF_STATE
#define PL_RF_REPT
#define PL_RF_IDLE
#define PL_RF_HALT1
#define PL_RF_HALT2


/*
 * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17)
 * It is read only and is clearde whenever it is read!
 * It is used by the PLC to report events to the node processor.
 */
#define PL_PARITY_ERR
#define PL_LS_MATCH
#define PL_PCM_CODE
#define PL_TRACE_PROP
#define PL_SELF_TEST
#define PL_PCM_BREAK
#define PL_PCM_ENABLED
#define PL_TPC_EXPIRED
#define PL_TNE_EXPIRED
#define PL_EBUF_ERR
#define PL_PHYINV
#define PL_VSYM_CTR
#define PL_MINI_CTR
#define PL_LE_CTR
#define PL_LSDO
#define PL_NP_ERR

/*
 * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is
 * equal PL_INTR_EVENT register.
 * For each set bit, the setting of corresponding bit generate an int to NP. 
 */

#ifdef	MOT_ELM
/*
 * Quad ELM Crosbar Control register values (QELM_XBAR_?)
 */
#define QELM_XOUT_IDLE
#define QELM_XOUT_P
#define QELM_XOUT_S
#define QELM_XOUT_R
#define QELM_XOUT_W
#define QELM_XOUT_X
#define QELM_XOUT_Y
#define QELM_XOUT_Z

/*
 * Quad ELM Interrupt data and event registers.
 */
#define QELM_NP_ERR
#define QELM_COUNT_Z
#define QELM_COUNT_Y
#define QELM_COUNT_X
#define QELM_COUNT_W
#define QELM_ELM_Z
#define QELM_ELM_Y
#define QELM_ELM_X
#define QELM_ELM_W
#endif	/* MOT_ELM */
/*
 * PLC Timing Parameters
 */
#define TP_C_MIN
#define TP_TL_MIN
#define TP_TB_MIN
#define TP_T_OUT
#define TP_LC_LENGTH
#define TP_LC_LONGLN
#define TP_T_SCRUB
#define TP_NS_MAX

/*
 * BIST values
 */
#define PLC_BIST
#define PLCS_BIST
#define PLC_ELM_B_BIST
#define PLC_ELM_D_BIST
#define PLC_CAM_A_BIST
#define PLC_CAM_B_BIST
#define PLC_IFD_A_BIST
#define PLC_IFD_B_BIST
#define PLC_QELM_A_BIST

/*
	FDDI board recources
 */

/*
 * request register array (log. addr: RQA_A + a<<1 {a=0..7}) write only.
 * It specifies to FORMAC+ the type of buffer memory access the host requires.
 */
#define RQ_NOT
#define RQ_RES
#define RQ_SFW
#define RQ_RRQ
#define RQ_WSQ
#define RQ_WA0
#define RQ_WA1
#define RQ_WA2

#define SZ_LONG

/*
 * FDDI defaults
 * NOTE : In the ANSI docs, times are specified in units of "symbol time".
 * 	  AMD chips use BCLK as unit. 1 BCKL == 2 symbols
 */
#define COMPLREF
#define MSTOBCLK(x)
#define MSTOTVX(x)

#endif	/* _SUPERNET_ */