/* * File Name: * defxx.h * * Copyright Information: * Copyright Digital Equipment Corporation 1996. * * This software may be used and distributed according to the terms of * the GNU General Public License, incorporated herein by reference. * * Abstract: * Contains all definitions specified by port specification and required * by the defxx.c driver. * * The original author: * LVS Lawrence V. Stefani <[email protected]> * * Maintainers: * macro Maciej W. Rozycki <[email protected]> * * Modification History: * Date Name Description * 16-Aug-96 LVS Created. * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O * macros to DEFXX.C. * 12-Sep-96 LVS Removed packet request header pointers. * 04 Aug 2003 macro Converted to the DMA API. * 23 Oct 2006 macro Big-endian host support. * 14 Dec 2006 macro TURBOchannel support. * 10 Mar 2021 macro Dynamic MMIO vs port I/O. */ #ifndef _DEFXX_H_ #define _DEFXX_H_ /* Define basic types for unsigned chars, shorts, longs */ PI_UINT8; PI_UINT16; PI_UINT32; /* Define general structures */ PI_CNTR; PI_LAN_ADDR; PI_STATION_ID; /* Define general constants */ #define PI_ALIGN_K_DESC_BLK … #define PI_ALIGN_K_CONS_BLK … #define PI_ALIGN_K_CMD_REQ_BUFF … #define PI_ALIGN_K_CMD_RSP_BUFF … #define PI_ALIGN_K_UNSOL_BUFF … #define PI_ALIGN_K_XMT_DATA_BUFF … #define PI_ALIGN_K_RCV_DATA_BUFF … /* Define PHY index values */ #define PI_PHY_K_S … #define PI_PHY_K_A … #define PI_PHY_K_B … #define PI_PHY_K_MAX … /* Define FMC descriptor fields */ #define PI_FMC_DESCR_V_SOP … #define PI_FMC_DESCR_V_EOP … #define PI_FMC_DESCR_V_FSC … #define PI_FMC_DESCR_V_FSB_ERROR … #define PI_FMC_DESCR_V_FSB_ADDR_RECOG … #define PI_FMC_DESCR_V_FSB_ADDR_COPIED … #define PI_FMC_DESCR_V_FSB … #define PI_FMC_DESCR_V_RCC_FLUSH … #define PI_FMC_DESCR_V_RCC_CRC … #define PI_FMC_DESCR_V_RCC_RRR … #define PI_FMC_DESCR_V_RCC_DD … #define PI_FMC_DESCR_V_RCC_SS … #define PI_FMC_DESCR_V_RCC … #define PI_FMC_DESCR_V_LEN … #define PI_FMC_DESCR_M_SOP … #define PI_FMC_DESCR_M_EOP … #define PI_FMC_DESCR_M_FSC … #define PI_FMC_DESCR_M_FSB_ERROR … #define PI_FMC_DESCR_M_FSB_ADDR_RECOG … #define PI_FMC_DESCR_M_FSB_ADDR_COPIED … #define PI_FMC_DESCR_M_FSB … #define PI_FMC_DESCR_M_RCC_FLUSH … #define PI_FMC_DESCR_M_RCC_CRC … #define PI_FMC_DESCR_M_RCC_RRR … #define PI_FMC_DESCR_M_RCC_DD … #define PI_FMC_DESCR_M_RCC_SS … #define PI_FMC_DESCR_M_RCC … #define PI_FMC_DESCR_M_LEN … #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR … #define PI_FMC_DESCR_K_RRR_SUCCESS … #define PI_FMC_DESCR_K_RRR_SA_MATCH … #define PI_FMC_DESCR_K_RRR_DA_MATCH … #define PI_FMC_DESCR_K_RRR_FMC_ABORT … #define PI_FMC_DESCR_K_RRR_LENGTH_BAD … #define PI_FMC_DESCR_K_RRR_FRAGMENT … #define PI_FMC_DESCR_K_RRR_FORMAT_ERR … #define PI_FMC_DESCR_K_RRR_MAC_RESET … #define PI_FMC_DESCR_K_DD_NO_MATCH … #define PI_FMC_DESCR_K_DD_PROMISCUOUS … #define PI_FMC_DESCR_K_DD_CAM_MATCH … #define PI_FMC_DESCR_K_DD_LOCAL_MATCH … #define PI_FMC_DESCR_K_SS_NO_MATCH … #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH … #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE … #define PI_FMC_DESCR_K_SS_LOCAL_MATCH … /* Define some max buffer sizes */ #define PI_CMD_REQ_K_SIZE_MAX … #define PI_CMD_RSP_K_SIZE_MAX … #define PI_UNSOL_K_SIZE_MAX … #define PI_SMT_HOST_K_SIZE_MAX … #define PI_RCV_DATA_K_SIZE_MAX … #define PI_XMT_DATA_K_SIZE_MAX … /* Define adapter states */ #define PI_STATE_K_RESET … #define PI_STATE_K_UPGRADE … #define PI_STATE_K_DMA_UNAVAIL … #define PI_STATE_K_DMA_AVAIL … #define PI_STATE_K_LINK_AVAIL … #define PI_STATE_K_LINK_UNAVAIL … #define PI_STATE_K_HALTED … #define PI_STATE_K_RING_MEMBER … #define PI_STATE_K_NUMBER … /* Define codes for command type */ #define PI_CMD_K_START … #define PI_CMD_K_FILTERS_SET … #define PI_CMD_K_FILTERS_GET … #define PI_CMD_K_CHARS_SET … #define PI_CMD_K_STATUS_CHARS_GET … #define PI_CMD_K_CNTRS_GET … #define PI_CMD_K_CNTRS_SET … #define PI_CMD_K_ADDR_FILTER_SET … #define PI_CMD_K_ADDR_FILTER_GET … #define PI_CMD_K_ERROR_LOG_CLEAR … #define PI_CMD_K_ERROR_LOG_GET … #define PI_CMD_K_FDDI_MIB_GET … #define PI_CMD_K_DEC_EXT_MIB_GET … #define PI_CMD_K_DEVICE_SPECIFIC_GET … #define PI_CMD_K_SNMP_SET … #define PI_CMD_K_UNSOL_TEST … #define PI_CMD_K_SMT_MIB_GET … #define PI_CMD_K_SMT_MIB_SET … #define PI_CMD_K_MAX … /* Define item codes for Chars_Set and Filters_Set commands */ #define PI_ITEM_K_EOL … #define PI_ITEM_K_T_REQ … #define PI_ITEM_K_TVX … #define PI_ITEM_K_RESTRICTED_TOKEN … #define PI_ITEM_K_LEM_THRESHOLD … #define PI_ITEM_K_RING_PURGER … #define PI_ITEM_K_CNTR_INTERVAL … #define PI_ITEM_K_IND_GROUP_PROM … #define PI_ITEM_K_GROUP_PROM … #define PI_ITEM_K_BROADCAST … #define PI_ITEM_K_SMT_PROM … #define PI_ITEM_K_SMT_USER … #define PI_ITEM_K_RESERVED … #define PI_ITEM_K_IMPLEMENTOR … #define PI_ITEM_K_LOOPBACK_MODE … #define PI_ITEM_K_CONFIG_POLICY … #define PI_ITEM_K_CON_POLICY … #define PI_ITEM_K_T_NOTIFY … #define PI_ITEM_K_STATION_ACTION … #define PI_ITEM_K_MAC_PATHS_REQ … #define PI_ITEM_K_MAC_ACTION … #define PI_ITEM_K_CON_POLICIES … #define PI_ITEM_K_PORT_PATHS_REQ … #define PI_ITEM_K_MAC_LOOP_TIME … #define PI_ITEM_K_TB_MAX … #define PI_ITEM_K_LER_CUTOFF … #define PI_ITEM_K_LER_ALARM … #define PI_ITEM_K_PORT_ACTION … #define PI_ITEM_K_FLUSH_TIME … #define PI_ITEM_K_MAC_T_REQ … #define PI_ITEM_K_EMAC_RING_PURGER … #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT … #define PI_ITEM_K_FDX_ENB_DIS … #define PI_ITEM_K_MAX … /* Values for some of the items */ #define PI_K_FALSE … #define PI_K_TRUE … #define PI_SNMP_K_TRUE … #define PI_SNMP_K_FALSE … #define PI_FSTATE_K_BLOCK … #define PI_FSTATE_K_PASS … /* Define command return codes */ #define PI_RSP_K_SUCCESS … #define PI_RSP_K_FAILURE … #define PI_RSP_K_WARNING … #define PI_RSP_K_LOOP_MODE_BAD … #define PI_RSP_K_ITEM_CODE_BAD … #define PI_RSP_K_TVX_BAD … #define PI_RSP_K_TREQ_BAD … #define PI_RSP_K_TOKEN_BAD … #define PI_RSP_K_NO_EOL … #define PI_RSP_K_FILTER_STATE_BAD … #define PI_RSP_K_CMD_TYPE_BAD … #define PI_RSP_K_ADAPTER_STATE_BAD … #define PI_RSP_K_RING_PURGER_BAD … #define PI_RSP_K_LEM_THRESHOLD_BAD … #define PI_RSP_K_LOOP_NOT_SUPPORTED … #define PI_RSP_K_FLUSH_TIME_BAD … #define PI_RSP_K_NOT_IMPLEMENTED … #define PI_RSP_K_CONFIG_POLICY_BAD … #define PI_RSP_K_STATION_ACTION_BAD … #define PI_RSP_K_MAC_ACTION_BAD … #define PI_RSP_K_CON_POLICIES_BAD … #define PI_RSP_K_MAC_LOOP_TIME_BAD … #define PI_RSP_K_TB_MAX_BAD … #define PI_RSP_K_LER_CUTOFF_BAD … #define PI_RSP_K_LER_ALARM_BAD … #define PI_RSP_K_MAC_PATHS_REQ_BAD … #define PI_RSP_K_MAC_T_REQ_BAD … #define PI_RSP_K_EMAC_RING_PURGER_BAD … #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD … #define PI_RSP_K_NO_SUCH_ENTRY … #define PI_RSP_K_T_NOTIFY_BAD … #define PI_RSP_K_TR_MAX_EXP_BAD … #define PI_RSP_K_MAC_FRM_ERR_THR_BAD … #define PI_RSP_K_MAX_T_REQ_BAD … #define PI_RSP_K_FDX_ENB_DIS_BAD … #define PI_RSP_K_ITEM_INDEX_BAD … #define PI_RSP_K_PORT_ACTION_BAD … /* Commonly used structures */ PI_ITEM_LIST; PI_RSP_HEADER; /* Start Command */ PI_CMD_START_REQ; /* Start Response */ PI_CMD_START_RSP; /* Filters_Set Request */ #define PI_CMD_FILTERS_SET_K_ITEMS_MAX … PI_CMD_FILTERS_SET_REQ; /* Filters_Set Response */ PI_CMD_FILTERS_SET_RSP; /* Filters_Get Request */ PI_CMD_FILTERS_GET_REQ; /* Filters_Get Response */ PI_CMD_FILTERS_GET_RSP; /* Chars_Set Request */ #define PI_CMD_CHARS_SET_K_ITEMS_MAX … PI_CMD_CHARS_SET_REQ; /* Chars_Set Response */ PI_CMD_CHARS_SET_RSP; /* SNMP_Set Request */ #define PI_CMD_SNMP_SET_K_ITEMS_MAX … PI_CMD_SNMP_SET_REQ; /* SNMP_Set Response */ PI_CMD_SNMP_SET_RSP; /* SMT_MIB_Set Request */ #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX … PI_CMD_SMT_MIB_SET_REQ; /* SMT_MIB_Set Response */ PI_CMD_SMT_MIB_SET_RSP; /* SMT_MIB_Get Request */ PI_CMD_SMT_MIB_GET_REQ; /* SMT_MIB_Get Response */ PI_CMD_SMT_MIB_GET_RSP; /* * Item and group code definitions for SMT 7.3 mandatory objects. These * definitions are to be used as appropriate in SMT_MIB_SET commands and * certain host-sent SMT frames such as PMF Get and Set requests. The * codes have been taken from the MIB summary section of ANSI SMT 7.3. */ #define PI_GRP_K_SMT_STATION_ID … #define PI_ITEM_K_SMT_STATION_ID … #define PI_ITEM_K_SMT_OP_VERS_ID … #define PI_ITEM_K_SMT_HI_VERS_ID … #define PI_ITEM_K_SMT_LO_VERS_ID … #define PI_ITEM_K_SMT_USER_DATA … #define PI_ITEM_K_SMT_MIB_VERS_ID … #define PI_GRP_K_SMT_STATION_CONFIG … #define PI_ITEM_K_SMT_MAC_CT … #define PI_ITEM_K_SMT_NON_MASTER_CT … #define PI_ITEM_K_SMT_MASTER_CT … #define PI_ITEM_K_SMT_AVAIL_PATHS … #define PI_ITEM_K_SMT_CONFIG_CAPS … #define PI_ITEM_K_SMT_CONFIG_POL … #define PI_ITEM_K_SMT_CONN_POL … #define PI_ITEM_K_SMT_T_NOTIFY … #define PI_ITEM_K_SMT_STAT_POL … #define PI_ITEM_K_SMT_TR_MAX_EXP … #define PI_ITEM_K_SMT_PORT_INDEXES … #define PI_ITEM_K_SMT_MAC_INDEXES … #define PI_ITEM_K_SMT_BYPASS_PRESENT … #define PI_GRP_K_SMT_STATUS … #define PI_ITEM_K_SMT_ECM_STATE … #define PI_ITEM_K_SMT_CF_STATE … #define PI_ITEM_K_SMT_REM_DISC_FLAG … #define PI_ITEM_K_SMT_STATION_STATUS … #define PI_ITEM_K_SMT_PEER_WRAP_FLAG … #define PI_GRP_K_SMT_MIB_OPERATION … #define PI_ITEM_K_SMT_MSG_TIME_STAMP … #define PI_ITEM_K_SMT_TRN_TIME_STAMP … #define PI_ITEM_K_SMT_STATION_ACT … #define PI_GRP_K_MAC_CAPABILITIES … #define PI_ITEM_K_MAC_FRM_STAT_FUNC … #define PI_ITEM_K_MAC_T_MAX_CAP … #define PI_ITEM_K_MAC_TVX_CAP … #define PI_GRP_K_MAC_CONFIG … #define PI_ITEM_K_MAC_AVAIL_PATHS … #define PI_ITEM_K_MAC_CURRENT_PATH … #define PI_ITEM_K_MAC_UP_NBR … #define PI_ITEM_K_MAC_DOWN_NBR … #define PI_ITEM_K_MAC_OLD_UP_NBR … #define PI_ITEM_K_MAC_OLD_DOWN_NBR … #define PI_ITEM_K_MAC_DUP_ADDR_TEST … #define PI_ITEM_K_MAC_REQ_PATHS … #define PI_ITEM_K_MAC_DOWN_PORT_TYPE … #define PI_ITEM_K_MAC_INDEX … #define PI_GRP_K_MAC_ADDRESS … #define PI_ITEM_K_MAC_SMT_ADDRESS … #define PI_GRP_K_MAC_OPERATION … #define PI_ITEM_K_MAC_TREQ … #define PI_ITEM_K_MAC_TNEG … #define PI_ITEM_K_MAC_TMAX … #define PI_ITEM_K_MAC_TVX_VALUE … #define PI_GRP_K_MAC_COUNTERS … #define PI_ITEM_K_MAC_FRAME_CT … #define PI_ITEM_K_MAC_COPIED_CT … #define PI_ITEM_K_MAC_TRANSMIT_CT … #define PI_ITEM_K_MAC_ERROR_CT … #define PI_ITEM_K_MAC_LOST_CT … #define PI_GRP_K_MAC_FRM_ERR_COND … #define PI_ITEM_K_MAC_FRM_ERR_THR … #define PI_ITEM_K_MAC_FRM_ERR_RAT … #define PI_GRP_K_MAC_STATUS … #define PI_ITEM_K_MAC_RMT_STATE … #define PI_ITEM_K_MAC_DA_FLAG … #define PI_ITEM_K_MAC_UNDA_FLAG … #define PI_ITEM_K_MAC_FRM_ERR_FLAG … #define PI_ITEM_K_MAC_MA_UNIT_AVAIL … #define PI_ITEM_K_MAC_HW_PRESENT … #define PI_ITEM_K_MAC_MA_UNIT_ENAB … #define PI_GRP_K_PATH_CONFIG … #define PI_ITEM_K_PATH_INDEX … #define PI_ITEM_K_PATH_CONFIGURATION … #define PI_ITEM_K_PATH_TVX_LB … #define PI_ITEM_K_PATH_T_MAX_LB … #define PI_ITEM_K_PATH_MAX_T_REQ … #define PI_GRP_K_PORT_CONFIG … #define PI_ITEM_K_PORT_MY_TYPE … #define PI_ITEM_K_PORT_NBR_TYPE … #define PI_ITEM_K_PORT_CONN_POLS … #define PI_ITEM_K_PORT_MAC_INDICATED … #define PI_ITEM_K_PORT_CURRENT_PATH … #define PI_ITEM_K_PORT_REQ_PATHS … #define PI_ITEM_K_PORT_MAC_PLACEMENT … #define PI_ITEM_K_PORT_AVAIL_PATHS … #define PI_ITEM_K_PORT_PMD_CLASS … #define PI_ITEM_K_PORT_CONN_CAPS … #define PI_ITEM_K_PORT_INDEX … #define PI_GRP_K_PORT_OPERATION … #define PI_ITEM_K_PORT_BS_FLAG … #define PI_GRP_K_PORT_ERR_CNTRS … #define PI_ITEM_K_PORT_LCT_FAIL_CT … #define PI_GRP_K_PORT_LER … #define PI_ITEM_K_PORT_LER_ESTIMATE … #define PI_ITEM_K_PORT_LEM_REJ_CT … #define PI_ITEM_K_PORT_LEM_CT … #define PI_ITEM_K_PORT_LER_CUTOFF … #define PI_ITEM_K_PORT_LER_ALARM … #define PI_GRP_K_PORT_STATUS … #define PI_ITEM_K_PORT_CONNECT_STATE … #define PI_ITEM_K_PORT_PCM_STATE … #define PI_ITEM_K_PORT_PC_WITHHOLD … #define PI_ITEM_K_PORT_LER_FLAG … #define PI_ITEM_K_PORT_HW_PRESENT … #define PI_ITEM_K_PORT_ACT … /* Addr_Filter_Set Request */ #define PI_CMD_ADDR_FILTER_K_SIZE … PI_CMD_ADDR_FILTER_SET_REQ; /* Addr_Filter_Set Response */ PI_CMD_ADDR_FILTER_SET_RSP; /* Addr_Filter_Get Request */ PI_CMD_ADDR_FILTER_GET_REQ; /* Addr_Filter_Get Response */ PI_CMD_ADDR_FILTER_GET_RSP; /* Status_Chars_Get Request */ PI_CMD_STATUS_CHARS_GET_REQ; /* Status_Chars_Get Response */ PI_CMD_STATUS_CHARS_GET_RSP; /* FDDI_MIB_Get Request */ PI_CMD_FDDI_MIB_GET_REQ; /* FDDI_MIB_Get Response */ PI_CMD_FDDI_MIB_GET_RSP; /* DEC_Ext_MIB_Get Request */ PI_CMD_DEC_EXT_MIB_GET_REQ; /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */ PI_CMD_DEC_EXT_MIB_GET_RSP; PI_CNTR_BLK; /* Counters_Get Request */ PI_CMD_CNTRS_GET_REQ; /* Counters_Get Response */ PI_CMD_CNTRS_GET_RSP; /* Counters_Set Request */ PI_CMD_CNTRS_SET_REQ; /* Counters_Set Response */ PI_CMD_CNTRS_SET_RSP; /* Error_Log_Clear Request */ PI_CMD_ERROR_LOG_CLEAR_REQ; /* Error_Log_Clear Response */ PI_CMD_ERROR_LOG_CLEAR_RSP; /* Error_Log_Get Request */ #define PI_LOG_ENTRY_K_INDEX_MIN … PI_CMD_ERROR_LOG_GET_REQ; /* Error_Log_Get Response */ #define PI_K_LOG_FW_SIZE … #define PI_K_LOG_DIAG_SIZE … PI_LOG_ENTRY; PI_CMD_ERROR_LOG_GET_RSP; /* Define error log related constants and types. */ /* Not all of the caller id's can occur. The only ones currently */ /* implemented are: none, selftest, mfg, fw, console */ #define PI_LOG_EVENT_STATUS_K_VALID … #define PI_LOG_EVENT_STATUS_K_INVALID … #define PI_LOG_CALLER_ID_K_NONE … #define PI_LOG_CALLER_ID_K_SELFTEST … #define PI_LOG_CALLER_ID_K_MFG … #define PI_LOG_CALLER_ID_K_ONLINE … #define PI_LOG_CALLER_ID_K_HW … #define PI_LOG_CALLER_ID_K_FW … #define PI_LOG_CALLER_ID_K_CNS_HW … #define PI_LOG_CALLER_ID_K_CNS_FW … #define PI_LOG_CALLER_ID_K_CONSOLE … /* * Place all DMA commands in the following request and response structures * to simplify code. */ PI_DMA_CMD_REQ; PI_DMA_CMD_RSP; PI_DMA_CMD_BUFFER; /* Define format of Consumer Block (resident in host memory) */ PI_CONSUMER_BLOCK; #define PI_CONS_M_RCV_INDEX … #define PI_CONS_M_XMT_INDEX … #define PI_CONS_V_RCV_INDEX … #define PI_CONS_V_XMT_INDEX … /* Offsets into consumer block */ #define PI_CONS_BLK_K_XMT_RCV … #define PI_CONS_BLK_K_SMT_HOST … #define PI_CONS_BLK_K_UNSOL … #define PI_CONS_BLK_K_CMD_RSP … #define PI_CONS_BLK_K_CMD_REQ … /* Offsets into descriptor block */ #define PI_DESCR_BLK_K_RCV_DATA … #define PI_DESCR_BLK_K_XMT_DATA … #define PI_DESCR_BLK_K_SMT_HOST … #define PI_DESCR_BLK_K_UNSOL … #define PI_DESCR_BLK_K_CMD_RSP … #define PI_DESCR_BLK_K_CMD_REQ … /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */ /* Note a field has been added for later versions of the PDQ to allow for */ /* finer granularity of the rcv buffer alignment. For backwards */ /* compatibility, the two bits (which allow the rcv buffer to be longword */ /* aligned) have been added at the MBZ bits. To support previous drivers, */ /* the MBZ definition is left intact. */ PI_RCV_DESCR; #define PI_RCV_DESCR_M_SOP … #define PI_RCV_DESCR_M_SEG_LEN_LO … #define PI_RCV_DESCR_M_MBZ … #define PI_RCV_DESCR_M_SEG_LEN … #define PI_RCV_DESCR_M_SEG_LEN_HI … #define PI_RCV_DESCR_M_SEG_CNT … #define PI_RCV_DESCR_M_BUFF_HI … #define PI_RCV_DESCR_V_SOP … #define PI_RCV_DESCR_V_SEG_LEN_LO … #define PI_RCV_DESCR_V_MBZ … #define PI_RCV_DESCR_V_SEG_LEN … #define PI_RCV_DESCR_V_SEG_LEN_HI … #define PI_RCV_DESCR_V_SEG_CNT … #define PI_RCV_DESCR_V_BUFF_HI … /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */ PI_XMT_DESCR; #define PI_XMT_DESCR_M_SOP … #define PI_XMT_DESCR_M_EOP … #define PI_XMT_DESCR_M_MBZ … #define PI_XMT_DESCR_M_SEG_LEN … #define PI_XMT_DESCR_M_BUFF_HI … #define PI_XMT_DESCR_V_SOP … #define PI_XMT_DESCR_V_EOP … #define PI_XMT_DESCR_V_MBZ … #define PI_XMT_DESCR_V_SEG_LEN … #define PI_XMT_DESCR_V_BUFF_HI … /* Define format of the Descriptor Block (resident in host memory) */ #define PI_RCV_DATA_K_NUM_ENTRIES … #define PI_XMT_DATA_K_NUM_ENTRIES … #define PI_SMT_HOST_K_NUM_ENTRIES … #define PI_UNSOL_K_NUM_ENTRIES … #define PI_CMD_RSP_K_NUM_ENTRIES … #define PI_CMD_REQ_K_NUM_ENTRIES … PI_DESCR_BLOCK; /* Define Port Registers - offsets from PDQ Base address */ #define PI_PDQ_K_REG_PORT_RESET … #define PI_PDQ_K_REG_HOST_DATA … #define PI_PDQ_K_REG_PORT_CTRL … #define PI_PDQ_K_REG_PORT_DATA_A … #define PI_PDQ_K_REG_PORT_DATA_B … #define PI_PDQ_K_REG_PORT_STATUS … #define PI_PDQ_K_REG_TYPE_0_STATUS … #define PI_PDQ_K_REG_HOST_INT_ENB … #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT … #define PI_PDQ_K_REG_TYPE_2_PROD … #define PI_PDQ_K_REG_CMD_RSP_PROD … #define PI_PDQ_K_REG_CMD_REQ_PROD … #define PI_PDQ_K_REG_SMT_HOST_PROD … #define PI_PDQ_K_REG_UNSOL_PROD … /* Port Control Register - Command codes for primary commands */ #define PI_PCTRL_M_CMD_ERROR … #define PI_PCTRL_M_BLAST_FLASH … #define PI_PCTRL_M_HALT … #define PI_PCTRL_M_COPY_DATA … #define PI_PCTRL_M_ERROR_LOG_START … #define PI_PCTRL_M_ERROR_LOG_READ … #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE … #define PI_PCTRL_M_INIT … #define PI_PCTRL_M_INIT_START … #define PI_PCTRL_M_CONS_BLOCK … #define PI_PCTRL_M_UNINIT … #define PI_PCTRL_M_RING_MEMBER … #define PI_PCTRL_M_MLA … #define PI_PCTRL_M_FW_REV_READ … #define PI_PCTRL_M_DEV_SPECIFIC … #define PI_PCTRL_M_SUB_CMD … /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */ #define PI_SUB_CMD_K_LINK_UNINIT … #define PI_SUB_CMD_K_BURST_SIZE_SET … #define PI_SUB_CMD_K_PDQ_REV_GET … #define PI_SUB_CMD_K_HW_REV_GET … /* Define some Port Data B values */ #define PI_PDATA_B_DMA_BURST_SIZE_4 … #define PI_PDATA_B_DMA_BURST_SIZE_8 … #define PI_PDATA_B_DMA_BURST_SIZE_16 … #define PI_PDATA_B_DMA_BURST_SIZE_32 … #define PI_PDATA_B_DMA_BURST_SIZE_DEF … /* Port Data A Reset state */ #define PI_PDATA_A_RESET_M_UPGRADE … #define PI_PDATA_A_RESET_M_SOFT_RESET … #define PI_PDATA_A_RESET_M_SKIP_ST … /* Read adapter MLA address port control command constants */ #define PI_PDATA_A_MLA_K_LO … #define PI_PDATA_A_MLA_K_HI … /* Byte Swap values for init command */ #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR … #define PI_PDATA_A_INIT_M_RESERVED … #define PI_PDATA_A_INIT_M_BSWAP_DATA … #define PI_PDATA_A_INIT_M_BSWAP_LITERAL … #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR … #define PI_PDATA_A_INIT_V_RESERVED … #define PI_PDATA_A_INIT_V_BSWAP_DATA … #define PI_PDATA_A_INIT_V_BSWAP_LITERAL … /* Port Reset Register */ #define PI_RESET_M_ASSERT_RESET … /* Port Status register */ #define PI_PSTATUS_V_RCV_DATA_PENDING … #define PI_PSTATUS_V_XMT_DATA_PENDING … #define PI_PSTATUS_V_SMT_HOST_PENDING … #define PI_PSTATUS_V_UNSOL_PENDING … #define PI_PSTATUS_V_CMD_RSP_PENDING … #define PI_PSTATUS_V_CMD_REQ_PENDING … #define PI_PSTATUS_V_TYPE_0_PENDING … #define PI_PSTATUS_V_RESERVED_1 … #define PI_PSTATUS_V_RESERVED_2 … #define PI_PSTATUS_V_STATE … #define PI_PSTATUS_V_HALT_ID … #define PI_PSTATUS_M_RCV_DATA_PENDING … #define PI_PSTATUS_M_XMT_DATA_PENDING … #define PI_PSTATUS_M_SMT_HOST_PENDING … #define PI_PSTATUS_M_UNSOL_PENDING … #define PI_PSTATUS_M_CMD_RSP_PENDING … #define PI_PSTATUS_M_CMD_REQ_PENDING … #define PI_PSTATUS_M_TYPE_0_PENDING … #define PI_PSTATUS_M_RESERVED_1 … #define PI_PSTATUS_M_RESERVED_2 … #define PI_PSTATUS_M_STATE … #define PI_PSTATUS_M_HALT_ID … /* Define Halt Id's */ /* Do not insert into this list, only append. */ #define PI_HALT_ID_K_SELFTEST_TIMEOUT … #define PI_HALT_ID_K_PARITY_ERROR … #define PI_HALT_ID_K_HOST_DIR_HALT … #define PI_HALT_ID_K_SW_FAULT … #define PI_HALT_ID_K_HW_FAULT … #define PI_HALT_ID_K_PC_TRACE … #define PI_HALT_ID_K_DMA_ERROR … #define PI_HALT_ID_K_IMAGE_CRC_ERROR … #define PI_HALT_ID_K_BUS_EXCEPTION … /* Host Interrupt Enable Register as seen by host */ #define PI_HOST_INT_M_XMT_DATA_ENB … #define PI_HOST_INT_M_RCV_DATA_ENB … #define PI_HOST_INT_M_SMT_HOST_ENB … #define PI_HOST_INT_M_UNSOL_ENB … #define PI_HOST_INT_M_CMD_RSP_ENB … #define PI_HOST_INT_M_CMD_REQ_ENB … #define PI_HOST_INT_M_TYPE_1_RESERVED … #define PI_HOST_INT_M_TYPE_0_RESERVED … #define PI_HOST_INT_M_1MS … #define PI_HOST_INT_M_20MS … #define PI_HOST_INT_M_CSR_CMD_DONE … #define PI_HOST_INT_M_STATE_CHANGE … #define PI_HOST_INT_M_XMT_FLUSH … #define PI_HOST_INT_M_NXM … #define PI_HOST_INT_M_PM_PAR_ERR … #define PI_HOST_INT_M_BUS_PAR_ERR … #define PI_HOST_INT_V_XMT_DATA_ENB … #define PI_HOST_INT_V_RCV_DATA_ENB … #define PI_HOST_INT_V_SMT_HOST_ENB … #define PI_HOST_INT_V_UNSOL_ENB … #define PI_HOST_INT_V_CMD_RSP_ENB … #define PI_HOST_INT_V_CMD_REQ_ENB … #define PI_HOST_INT_V_TYPE_1_RESERVED … #define PI_HOST_INT_V_TYPE_0_RESERVED … #define PI_HOST_INT_V_1MS_ENB … #define PI_HOST_INT_V_20MS_ENB … #define PI_HOST_INT_V_CSR_CMD_DONE_ENB … #define PI_HOST_INT_V_STATE_CHANGE_ENB … #define PI_HOST_INT_V_XMT_FLUSH_ENB … #define PI_HOST_INT_V_NXM_ENB … #define PI_HOST_INT_V_PM_PAR_ERR_ENB … #define PI_HOST_INT_V_BUS_PAR_ERR_ENB … #define PI_HOST_INT_K_ACK_ALL_TYPE_0 … #define PI_HOST_INT_K_DISABLE_ALL_INTS … #define PI_HOST_INT_K_ENABLE_ALL_INTS … #define PI_HOST_INT_K_ENABLE_DEF_INTS … /* Type 0 Interrupt Status Register */ #define PI_TYPE_0_STAT_M_1MS … #define PI_TYPE_0_STAT_M_20MS … #define PI_TYPE_0_STAT_M_CSR_CMD_DONE … #define PI_TYPE_0_STAT_M_STATE_CHANGE … #define PI_TYPE_0_STAT_M_XMT_FLUSH … #define PI_TYPE_0_STAT_M_NXM … #define PI_TYPE_0_STAT_M_PM_PAR_ERR … #define PI_TYPE_0_STAT_M_BUS_PAR_ERR … #define PI_TYPE_0_STAT_V_1MS … #define PI_TYPE_0_STAT_V_20MS … #define PI_TYPE_0_STAT_V_CSR_CMD_DONE … #define PI_TYPE_0_STAT_V_STATE_CHANGE … #define PI_TYPE_0_STAT_V_XMT_FLUSH … #define PI_TYPE_0_STAT_V_NXM … #define PI_TYPE_0_STAT_V_PM_PAR_ERR … #define PI_TYPE_0_STAT_V_BUS_PAR_ERR … /* Register definition structures are defined for both big and little endian systems */ #ifndef __BIG_ENDIAN /* Little endian format of Type 1 Producer register */ PI_TYPE_1_PROD_REG; /* Little endian format of Type 2 Producer register */ PI_TYPE_2_PROD_REG; /* Little endian format of Type 1 Consumer Block longword */ PI_TYPE_1_CONSUMER; /* Little endian format of Type 2 Consumer Block longword */ PI_TYPE_2_CONSUMER; /* Define swapping required by DMA transfers. */ #define PI_PDATA_A_INIT_M_BSWAP_INIT … #else /* __BIG_ENDIAN */ /* Big endian format of Type 1 Producer register */ typedef union { PI_UINT32 lword; struct { PI_UINT8 mbz_2; PI_UINT8 mbz_1; PI_UINT8 comp; PI_UINT8 prod; } index; } PI_TYPE_1_PROD_REG; /* Big endian format of Type 2 Producer register */ typedef union { PI_UINT32 lword; struct { PI_UINT8 xmt_comp; PI_UINT8 rcv_comp; PI_UINT8 xmt_prod; PI_UINT8 rcv_prod; } index; } PI_TYPE_2_PROD_REG; /* Big endian format of Type 1 Consumer Block longword */ typedef union { PI_UINT32 lword; struct { PI_UINT8 res2; PI_UINT8 res1; PI_UINT8 res0; PI_UINT8 cons; } index; } PI_TYPE_1_CONSUMER; /* Big endian format of Type 2 Consumer Block longword */ typedef union { PI_UINT32 lword; struct { PI_UINT8 res1; PI_UINT8 xmt_cons; PI_UINT8 res0; PI_UINT8 rcv_cons; } index; } PI_TYPE_2_CONSUMER; /* Define swapping required by DMA transfers. */ #define PI_PDATA_A_INIT_M_BSWAP_INIT … #endif /* __BIG_ENDIAN */ /* Define TC PDQ CSR offset and length */ #define PI_TC_K_CSR_OFFSET … #define PI_TC_K_CSR_LEN … /* Define EISA controller register offsets */ #define PI_ESIC_K_CSR_IO_LEN … #define PI_ESIC_K_BURST_HOLDOFF_LEN … #define PI_ESIC_K_ESIC_CSR_LEN … #define PI_DEFEA_K_CSR_IO … #define PI_DEFEA_K_BURST_HOLDOFF … #define PI_ESIC_K_ESIC_CSR … #define PI_ESIC_K_SLOT_ID … #define PI_ESIC_K_SLOT_CNTRL … #define PI_ESIC_K_MEM_ADD_CMP_0 … #define PI_ESIC_K_MEM_ADD_CMP_1 … #define PI_ESIC_K_MEM_ADD_CMP_2 … #define PI_ESIC_K_MEM_ADD_HI_CMP_0 … #define PI_ESIC_K_MEM_ADD_HI_CMP_1 … #define PI_ESIC_K_MEM_ADD_HI_CMP_2 … #define PI_ESIC_K_MEM_ADD_MASK_0 … #define PI_ESIC_K_MEM_ADD_MASK_1 … #define PI_ESIC_K_MEM_ADD_MASK_2 … #define PI_ESIC_K_MEM_ADD_LO_CMP_0 … #define PI_ESIC_K_MEM_ADD_LO_CMP_1 … #define PI_ESIC_K_MEM_ADD_LO_CMP_2 … #define PI_ESIC_K_IO_ADD_CMP_0_0 … #define PI_ESIC_K_IO_ADD_CMP_0_1 … #define PI_ESIC_K_IO_ADD_CMP_1_0 … #define PI_ESIC_K_IO_ADD_CMP_1_1 … #define PI_ESIC_K_IO_ADD_CMP_2_0 … #define PI_ESIC_K_IO_ADD_CMP_2_1 … #define PI_ESIC_K_IO_ADD_CMP_3_0 … #define PI_ESIC_K_IO_ADD_CMP_3_1 … #define PI_ESIC_K_IO_ADD_MASK_0_0 … #define PI_ESIC_K_IO_ADD_MASK_0_1 … #define PI_ESIC_K_IO_ADD_MASK_1_0 … #define PI_ESIC_K_IO_ADD_MASK_1_1 … #define PI_ESIC_K_IO_ADD_MASK_2_0 … #define PI_ESIC_K_IO_ADD_MASK_2_1 … #define PI_ESIC_K_IO_ADD_MASK_3_0 … #define PI_ESIC_K_IO_ADD_MASK_3_1 … #define PI_ESIC_K_MOD_CONFIG_1 … #define PI_ESIC_K_MOD_CONFIG_2 … #define PI_ESIC_K_MOD_CONFIG_3 … #define PI_ESIC_K_MOD_CONFIG_4 … #define PI_ESIC_K_MOD_CONFIG_5 … #define PI_ESIC_K_MOD_CONFIG_6 … #define PI_ESIC_K_MOD_CONFIG_7 … #define PI_ESIC_K_DIP_SWITCH … #define PI_ESIC_K_IO_CONFIG_STAT_0 … #define PI_ESIC_K_IO_CONFIG_STAT_1 … #define PI_ESIC_K_DMA_CONFIG … #define PI_ESIC_K_INPUT_PORT … #define PI_ESIC_K_OUTPUT_PORT … #define PI_ESIC_K_FUNCTION_CNTRL … /* Define the bits in the function control register. */ #define PI_FUNCTION_CNTRL_M_IOCS0 … #define PI_FUNCTION_CNTRL_M_IOCS1 … #define PI_FUNCTION_CNTRL_M_IOCS2 … #define PI_FUNCTION_CNTRL_M_IOCS3 … #define PI_FUNCTION_CNTRL_M_MEMCS0 … #define PI_FUNCTION_CNTRL_M_MEMCS1 … #define PI_FUNCTION_CNTRL_M_DMA … /* Define the bits in the slot control register. */ #define PI_SLOT_CNTRL_M_RESET … #define PI_SLOT_CNTRL_M_ERROR … #define PI_SLOT_CNTRL_M_ENB … /* Define the bits in the burst holdoff register. */ #define PI_BURST_HOLDOFF_M_HOLDOFF … #define PI_BURST_HOLDOFF_M_RESERVED … #define PI_BURST_HOLDOFF_M_MEM_MAP … #define PI_BURST_HOLDOFF_V_HOLDOFF … #define PI_BURST_HOLDOFF_V_RESERVED … #define PI_BURST_HOLDOFF_V_MEM_MAP … /* Define the implicit mask of the Memory Address Compare registers. */ #define PI_MEM_ADD_MASK_M … /* Define the fields in the I/O Address Compare and Mask registers. */ #define PI_IO_CMP_M_SLOT … #define PI_IO_CMP_V_SLOT … /* Define the fields in the Interrupt Channel Configuration and Status reg */ #define PI_CONFIG_STAT_0_M_PEND … #define PI_CONFIG_STAT_0_M_RES_1 … #define PI_CONFIG_STAT_0_M_IREQ_OUT … #define PI_CONFIG_STAT_0_M_IREQ_IN … #define PI_CONFIG_STAT_0_M_INT_ENB … #define PI_CONFIG_STAT_0_M_RES_0 … #define PI_CONFIG_STAT_0_M_IRQ … #define PI_CONFIG_STAT_0_V_PEND … #define PI_CONFIG_STAT_0_V_RES_1 … #define PI_CONFIG_STAT_0_V_IREQ_OUT … #define PI_CONFIG_STAT_0_V_IREQ_IN … #define PI_CONFIG_STAT_0_V_INT_ENB … #define PI_CONFIG_STAT_0_V_RES_0 … #define PI_CONFIG_STAT_0_V_IRQ … #define PI_CONFIG_STAT_0_IRQ_K_9 … #define PI_CONFIG_STAT_0_IRQ_K_10 … #define PI_CONFIG_STAT_0_IRQ_K_11 … #define PI_CONFIG_STAT_0_IRQ_K_15 … /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */ #define DEFEA_PRODUCT_ID … #define DEFEA_PROD_ID_1 … #define DEFEA_PROD_ID_2 … #define DEFEA_PROD_ID_3 … #define DEFEA_PROD_ID_4 … /**********************************************/ /* Digital PFI Specification v1.0 Definitions */ /**********************************************/ /* PCI Configuration Space Constants */ #define PFI_K_LAT_TIMER_DEF … #define PFI_K_LAT_TIMER_MIN … #define PFI_K_CSR_MEM_LEN … #define PFI_K_CSR_IO_LEN … #define PFI_K_PKT_MEM_LEN … /* PFI Register Offsets (starting at PDQ Register Base Address) */ #define PFI_K_REG_RESERVED_0 … #define PFI_K_REG_RESERVED_1 … #define PFI_K_REG_MODE_CTRL … #define PFI_K_REG_STATUS … #define PFI_K_REG_FIFO_WRITE … #define PFI_K_REG_FIFO_READ … /* PFI Mode Control Register Constants */ #define PFI_MODE_M_RESERVED … #define PFI_MODE_M_TGT_ABORT_ENB … #define PFI_MODE_M_PDQ_INT_ENB … #define PFI_MODE_M_PFI_INT_ENB … #define PFI_MODE_M_DMA_ENB … #define PFI_MODE_V_RESERVED … #define PFI_MODE_V_TGT_ABORT_ENB … #define PFI_MODE_V_PDQ_INT_ENB … #define PFI_MODE_V_PFI_INT_ENB … #define PFI_MODE_V_DMA_ENB … #define PFI_MODE_K_ALL_DISABLE … /* PFI Status Register Constants */ #define PFI_STATUS_M_RESERVED … #define PFI_STATUS_M_PFI_ERROR … #define PFI_STATUS_M_PDQ_INT … #define PFI_STATUS_M_PDQ_DMA_ABORT … #define PFI_STATUS_M_FIFO_FULL … #define PFI_STATUS_M_FIFO_EMPTY … #define PFI_STATUS_M_DMA_IN_PROGRESS … #define PFI_STATUS_V_RESERVED … #define PFI_STATUS_V_PFI_ERROR … #define PFI_STATUS_V_PDQ_INT … #define PFI_STATUS_V_PDQ_DMA_ABORT … #define PFI_STATUS_V_FIFO_FULL … #define PFI_STATUS_V_FIFO_EMPTY … #define PFI_STATUS_V_DMA_IN_PROGRESS … #define DFX_FC_PRH2_PRH1_PRH0 … #define DFX_PRH0_BYTE … #define DFX_PRH1_BYTE … #define DFX_PRH2_BYTE … /* Driver routine status (return) codes */ #define DFX_K_SUCCESS … #define DFX_K_FAILURE … #define DFX_K_OUTSTATE … #define DFX_K_HW_TIMEOUT … /* Define LLC host receive buffer min/max/default values */ #define RCV_BUFS_MIN … #define RCV_BUFS_MAX … #define RCV_BUFS_DEF … /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */ #define RCV_BUFF_K_DESCR … #define RCV_BUFF_K_PADDING … #define RCV_BUFF_K_FC … #define RCV_BUFF_K_DA … #define RCV_BUFF_K_SA … #define RCV_BUFF_K_DATA … /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */ #define XMT_BUFF_K_FC … #define XMT_BUFF_K_DA … #define XMT_BUFF_K_SA … #define XMT_BUFF_K_DATA … /* Macro for checking a "value" is within a specific range */ #define IN_RANGE(value,low,high) … /* Only execute special print call when debug driver was built */ #ifdef DEFXX_DEBUG #define DBG_printk … #else #define DBG_printk(args...) … #endif /* Define constants for masking/unmasking interrupts */ #define DFX_MASK_INTERRUPTS … #define DFX_UNMASK_INTERRUPTS … /* Define structure for driver transmit descriptor block */ XMT_DRIVER_DESCR; DFX_board_t; #endif /* #ifndef _DEFXX_H_ */
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