linux/drivers/net/ipa/reg/ipa_reg-v4.11.c

// SPDX-License-Identifier: GPL-2.0

/* Copyright (C) 2022-2024 Linaro Ltd. */

#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/types.h>

#include "../ipa_reg.h"
#include "../ipa_version.h"

static const u32 reg_comp_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_clkon_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_route_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_shared_mem_size_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_qsb_max_writes_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_qsb_max_reads_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_filt_rout_hash_flush_fmask[] = …;

REG_FIELDS(…);

/* Valid bits defined by ipa->available */
REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);

static const u32 reg_local_pkt_proc_cntxt_fmask[] = …;

/* Offset must be a multiple of 8 */
REG_FIELDS(…);

/* Valid bits defined by ipa->available */
REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);

static const u32 reg_ipa_tx_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_flavor_0_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_idle_indication_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_qtime_timestamp_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_timers_xo_clk_div_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_timers_pulse_gran_cfg_fmask[] = …;

REG_FIELDS(…);

static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_cfg_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_nat_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_hdr_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_hdr_ext_fmask[] = …;

REG_STRIDE_FIELDS(…);

REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
	   0x00000818, 0x0070);

static const u32 reg_endp_init_mode_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_aggr_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_hol_block_en_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_hol_block_timer_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_deaggr_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_rsrc_grp_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_init_seq_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_status_fmask[] = …;

REG_STRIDE_FIELDS(…);

static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = …;

REG_STRIDE_FIELDS(…);

/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);

/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);

/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);

static const u32 reg_ipa_irq_uc_fmask[] = …;

REG_FIELDS(…);

/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
	   0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);

/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
	   0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);

/* Valid bits defined by ipa->available */
REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
	   0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);

static const struct reg *reg_array[] = …;

const struct regs ipa_regs_v4_11 = …;