/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Freescale QUICC Engine HDLC Device Driver * * Copyright 2014 Freescale Semiconductor Inc. */ #ifndef _UCC_HDLC_H_ #define _UCC_HDLC_H_ #include <linux/kernel.h> #include <linux/list.h> #include <soc/fsl/qe/immap_qe.h> #include <soc/fsl/qe/qe.h> #include <soc/fsl/qe/ucc.h> #include <soc/fsl/qe/ucc_fast.h> /* UCC HDLC event register */ #define UCCE_HDLC_RX_EVENTS … #define UCCE_HDLC_TX_EVENTS … struct ucc_hdlc_param { … }; struct ucc_hdlc_private { … }; #define TX_BD_RING_LEN … #define RX_BD_RING_LEN … #define RX_CLEAN_MAX … #define NUM_OF_BUF … #define MAX_RX_BUF_LENGTH … #define MAX_FRAME_LENGTH … #define ALIGNMENT_OF_UCC_HDLC_PRAM … #define SI_BANK_SIZE … #define MAX_HDLC_NUM … #define HDLC_HEAD_LEN … #define HDLC_CRC_SIZE … #define TX_RING_MOD_MASK(size) … #define RX_RING_MOD_MASK(size) … #define HDLC_HEAD_MASK … #define DEFAULT_HDLC_HEAD … #define DEFAULT_ADDR_MASK … #define DEFAULT_HDLC_ADDR … #define BMR_GBL … #define BMR_BIG_ENDIAN … #define CRC_16BIT_MASK … #define CRC_16BIT_PRES … #define DEFAULT_RFTHR … #define DEFAULT_PPP_HEAD … #endif
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