/* * Copyright (c) 2004-2008 Reyk Floeter <[email protected]> * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]> * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ /* * RX/TX descriptor structures */ /** * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor * @rx_control_0: RX control word 0 * @rx_control_1: RX control word 1 */ struct ath5k_hw_rx_ctl { … } __packed __aligned(…); /* RX control word 1 fields/flags */ #define AR5K_DESC_RX_CTL1_BUF_LEN … #define AR5K_DESC_RX_CTL1_INTREQ … /** * struct ath5k_hw_rx_status - Common hardware RX status descriptor * @rx_status_0: RX status word 0 * @rx_status_1: RX status word 1 * * 5210, 5211 and 5212 differ only in the fields and flags defined below */ struct ath5k_hw_rx_status { … } __packed __aligned(…); /* 5210/5211 */ /* RX status word 0 fields/flags */ #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN … #define AR5K_5210_RX_DESC_STATUS0_MORE … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211 … #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211_S … /* RX status word 1 fields/flags */ #define AR5K_5210_RX_DESC_STATUS1_DONE … #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK … #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR … #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 … #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR … #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR … #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S … #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID … #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX … #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S … #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP … #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S … #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS … /* 5212 */ /* RX status word 0 fields/flags */ #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN … #define AR5K_5212_RX_DESC_STATUS0_MORE … #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR … #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE … #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S … #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL … #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S … #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA … #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S … /* RX status word 1 fields/flags */ #define AR5K_5212_RX_DESC_STATUS1_DONE … #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK … #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR … #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR … #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR … #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR … #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID … #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX … #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S … #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP … #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S … #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS … #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE … #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE_S … /** * enum ath5k_phy_error_code - PHY Error codes * @AR5K_RX_PHY_ERROR_UNDERRUN: Transmit underrun, [5210] No error * @AR5K_RX_PHY_ERROR_TIMING: Timing error * @AR5K_RX_PHY_ERROR_PARITY: Illegal parity * @AR5K_RX_PHY_ERROR_RATE: Illegal rate * @AR5K_RX_PHY_ERROR_LENGTH: Illegal length * @AR5K_RX_PHY_ERROR_RADAR: Radar detect, [5210] 64 QAM rate * @AR5K_RX_PHY_ERROR_SERVICE: Illegal service * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive * @AR5K_RX_PHY_ERROR_OFDM_TIMING: OFDM Timing error [5212+] * @AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY: OFDM Signal parity error [5212+] * @AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL: OFDM Illegal rate [5212+] * @AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL: OFDM Illegal length [5212+] * @AR5K_RX_PHY_ERROR_OFDM_POWER_DROP: OFDM Power drop [5212+] * @AR5K_RX_PHY_ERROR_OFDM_SERVICE: OFDM Service (?) [5212+] * @AR5K_RX_PHY_ERROR_OFDM_RESTART: OFDM Restart (?) [5212+] * @AR5K_RX_PHY_ERROR_CCK_TIMING: CCK Timing error [5212+] * @AR5K_RX_PHY_ERROR_CCK_HEADER_CRC: Header CRC error [5212+] * @AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL: Illegal rate [5212+] * @AR5K_RX_PHY_ERROR_CCK_SERVICE: CCK Service (?) [5212+] * @AR5K_RX_PHY_ERROR_CCK_RESTART: CCK Restart (?) [5212+] */ enum ath5k_phy_error_code { … }; /** * struct ath5k_hw_2w_tx_ctl - 5210/5211 hardware 2-word TX control descriptor * @tx_control_0: TX control word 0 * @tx_control_1: TX control word 1 */ struct ath5k_hw_2w_tx_ctl { … } __packed __aligned(…); /* TX control word 0 fields/flags */ #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN … #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210 … #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210_S … #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE … #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S … #define AR5K_2W_TX_DESC_CTL0_RTSENA … #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210 … #define AR5K_2W_TX_DESC_CTL0_VEOL_5211 … #define AR5K_2W_TX_DESC_CTL0_CLRDMASK … #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 … #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 … #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT … #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S … #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210 … #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210_S … #define AR5K_2W_TX_DESC_CTL0_INTREQ … #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID … /* TX control word 1 fields/flags */ #define AR5K_2W_TX_DESC_CTL1_BUF_LEN … #define AR5K_2W_TX_DESC_CTL1_MORE … #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 … #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211 … #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX … #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_S … #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211 … #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211_S … #define AR5K_2W_TX_DESC_CTL1_NOACK_5211 … #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210 … /* Frame types */ #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL … #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM … #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL … #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY … #define AR5K_AR5211_TX_DESC_FRAME_TYPE_BEACON … #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS … #define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP … /** * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor * @tx_control_0: TX control word 0 * @tx_control_1: TX control word 1 * @tx_control_2: TX control word 2 * @tx_control_3: TX control word 3 */ struct ath5k_hw_4w_tx_ctl { … } __packed __aligned(…); /* TX control word 0 fields/flags */ #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN … #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER … #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S … #define AR5K_4W_TX_DESC_CTL0_RTSENA … #define AR5K_4W_TX_DESC_CTL0_VEOL … #define AR5K_4W_TX_DESC_CTL0_CLRDMASK … #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT … #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S … #define AR5K_4W_TX_DESC_CTL0_INTREQ … #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID … #define AR5K_4W_TX_DESC_CTL0_CTSENA … /* TX control word 1 fields/flags */ #define AR5K_4W_TX_DESC_CTL1_BUF_LEN … #define AR5K_4W_TX_DESC_CTL1_MORE … #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX … #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX_S … #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE … #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S … #define AR5K_4W_TX_DESC_CTL1_NOACK … #define AR5K_4W_TX_DESC_CTL1_COMP_PROC … #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S … #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN … #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S … #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN … #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S … /* TX control word 2 fields/flags */ #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION … #define AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 … #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S … /* TX control word 3 fields/flags */ #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 … #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 … #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S … #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 … #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S … #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 … #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S … #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE … #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S … /** * struct ath5k_hw_tx_status - Common TX status descriptor * @tx_status_0: TX status word 0 * @tx_status_1: TX status word 1 */ struct ath5k_hw_tx_status { … } __packed __aligned(…); /* TX status word 0 fields/flags */ #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK … #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES … #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN … #define AR5K_DESC_TX_STATUS0_FILTERED … /* according to the HAL sources the spec has short/long retry counts reversed. * we have it reversed to the HAL sources as well, for 5210 and 5211. * For 5212 these fields are defined as RTS_FAIL_COUNT and DATA_FAIL_COUNT, * but used respectively as SHORT and LONG retry count in the code later. This * is consistent with the definitions here... TODO: check */ #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT … #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S … #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT … #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S … #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211 … #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5212_S … #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP … #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S … /* TX status word 1 fields/flags */ #define AR5K_DESC_TX_STATUS1_DONE … #define AR5K_DESC_TX_STATUS1_SEQ_NUM … #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S … #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH … #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S … #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212 … #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212_S … #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 … #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 … /** * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor * @tx_ctl: The &struct ath5k_hw_2w_tx_ctl * @tx_stat: The &struct ath5k_hw_tx_status */ struct ath5k_hw_5210_tx_desc { … } __packed __aligned(…); /** * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor * @tx_ctl: The &struct ath5k_hw_4w_tx_ctl * @tx_stat: The &struct ath5k_hw_tx_status */ struct ath5k_hw_5212_tx_desc { … } __packed __aligned(…); /** * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor * @rx_ctl: The &struct ath5k_hw_rx_ctl * @rx_stat: The &struct ath5k_hw_rx_status */ struct ath5k_hw_all_rx_desc { … } __packed __aligned(…); /** * struct ath5k_desc - Atheros hardware DMA descriptor * @ds_link: Physical address of the next descriptor * @ds_data: Physical address of data buffer (skb) * @ud: Union containing hw_5xxx_tx_desc structs and hw_all_rx_desc * * This is read and written to by the hardware */ struct ath5k_desc { … } __packed __aligned(…); #define AR5K_RXDESC_INTREQ … #define AR5K_TXDESC_CLRDMASK … #define AR5K_TXDESC_NOACK … #define AR5K_TXDESC_RTSENA … #define AR5K_TXDESC_CTSENA … #define AR5K_TXDESC_INTREQ … #define AR5K_TXDESC_VEOL …
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