/* * Copyright (c) 2004-2008 Reyk Floeter <[email protected]> * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]> * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ /* * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) */ #define AR5K_EEPROM_PCIE_OFFSET … #define AR5K_EEPROM_PCIE_SERDES_SECTION … #define AR5K_EEPROM_MAGIC … #define AR5K_EEPROM_MAGIC_VALUE … #define AR5K_EEPROM_IS_HB63 … #define AR5K_EEPROM_RFKILL … #define AR5K_EEPROM_RFKILL_GPIO_SEL … #define AR5K_EEPROM_RFKILL_GPIO_SEL_S … #define AR5K_EEPROM_RFKILL_POLARITY … #define AR5K_EEPROM_RFKILL_POLARITY_S … #define AR5K_EEPROM_REG_DOMAIN … /* FLASH(EEPROM) Defines for AR531X chips */ #define AR5K_EEPROM_SIZE_LOWER … #define AR5K_EEPROM_SIZE_UPPER … #define AR5K_EEPROM_SIZE_UPPER_MASK … #define AR5K_EEPROM_SIZE_UPPER_SHIFT … #define AR5K_EEPROM_SIZE_ENDLOC_SHIFT … #define AR5K_EEPROM_CHECKSUM … #define AR5K_EEPROM_INFO_BASE … #define AR5K_EEPROM_INFO_MAX … #define AR5K_EEPROM_INFO_CKSUM … #define AR5K_EEPROM_INFO(_n) … #define AR5K_EEPROM_VERSION … #define AR5K_EEPROM_VERSION_3_0 … #define AR5K_EEPROM_VERSION_3_1 … #define AR5K_EEPROM_VERSION_3_2 … #define AR5K_EEPROM_VERSION_3_3 … #define AR5K_EEPROM_VERSION_3_4 … #define AR5K_EEPROM_VERSION_4_0 … #define AR5K_EEPROM_VERSION_4_1 … #define AR5K_EEPROM_VERSION_4_2 … #define AR5K_EEPROM_VERSION_4_3 … #define AR5K_EEPROM_VERSION_4_4 … #define AR5K_EEPROM_VERSION_4_5 … #define AR5K_EEPROM_VERSION_4_6 … #define AR5K_EEPROM_VERSION_4_7 … #define AR5K_EEPROM_VERSION_4_9 … #define AR5K_EEPROM_VERSION_5_0 … #define AR5K_EEPROM_VERSION_5_1 … #define AR5K_EEPROM_VERSION_5_3 … #define AR5K_EEPROM_MODE_11A … #define AR5K_EEPROM_MODE_11B … #define AR5K_EEPROM_MODE_11G … #define AR5K_EEPROM_HDR … #define AR5K_EEPROM_HDR_11A(_v) … #define AR5K_EEPROM_HDR_11B(_v) … #define AR5K_EEPROM_HDR_11G(_v) … #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) … #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) … #define AR5K_EEPROM_HDR_DEVICE(_v) … #define AR5K_EEPROM_HDR_RFKILL(_v) … #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) … /* Newer EEPROMs are using a different offset */ #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) … #define AR5K_EEPROM_ANT_GAIN(_v) … #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) … #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) … /* Misc values available since EEPROM 4.0 */ #define AR5K_EEPROM_MISC0 … #define AR5K_EEPROM_EARSTART(_v) … #define AR5K_EEPROM_HDR_XR2_DIS(_v) … #define AR5K_EEPROM_HDR_XR5_DIS(_v) … #define AR5K_EEPROM_EEMAP(_v) … #define AR5K_EEPROM_MISC1 … #define AR5K_EEPROM_TARGET_PWRSTART(_v) … #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) … #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) … #define AR5K_EEPROM_MISC2 … #define AR5K_EEPROM_EEP_FILE_VERSION(_v) … #define AR5K_EEPROM_EAR_FILE_VERSION(_v) … #define AR5K_EEPROM_MISC3 … #define AR5K_EEPROM_ART_BUILD_NUM(_v) … #define AR5K_EEPROM_EAR_FILE_ID(_v) … #define AR5K_EEPROM_MISC4 … #define AR5K_EEPROM_CAL_DATA_START(_v) … #define AR5K_EEPROM_MASK_R0(_v) … #define AR5K_EEPROM_MASK_R1(_v) … #define AR5K_EEPROM_MISC5 … #define AR5K_EEPROM_COMP_DIS(_v) … #define AR5K_EEPROM_AES_DIS(_v) … #define AR5K_EEPROM_FF_DIS(_v) … #define AR5K_EEPROM_BURST_DIS(_v) … #define AR5K_EEPROM_MAX_QCU(_v) … #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) … #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) … #define AR5K_EEPROM_MISC6 … #define AR5K_EEPROM_TX_CHAIN_DIS … #define AR5K_EEPROM_RX_CHAIN_DIS … #define AR5K_EEPROM_FCC_MID_EN … #define AR5K_EEPROM_JAP_U1EVEN_EN … #define AR5K_EEPROM_JAP_U2_EN … #define AR5K_EEPROM_JAP_MID_EN … #define AR5K_EEPROM_JAP_U1ODD_EN … #define AR5K_EEPROM_JAP_11A_NEW_EN … /* calibration settings */ #define AR5K_EEPROM_MODES_11A(_v) … #define AR5K_EEPROM_MODES_11B(_v) … #define AR5K_EEPROM_MODES_11G(_v) … #define AR5K_EEPROM_CTL(_v) … #define AR5K_EEPROM_GROUPS_START(_v) … #define AR5K_EEPROM_GROUP1_OFFSET … #define AR5K_EEPROM_GROUP2_OFFSET … #define AR5K_EEPROM_GROUP3_OFFSET … #define AR5K_EEPROM_GROUP4_OFFSET … #define AR5K_EEPROM_GROUP5_OFFSET … #define AR5K_EEPROM_GROUP6_OFFSET … #define AR5K_EEPROM_GROUP7_OFFSET … #define AR5K_EEPROM_GROUP8_OFFSET … #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) … #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) … #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) … /* [3.1 - 3.3] */ #define AR5K_EEPROM_OBDB0_2GHZ … #define AR5K_EEPROM_OBDB1_2GHZ … #define AR5K_EEPROM_PROTECT … #define AR5K_EEPROM_PROTECT_RD_0_31 … #define AR5K_EEPROM_PROTECT_WR_0_31 … #define AR5K_EEPROM_PROTECT_RD_32_63 … #define AR5K_EEPROM_PROTECT_WR_32_63 … #define AR5K_EEPROM_PROTECT_RD_64_127 … #define AR5K_EEPROM_PROTECT_WR_64_127 … #define AR5K_EEPROM_PROTECT_RD_128_191 … #define AR5K_EEPROM_PROTECT_WR_128_191 … #define AR5K_EEPROM_PROTECT_RD_192_207 … #define AR5K_EEPROM_PROTECT_WR_192_207 … #define AR5K_EEPROM_PROTECT_RD_208_223 … #define AR5K_EEPROM_PROTECT_WR_208_223 … #define AR5K_EEPROM_PROTECT_RD_224_239 … #define AR5K_EEPROM_PROTECT_WR_224_239 … #define AR5K_EEPROM_PROTECT_RD_240_255 … #define AR5K_EEPROM_PROTECT_WR_240_255 … /* Some EEPROM defines */ #define AR5K_EEPROM_EEP_SCALE … #define AR5K_EEPROM_EEP_DELTA … #define AR5K_EEPROM_N_MODES … #define AR5K_EEPROM_N_5GHZ_CHAN … #define AR5K_EEPROM_N_5GHZ_RATE_CHAN … #define AR5K_EEPROM_N_2GHZ_CHAN … #define AR5K_EEPROM_N_2GHZ_CHAN_2413 … #define AR5K_EEPROM_N_2GHZ_CHAN_MAX … #define AR5K_EEPROM_MAX_CHAN … #define AR5K_EEPROM_N_PWR_POINTS_5111 … #define AR5K_EEPROM_N_PCDAC … #define AR5K_EEPROM_N_PHASE_CAL … #define AR5K_EEPROM_N_TEST_FREQ … #define AR5K_EEPROM_N_EDGES … #define AR5K_EEPROM_N_INTERCEPTS … #define AR5K_EEPROM_FREQ_M(_v) … #define AR5K_EEPROM_PCDAC_M … #define AR5K_EEPROM_PCDAC_START … #define AR5K_EEPROM_PCDAC_STOP … #define AR5K_EEPROM_PCDAC_STEP … #define AR5K_EEPROM_NON_EDGE_M … #define AR5K_EEPROM_CHANNEL_POWER … #define AR5K_EEPROM_N_OBDB … #define AR5K_EEPROM_OBDB_DIS … #define AR5K_EEPROM_CHANNEL_DIS … #define AR5K_EEPROM_SCALE_OC_DELTA(_x) … #define AR5K_EEPROM_N_CTLS(_v) … #define AR5K_EEPROM_MAX_CTLS … #define AR5K_EEPROM_N_PD_CURVES … #define AR5K_EEPROM_N_XPD0_POINTS … #define AR5K_EEPROM_N_XPD3_POINTS … #define AR5K_EEPROM_N_PD_GAINS … #define AR5K_EEPROM_N_PD_POINTS … #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ … #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ … #define AR5K_EEPROM_POWER_M … #define AR5K_EEPROM_POWER_MIN … #define AR5K_EEPROM_POWER_MAX … #define AR5K_EEPROM_POWER_STEP … #define AR5K_EEPROM_POWER_TABLE_SIZE … #define AR5K_EEPROM_N_POWER_LOC_11B … #define AR5K_EEPROM_N_POWER_LOC_11G … #define AR5K_EEPROM_I_GAIN … #define AR5K_EEPROM_CCK_OFDM_DELTA … #define AR5K_EEPROM_N_IQ_CAL … /* 5GHz/2GHz */ enum ath5k_eeprom_freq_bands { … }; /* Spur chans per freq band */ #define AR5K_EEPROM_N_SPUR_CHANS … /* fbin value for chan 2464 x2 */ #define AR5K_EEPROM_5413_SPUR_CHAN_1 … /* fbin value for chan 2420 x2 */ #define AR5K_EEPROM_5413_SPUR_CHAN_2 … #define AR5K_EEPROM_SPUR_CHAN_MASK … #define AR5K_EEPROM_NO_SPUR … #define AR5K_SPUR_CHAN_WIDTH … #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz … #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz … #define AR5K_EEPROM_READ(_o, _v) … #define AR5K_EEPROM_READ_HDR(_o, _v) … \ enum ath5k_ant_table { … }; enum ath5k_ctl_mode { … }; /* Per channel calibration data, used for power table setup */ struct ath5k_chan_pcal_info_rf5111 { … }; struct ath5k_chan_pcal_info_rf5112 { … }; struct ath5k_chan_pcal_info_rf2413 { … }; enum ath5k_powertable_type { … }; struct ath5k_pdgain_info { … }; struct ath5k_chan_pcal_info { … }; /* Per rate calibration data for each mode, * used for rate power table setup. * Note: Values in 0.5dB units */ struct ath5k_rate_pcal_info { … }; /* Power edges for conformance test limits */ struct ath5k_edge_power { … }; /** * struct ath5k_eeprom_info - EEPROM calibration data * * @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING * flags * @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?] * @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for * OFDM and CCK packets * @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK * (11Mbps) rate in G mode. 0.1dB steps * @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution * * @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path * @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path * @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control * @ee_switch_settling: RX/TX Switch settling time * @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps * @ee_ant_control: Antenna Control Settings * @ee_ob: Bias current for Output stage of PA * B/G mode: Index [0] is used for AR2112/5112, otherwise [1] * A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz * @ee_db: Bias current for Output stage of PA. see @ee_ob * @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame * to when the external LNA is activated * @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame * to when the external PA switch is deactivated * @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when * external PA switch is activated * @ee_thr_62: Clear Channel Assessment (CCA) sensitivity * (IEEE802.11a section 17.3.10.5 ) * @ee_xlna_gain: Total gain of the LNA (information only) * @ee_xpd: Use external (1) or internal power detector * @ee_x_gain: Gain for external power detector output (differences in EEMAP * versions!) * @ee_i_gain: Initial gain value after reset * @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used * * @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals * @ee_noise_floor_thr: Noise floor threshold in 1dB steps * @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps * @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps * @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2) */ struct ath5k_eeprom_info { … };
Codebase Browser
linux