/* * Copyright (c) 2004-2007 Reyk Floeter <[email protected]> * Copyright (c) 2006-2007 Nick Kossifidis <[email protected]> * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef _ATH5K_H #define _ATH5K_H /* TODO: Clean up channel debugging (doesn't work anyway) and start * working on reg. control code using all available eeprom information * (rev. engineering needed) */ #define CHAN_DEBUG … #include <linux/io.h> #include <linux/interrupt.h> #include <linux/types.h> #include <linux/average.h> #include <linux/leds.h> #include <net/mac80211.h> #include <net/cfg80211.h> /* RX/TX descriptor hw structs * TODO: Driver part should only see sw structs */ #include "desc.h" /* EEPROM structs/offsets * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) * and clean up common bits, then introduce set/get functions in eeprom.c */ #include "eeprom.h" #include "debug.h" #include "../ath.h" #include "ani.h" /* PCI IDs */ #define PCI_DEVICE_ID_ATHEROS_AR5210 … #define PCI_DEVICE_ID_ATHEROS_AR5311 … #define PCI_DEVICE_ID_ATHEROS_AR5211 … #define PCI_DEVICE_ID_ATHEROS_AR5212 … #define PCI_DEVICE_ID_3COM_3CRDAG675 … #define PCI_DEVICE_ID_3COM_2_3CRPAG175 … #define PCI_DEVICE_ID_ATHEROS_AR5210_AP … #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM … #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT … #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT … #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT … #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA … #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY … #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B … #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 … #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 … #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 … #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 … #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 … #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 … #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 … #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 … #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 … #define PCI_DEVICE_ID_ATHEROS_AR2413 … #define PCI_DEVICE_ID_ATHEROS_AR5413 … #define PCI_DEVICE_ID_ATHEROS_AR5424 … #define PCI_DEVICE_ID_ATHEROS_AR5416 … #define PCI_DEVICE_ID_ATHEROS_AR5418 … /****************************\ GENERIC DRIVER DEFINITIONS \****************************/ #define ATH5K_PRINTF(fmt, ...) … void __printf(3, 4) _ath5k_printk(const struct ath5k_hw *ah, const char *level, const char *fmt, ...); #define ATH5K_PRINTK(_sc, _level, _fmt, ...) … #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) … #define ATH5K_INFO(_sc, _fmt, ...) … #define ATH5K_WARN(_sc, _fmt, ...) … #define ATH5K_ERR(_sc, _fmt, ...) … /* * AR5K REGISTER ACCESS */ /* Some macros to read/write fields */ /* First shift, then mask */ #define AR5K_REG_SM(_val, _flags) … /* First mask, then shift */ #define AR5K_REG_MS(_val, _flags) … /* Some registers can hold multiple values of interest. For this * reason when we want to write to these registers we must first * retrieve the values which we do not want to clear (lets call this * old_data) and then set the register with this and our new_value: * ( old_data | new_value) */ #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) … #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) … #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) … #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) … /* Access QCU registers per queue */ #define AR5K_REG_READ_Q(ah, _reg, _queue) … \ #define AR5K_REG_WRITE_Q(ah, _reg, _queue) … #define AR5K_Q_ENABLE_BITS(_reg, _queue) … #define AR5K_Q_DISABLE_BITS(_reg, _queue) … /* Used while writing initvals */ #define AR5K_REG_WAIT(_i) … /* * Some tunable values (these should be changeable by the user) * TODO: Make use of them and add more options OR use debug/configfs */ #define AR5K_TUNE_DMA_BEACON_RESP … #define AR5K_TUNE_SW_BEACON_RESP … #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF … #define AR5K_TUNE_MIN_TX_FIFO_THRES … #define AR5K_TUNE_MAX_TX_FIFO_THRES … #define AR5K_TUNE_REGISTER_TIMEOUT … /* Register for RSSI threshold has a mask of 0xff, so 255 seems to * be the max value. */ #define AR5K_TUNE_RSSI_THRES … /* This must be set when setting the RSSI threshold otherwise it can * prevent a reset. If AR5K_RSSI_THR is read after writing to it * the BMISS_THRES will be seen as 0, seems hardware doesn't keep * track of it. Max value depends on hardware. For AR5210 this is just 7. * For AR5211+ this seems to be up to 255. */ #define AR5K_TUNE_BMISS_THRES … #define AR5K_TUNE_REGISTER_DWELL_TIME … #define AR5K_TUNE_BEACON_INTERVAL … #define AR5K_TUNE_AIFS … #define AR5K_TUNE_AIFS_11B … #define AR5K_TUNE_AIFS_XR … #define AR5K_TUNE_CWMIN … #define AR5K_TUNE_CWMIN_11B … #define AR5K_TUNE_CWMIN_XR … #define AR5K_TUNE_CWMAX … #define AR5K_TUNE_CWMAX_11B … #define AR5K_TUNE_CWMAX_XR … #define AR5K_TUNE_NOISE_FLOOR … #define AR5K_TUNE_CCA_MAX_GOOD_VALUE … #define AR5K_TUNE_MAX_TXPOWER … #define AR5K_TUNE_DEFAULT_TXPOWER … #define AR5K_TUNE_TPC_TXPOWER … #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL … #define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT … #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI … #define ATH5K_TX_COMPLETE_POLL_INT … #define AR5K_INIT_CARR_SENSE_EN … /*Swap RX/TX Descriptor for big endian archs*/ #if defined(__BIG_ENDIAN) #define AR5K_INIT_CFG … #else #define AR5K_INIT_CFG … #endif /* Initial values */ #define AR5K_INIT_CYCRSSI_THR1 … /* Tx retry limit defaults from standard */ #define AR5K_INIT_RETRY_SHORT … #define AR5K_INIT_RETRY_LONG … /* Slot time */ #define AR5K_INIT_SLOT_TIME_TURBO … #define AR5K_INIT_SLOT_TIME_DEFAULT … #define AR5K_INIT_SLOT_TIME_HALF_RATE … #define AR5K_INIT_SLOT_TIME_QUARTER_RATE … #define AR5K_INIT_SLOT_TIME_B … #define AR5K_SLOT_TIME_MAX … /* SIFS */ #define AR5K_INIT_SIFS_TURBO … #define AR5K_INIT_SIFS_DEFAULT_BG … #define AR5K_INIT_SIFS_DEFAULT_A … #define AR5K_INIT_SIFS_HALF_RATE … #define AR5K_INIT_SIFS_QUARTER_RATE … /* Used to calculate tx time for non 5/10/40MHz * operation */ /* It's preamble time + signal time (16 + 4) */ #define AR5K_INIT_OFDM_PREAMPLE_TIME … /* Preamble time for 40MHz (turbo) operation (min ?) */ #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN … #define AR5K_INIT_OFDM_SYMBOL_TIME … #define AR5K_INIT_OFDM_PLCP_BITS … /* Rx latency for 5 and 10MHz operation (max ?) */ #define AR5K_INIT_RX_LAT_MAX … /* Tx latencies from initvals (5212 only but no problem * because we only tweak them on 5212) */ #define AR5K_INIT_TX_LAT_A … #define AR5K_INIT_TX_LAT_BG … /* Tx latency for 40MHz (turbo) operation (min ?) */ #define AR5K_INIT_TX_LAT_MIN … /* Default Tx/Rx latencies (same for 5211)*/ #define AR5K_INIT_TX_LATENCY_5210 … #define AR5K_INIT_RX_LATENCY_5210 … /* Tx frame to Tx data start delay */ #define AR5K_INIT_TXF2TXD_START_DEFAULT … #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ … #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ … /* We need to increase PHY switch and agc settling time * on turbo mode */ #define AR5K_SWITCH_SETTLING … #define AR5K_SWITCH_SETTLING_TURBO … #define AR5K_AGC_SETTLING … /* 38 on 5210 but shouldn't matter */ #define AR5K_AGC_SETTLING_TURBO … /*****************************\ * GENERIC CHIPSET DEFINITIONS * \*****************************/ /** * enum ath5k_version - MAC Chips * @AR5K_AR5210: AR5210 (Crete) * @AR5K_AR5211: AR5211 (Oahu/Maui) * @AR5K_AR5212: AR5212 (Venice) and newer */ enum ath5k_version { … }; /** * enum ath5k_radio - PHY Chips * @AR5K_RF5110: RF5110 (Fez) * @AR5K_RF5111: RF5111 (Sombrero) * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2) * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite) * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor) * @AR5K_RF2316: RF2315/2316 (Cobra SoC) * @AR5K_RF2317: RF2317 (Spider SoC) * @AR5K_RF2425: RF2425/2417 (Swan/Nalla) */ enum ath5k_radio { … }; /* * Common silicon revision/version values */ #define AR5K_SREV_UNKNOWN … #define AR5K_SREV_AR5210 … #define AR5K_SREV_AR5311 … #define AR5K_SREV_AR5311A … #define AR5K_SREV_AR5311B … #define AR5K_SREV_AR5211 … #define AR5K_SREV_AR5212 … #define AR5K_SREV_AR5312_R2 … #define AR5K_SREV_AR5212_V4 … #define AR5K_SREV_AR5213 … #define AR5K_SREV_AR5312_R7 … #define AR5K_SREV_AR2313_R8 … #define AR5K_SREV_AR5213A … #define AR5K_SREV_AR2413 … #define AR5K_SREV_AR2414 … #define AR5K_SREV_AR2315_R6 … #define AR5K_SREV_AR2315_R7 … #define AR5K_SREV_AR5424 … #define AR5K_SREV_AR2317_R1 … #define AR5K_SREV_AR2317_R2 … #define AR5K_SREV_AR5413 … #define AR5K_SREV_AR5414 … #define AR5K_SREV_AR2415 … #define AR5K_SREV_AR5416 … #define AR5K_SREV_AR5418 … #define AR5K_SREV_AR2425 … #define AR5K_SREV_AR2417 … #define AR5K_SREV_RAD_5110 … #define AR5K_SREV_RAD_5111 … #define AR5K_SREV_RAD_5111A … #define AR5K_SREV_RAD_2111 … #define AR5K_SREV_RAD_5112 … #define AR5K_SREV_RAD_5112A … #define AR5K_SREV_RAD_5112B … #define AR5K_SREV_RAD_2112 … #define AR5K_SREV_RAD_2112A … #define AR5K_SREV_RAD_2112B … #define AR5K_SREV_RAD_2413 … #define AR5K_SREV_RAD_5413 … #define AR5K_SREV_RAD_2316 … #define AR5K_SREV_RAD_2317 … #define AR5K_SREV_RAD_5424 … #define AR5K_SREV_RAD_2425 … #define AR5K_SREV_RAD_5133 … #define AR5K_SREV_PHY_5211 … #define AR5K_SREV_PHY_5212 … #define AR5K_SREV_PHY_5212A … #define AR5K_SREV_PHY_5212B … #define AR5K_SREV_PHY_2413 … #define AR5K_SREV_PHY_5413 … #define AR5K_SREV_PHY_2425 … /* TODO add support to mac80211 for vendor-specific rates and modes */ /** * DOC: Atheros XR * * Some of this information is based on Documentation from: * * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG * * Atheros' eXtended Range - range enhancing extension is a modulation scheme * that is supposed to double the link distance between an Atheros XR-enabled * client device with an Atheros XR-enabled access point. This is achieved * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB * above what the 802.11 specifications demand. In addition, new (proprietary) * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. * * Please note that can you either use XR or TURBO but you cannot use both, * they are exclusive. * * Also note that we do not plan to support XR mode at least for now. You can * get a mode similar to XR by using 5MHz bwmode. */ /** * DOC: Atheros SuperAG * * In addition to XR we have another modulation scheme called TURBO mode * that is supposed to provide a throughput transmission speed up to 40Mbit/s * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two * 54Mbit/s 802.11g channels. To use this feature both ends must support it. * There is also a distinction between "static" and "dynamic" turbo modes: * * - Static: is the dumb version: devices set to this mode stick to it until * the mode is turned off. * * - Dynamic: is the intelligent version, the network decides itself if it * is ok to use turbo. As soon as traffic is detected on adjacent channels * (which would get used in turbo mode), or when a non-turbo station joins * the network, turbo mode won't be used until the situation changes again. * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which * monitors the used radio band in order to decide whether turbo mode may * be used or not. * * This article claims Super G sticks to bonding of channels 5 and 6 for * USA: * * https://www.pcworld.com/article/id,113428-page,1/article.html * * The channel bonding seems to be driver specific though. * * In addition to TURBO modes we also have the following features for even * greater speed-up: * * - Bursting: allows multiple frames to be sent at once, rather than pausing * after each frame. Bursting is a standards-compliant feature that can be * used with any Access Point. * * - Fast frames: increases the amount of information that can be sent per * frame, also resulting in a reduction of transmission overhead. It is a * proprietary feature that needs to be supported by the Access Point. * * - Compression: data frames are compressed in real time using a Lempel Ziv * algorithm. This is done transparently. Once this feature is enabled, * compression and decompression takes place inside the chipset, without * putting additional load on the host CPU. * * As with XR we also don't plan to support SuperAG features for now. You can * get a mode similar to TURBO by using 40MHz bwmode. */ /** * enum ath5k_driver_mode - PHY operation mode * @AR5K_MODE_11A: 802.11a * @AR5K_MODE_11B: 802.11b * @AR5K_MODE_11G: 801.11g * @AR5K_MODE_MAX: Used for boundary checks * * Do not change the order here, we use these as * array indices and it also maps EEPROM structures. */ enum ath5k_driver_mode { … }; /** * enum ath5k_ant_mode - Antenna operation mode * @AR5K_ANTMODE_DEFAULT: Default antenna setup * @AR5K_ANTMODE_FIXED_A: Only antenna A is present * @AR5K_ANTMODE_FIXED_B: Only antenna B is present * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx- * @AR5K_ANTMODE_MAX: Used for boundary checks * * For more infos on antenna control check out phy.c */ enum ath5k_ant_mode { … }; /** * enum ath5k_bw_mode - Bandwidth operation mode * @AR5K_BWMODE_DEFAULT: 20MHz, default operation * @AR5K_BWMODE_5MHZ: Quarter rate * @AR5K_BWMODE_10MHZ: Half rate * @AR5K_BWMODE_40MHZ: Turbo */ enum ath5k_bw_mode { … }; /****************\ TX DEFINITIONS \****************/ /** * struct ath5k_tx_status - TX Status descriptor * @ts_seqnum: Sequence number * @ts_tstamp: Timestamp * @ts_status: Status code * @ts_final_idx: Final transmission series index * @ts_final_retry: Final retry count * @ts_rssi: RSSI for received ACK * @ts_shortretry: Short retry count * @ts_virtcol: Virtual collision count * @ts_antenna: Antenna used * * TX status descriptor gets filled by the hw * on each transmission attempt. */ struct ath5k_tx_status { … }; #define AR5K_TXSTAT_ALTRATE … #define AR5K_TXERR_XRETRY … #define AR5K_TXERR_FILT … #define AR5K_TXERR_FIFO … /** * enum ath5k_tx_queue - Queue types used to classify tx queues. * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue * @AR5K_TX_QUEUE_DATA: A normal data queue * @AR5K_TX_QUEUE_BEACON: The beacon queue * @AR5K_TX_QUEUE_CAB: The after-beacon queue * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue */ enum ath5k_tx_queue { … }; #define AR5K_NUM_TX_QUEUES … #define AR5K_NUM_TX_QUEUES_NOQCU … /** * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues * @AR5K_WME_AC_BK: Background traffic * @AR5K_WME_AC_BE: Best-effort (normal) traffic * @AR5K_WME_AC_VI: Video traffic * @AR5K_WME_AC_VO: Voice traffic * * These are the 4 Access Categories as defined in * WME spec. 0 is the lowest priority and 4 is the * highest. Normal data that hasn't been classified * goes to the Best Effort AC. */ enum ath5k_tx_queue_subtype { … }; /** * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available) * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available) * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery, * * Each number represents a hw queue. If hw does not support hw queues * (eg 5210) all data goes in one queue. */ enum ath5k_tx_queue_id { … }; /* * Flags to set hw queue's parameters... */ #define AR5K_TXQ_FLAG_TXOKINT_ENABLE … #define AR5K_TXQ_FLAG_TXERRINT_ENABLE … #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE … #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE … #define AR5K_TXQ_FLAG_TXURNINT_ENABLE … #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE … #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE … #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE … #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE … #define AR5K_TXQ_FLAG_BACKOFF_DISABLE … #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE … #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE … #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS … #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE … /** * struct ath5k_txq - Transmit queue state * @qnum: Hardware q number * @link: Link ptr in last TX desc * @q: Transmit queue (&struct list_head) * @lock: Lock on q and link * @setup: Is the queue configured * @txq_len:Number of queued buffers * @txq_max: Max allowed num of queued buffers * @txq_poll_mark: Used to check if queue got stuck * @txq_stuck: Queue stuck counter * * One of these exists for each hardware transmit queue. * Packets sent to us from above are assigned to queues based * on their priority. Not all devices support a complete set * of hardware transmit queues. For those devices the array * sc_ac2q will map multiple priorities to fewer hardware queues * (typically all to one hardware queue). */ struct ath5k_txq { … }; /** * struct ath5k_txq_info - A struct to hold TX queue's parameters * @tqi_type: One of enum ath5k_tx_queue * @tqi_subtype: One of enum ath5k_tx_queue_subtype * @tqi_flags: TX queue flags (see above) * @tqi_aifs: Arbitrated Inter-frame Space * @tqi_cw_min: Minimum Contention Window * @tqi_cw_max: Maximum Contention Window * @tqi_cbr_period: Constant bit rate period * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled */ struct ath5k_txq_info { … }; /** * enum ath5k_pkt_type - Transmit packet types * @AR5K_PKT_TYPE_NORMAL: Normal data * @AR5K_PKT_TYPE_ATIM: ATIM * @AR5K_PKT_TYPE_PSPOLL: PS-Poll * @AR5K_PKT_TYPE_BEACON: Beacon * @AR5K_PKT_TYPE_PROBE_RESP: Probe response * @AR5K_PKT_TYPE_PIFS: PIFS * Used on tx control descriptor */ enum ath5k_pkt_type { … }; /* * TX power and TPC settings */ #define AR5K_TXPOWER_OFDM(_r, _v) … #define AR5K_TXPOWER_CCK(_r, _v) … /****************\ RX DEFINITIONS \****************/ /** * struct ath5k_rx_status - RX Status descriptor * @rs_datalen: Data length * @rs_tstamp: Timestamp * @rs_status: Status code * @rs_phyerr: PHY error mask * @rs_rssi: RSSI in 0.5dbm units * @rs_keyix: Index to the key used for decrypting * @rs_rate: Rate used to decode the frame * @rs_antenna: Antenna used to receive the frame * @rs_more: Indicates this is a frame fragment (Fast frames) */ struct ath5k_rx_status { … }; #define AR5K_RXERR_CRC … #define AR5K_RXERR_PHY … #define AR5K_RXERR_FIFO … #define AR5K_RXERR_DECRYPT … #define AR5K_RXERR_MIC … #define AR5K_RXKEYIX_INVALID … #define AR5K_TXKEYIX_INVALID … /**************************\ BEACON TIMERS DEFINITIONS \**************************/ #define AR5K_BEACON_PERIOD … #define AR5K_BEACON_ENA … #define AR5K_BEACON_RESET_TSF … /* * TSF to TU conversion: * * TSF is a 64bit value in usec (microseconds). * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). */ #define TSF_TO_TU(_tsf) … /*******************************\ GAIN OPTIMIZATION DEFINITIONS \*******************************/ /** * enum ath5k_rfgain - RF Gain optimization engine state * @AR5K_RFGAIN_INACTIVE: Engine disabled * @AR5K_RFGAIN_ACTIVE: Probe active * @AR5K_RFGAIN_READ_REQUESTED: Probe requested * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change */ enum ath5k_rfgain { … }; /** * struct ath5k_gain - RF Gain optimization engine state data * @g_step_idx: Current step index * @g_current: Current gain * @g_target: Target gain * @g_low: Low gain boundary * @g_high: High gain boundary * @g_f_corr: Gain_F correction * @g_state: One of enum ath5k_rfgain */ struct ath5k_gain { … }; /********************\ COMMON DEFINITIONS \********************/ #define AR5K_SLOT_TIME_9 … #define AR5K_SLOT_TIME_20 … #define AR5K_SLOT_TIME_MAX … /** * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111 * @a2_flags: Channel flags (internal) * @a2_athchan: HW channel number (internal) * * This structure is used to map 2GHz channels to * 5GHz Atheros channels on 2111 frequency converter * that comes together with RF5111 * TODO: Clean up */ struct ath5k_athchan_2ghz { … }; /** * enum ath5k_dmasize - DMA size definitions (2^(n+2)) * @AR5K_DMASIZE_4B: 4Bytes * @AR5K_DMASIZE_8B: 8Bytes * @AR5K_DMASIZE_16B: 16Bytes * @AR5K_DMASIZE_32B: 32Bytes * @AR5K_DMASIZE_64B: 64Bytes (Default) * @AR5K_DMASIZE_128B: 128Bytes * @AR5K_DMASIZE_256B: 256Bytes * @AR5K_DMASIZE_512B: 512Bytes * * These are used to set DMA burst size on hw * * Note: Some platforms can't handle more than 4Bytes * be careful on embedded boards. */ enum ath5k_dmasize { … }; /******************\ RATE DEFINITIONS \******************/ /** * DOC: Rate codes * * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32. * * The rate code is used to get the RX rate or set the TX rate on the * hardware descriptors. It is also used for internal modulation control * and settings. * * This is the hardware rate map we are aware of (html unfriendly): * * Rate code Rate (Kbps) * --------- ----------- * 0x01 3000 (XR) * 0x02 1000 (XR) * 0x03 250 (XR) * 0x04 - 05 -Reserved- * 0x06 2000 (XR) * 0x07 500 (XR) * 0x08 48000 (OFDM) * 0x09 24000 (OFDM) * 0x0A 12000 (OFDM) * 0x0B 6000 (OFDM) * 0x0C 54000 (OFDM) * 0x0D 36000 (OFDM) * 0x0E 18000 (OFDM) * 0x0F 9000 (OFDM) * 0x10 - 17 -Reserved- * 0x18 11000L (CCK) * 0x19 5500L (CCK) * 0x1A 2000L (CCK) * 0x1B 1000L (CCK) * 0x1C 11000S (CCK) * 0x1D 5500S (CCK) * 0x1E 2000S (CCK) * 0x1F -Reserved- * * "S" indicates CCK rates with short preamble and "L" with long preamble. * * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the * lowest 4 bits, so they are the same as above with a 0xF mask. * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). * We handle this in ath5k_setup_bands(). */ #define AR5K_MAX_RATES … /* B */ #define ATH5K_RATE_CODE_1M … #define ATH5K_RATE_CODE_2M … #define ATH5K_RATE_CODE_5_5M … #define ATH5K_RATE_CODE_11M … /* A and G */ #define ATH5K_RATE_CODE_6M … #define ATH5K_RATE_CODE_9M … #define ATH5K_RATE_CODE_12M … #define ATH5K_RATE_CODE_18M … #define ATH5K_RATE_CODE_24M … #define ATH5K_RATE_CODE_36M … #define ATH5K_RATE_CODE_48M … #define ATH5K_RATE_CODE_54M … /* Adding this flag to rate_code on B rates * enables short preamble */ #define AR5K_SET_SHORT_PREAMBLE … /* * Crypto definitions */ #define AR5K_KEYCACHE_SIZE … extern bool ath5k_modparam_nohwcrypt; /***********************\ HW RELATED DEFINITIONS \***********************/ /* * Misc definitions */ #define AR5K_RSSI_EP_MULTIPLIER … #define AR5K_ASSERT_ENTRY(_e, _s) … /* * Hardware interrupt abstraction */ /** * enum ath5k_int - Hardware interrupt masks helpers * @AR5K_INT_RXOK: Frame successfully received * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor * @AR5K_INT_RXERR: Frame reception failed * @AR5K_INT_RXNOFRM: No frame received within a specified time period * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is * not always fatal, on some chips we can continue operation * without resetting the card, that's why %AR5K_INT_FATAL is not * common for all chips. * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts * * @AR5K_INT_TXOK: Frame transmission success * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor * @AR5K_INT_TXERR: Frame transmission failure * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The * Queue Control Unit (QCU) signals an EOL interrupt only if a * descriptor's LinkPtr is NULL. For more details, refer to: * "http://www.freepatentsonline.com/20030225739.html" * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should * increase the TX trigger threshold. * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts * * @AR5K_INT_MIB: Indicates the either Management Information Base counters or * one of the PHY error counters reached the maximum value and * should be read and cleared. * @AR5K_INT_SWI: Software triggered interrupt. * @AR5K_INT_RXPHY: RX PHY Error * @AR5K_INT_RXKCM: RX Key cache miss * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a * beacon that must be handled in software. The alternative is if * you have VEOL support, in that case you let the hardware deal * with things. * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing * beacons from the AP have associated with, we should probably * try to reassociate. When in IBSS mode this might mean we have * not received any beacons from any local stations. Note that * every station in an IBSS schedules to send beacons at the * Target Beacon Transmission Time (TBTT) with a random backoff. * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty. * @AR5K_INT_TIM: Beacon with local station's TIM bit set * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received * @AR5K_INT_DTIM_SYNC: DTIM sync lost * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to * our GPIO pins. * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got * nothing or an incomplete CAB frame sequence. * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired * @AR5K_INT_QCBRURN: A queue got triggered wile empty * @AR5K_INT_QTRIG: A queue got triggered * * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA * errors. Indicates we need to reset the card. * @AR5K_INT_GLOBAL: Used to clear and set the IER * @AR5K_INT_NOCARD: Signals the card has been removed * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same * bit value * * These are mapped to take advantage of some common bits * between the MACs, to be able to set intr properties * easier. Some of them are not used yet inside hw.c. Most map * to the respective hw interrupt value as they are common among different * MACs. */ enum ath5k_int { … }; /** * enum ath5k_calibration_mask - Mask which calibration is active at the moment * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT) * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q) * @AR5K_CALIBRATION_NF: Noise Floor calibration * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity */ enum ath5k_calibration_mask { … }; /** * enum ath5k_power_mode - Power management modes * @AR5K_PM_UNDEFINED: Undefined * @AR5K_PM_AUTO: Allow card to sleep if possible * @AR5K_PM_AWAKE: Force card to wake up * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS) * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration * * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO * are also known to have problems on some cards. This is not a big * problem though because we can have almost the same effect as * FULL_SLEEP by putting card on warm reset (it's almost powered down). */ enum ath5k_power_mode { … }; /* * These match net80211 definitions (not used in * mac80211). * TODO: Clean this up */ #define AR5K_LED_INIT … #define AR5K_LED_SCAN … #define AR5K_LED_AUTH … #define AR5K_LED_ASSOC … #define AR5K_LED_RUN … /* GPIO-controlled software LED */ #define AR5K_SOFTLED_PIN … #define AR5K_SOFTLED_ON … #define AR5K_SOFTLED_OFF … /* XXX: we *may* move cap_range stuff to struct wiphy */ struct ath5k_capabilities { … }; /* size of noise floor history (keep it a power of two) */ #define ATH5K_NF_CAL_HIST_MAX … struct ath5k_nfcal_hist { … }; #define ATH5K_LED_MAX_NAME_LEN … /* * State for LED triggers */ struct ath5k_led { … }; /* Rfkill */ struct ath5k_rfkill { … }; /* statistics */ struct ath5k_statistics { … }; /* * Misc defines */ #define AR5K_MAX_GPIO … #define AR5K_MAX_RF_BANKS … #if CHAN_DEBUG #define ATH_CHAN_MAX … #else #define ATH_CHAN_MAX … #endif #define ATH_RXBUF … #define ATH_TXBUF … #define ATH_BCBUF … #define ATH5K_TXQ_LEN_MAX … #define ATH5K_TXQ_LEN_LOW … DECLARE_EWMA(beacon_rssi, 10, 8) /* Driver state associated with an instance of a device */ struct ath5k_hw { … }; struct ath_bus_ops { … }; /* * Prototypes */ extern const struct ieee80211_ops ath5k_hw_ops; /* Initialization and detach functions */ int ath5k_hw_init(struct ath5k_hw *ah); void ath5k_hw_deinit(struct ath5k_hw *ah); int ath5k_sysfs_register(struct ath5k_hw *ah); void ath5k_sysfs_unregister(struct ath5k_hw *ah); /*Chip id helper functions */ int ath5k_hw_read_srev(struct ath5k_hw *ah); /* LED functions */ int ath5k_init_leds(struct ath5k_hw *ah); void ath5k_led_enable(struct ath5k_hw *ah); void ath5k_led_off(struct ath5k_hw *ah); void ath5k_unregister_leds(struct ath5k_hw *ah); /* Reset Functions */ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel); int ath5k_hw_on_hold(struct ath5k_hw *ah); int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool fast, bool skip_pcu); int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, bool is_set); /* Power management functions */ /* Clock rate related functions */ unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); void ath5k_hw_set_clockrate(struct ath5k_hw *ah); /* DMA Related Functions */ void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr); int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); /* Interrupt handling */ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); /* Init/Stop functions */ void ath5k_hw_dma_init(struct ath5k_hw *ah); int ath5k_hw_dma_stop(struct ath5k_hw *ah); /* EEPROM access functions */ int ath5k_eeprom_init(struct ath5k_hw *ah); void ath5k_eeprom_detach(struct ath5k_hw *ah); int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel); /* Protocol Control Unit Functions */ /* Helpers */ int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band, int len, struct ieee80211_rate *rate, bool shortpre); unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); /* RX filter control*/ int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); void ath5k_hw_set_bssid(struct ath5k_hw *ah); void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); /* Receive (DRU) start/stop functions */ void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); /* Beacon control functions */ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); void ath5k_hw_reset_tsf(struct ath5k_hw *ah); void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval); bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); /* Init function */ void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode); /* Queue Control Unit, DFS Control Unit Functions */ int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info); int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, const struct ath5k_txq_info *queue_info); int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info); void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah, unsigned int queue); u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); /* Init function */ int ath5k_hw_init_queues(struct ath5k_hw *ah); /* Hardware Descriptor Functions */ int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, u32 size, unsigned int flags); int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); /* GPIO Functions */ void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); /* RFkill Functions */ void ath5k_rfkill_hw_start(struct ath5k_hw *ah); void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); /* Misc functions TODO: Cleanup */ int ath5k_hw_set_capabilities(struct ath5k_hw *ah); int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); /* Initial register settings functions */ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); /* PHY functions */ /* Misc PHY functions */ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band); int ath5k_hw_phy_disable(struct ath5k_hw *ah); /* Gain_F optimization */ enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); /* PHY/RF channel functions */ bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel); /* PHY calibration */ void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel); void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); /* Spur mitigation */ bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, struct ieee80211_channel *channel); /* Antenna control */ void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); /* TX power setup */ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); /* Init function */ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 mode, bool fast); /* * Functions used internally */ static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) { … } static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) { … } #ifdef CONFIG_ATH5K_AHB #define AR5K_AR2315_PCI_BASE … static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) { /* On AR2315 and AR2317 the PCI clock domain registers * are outside of the WMAC register space */ if (unlikely((reg >= 0x4000) && (reg < 0x5000) && (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) return AR5K_AR2315_PCI_BASE + reg; return ah->iobase + reg; } static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) { return ioread32(ath5k_ahb_reg(ah, reg)); } static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) { iowrite32(val, ath5k_ahb_reg(ah, reg)); } #else static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) { … } static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) { … } #endif static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) { … } static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) { … } static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) { … } static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) { … } #endif
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