/* * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]> * Copyright (c) 2004-2008 Reyk Floeter <[email protected]> * Copyright (c) 2007-2008 Michael Taylor <[email protected]> * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ /* * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k * maintained by Reyk Floeter * * I tried to document those registers by looking at ar5k code, some * 802.11 (802.11e mostly) papers and by reading various public available * Atheros presentations and papers like these: * * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf * * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf * * This file also contains register values found on a memory dump of * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal * released by Atheros and on various debug messages found on the net. */ #include "../reg.h" /*====MAC DMA REGISTERS====*/ /* * AR5210-Specific TXDP registers * 5210 has only 2 transmit queues so no DCU/QCU, just * 2 transmit descriptor pointers... */ #define AR5K_NOQCU_TXDP0 … #define AR5K_NOQCU_TXDP1 … /* * Mac Control Register */ #define AR5K_CR … #define AR5K_CR_TXE0 … #define AR5K_CR_TXE1 … #define AR5K_CR_RXE … #define AR5K_CR_TXD0 … #define AR5K_CR_TXD1 … #define AR5K_CR_RXD … #define AR5K_CR_SWI … /* * RX Descriptor Pointer register */ #define AR5K_RXDP … /* * Configuration and status register */ #define AR5K_CFG … #define AR5K_CFG_SWTD … #define AR5K_CFG_SWTB … #define AR5K_CFG_SWRD … #define AR5K_CFG_SWRB … #define AR5K_CFG_SWRG … #define AR5K_CFG_IBSS … #define AR5K_CFG_PHY_OK … #define AR5K_CFG_EEBS … #define AR5K_CFG_CLKGD … #define AR5K_CFG_TXCNT … #define AR5K_CFG_TXCNT_S … #define AR5K_CFG_TXFSTAT … #define AR5K_CFG_TXFSTRT … #define AR5K_CFG_PCI_THRES … #define AR5K_CFG_PCI_THRES_S … /* * Interrupt enable register */ #define AR5K_IER … #define AR5K_IER_DISABLE … #define AR5K_IER_ENABLE … /* * 0x0028 is Beacon Control Register on 5210 * and first RTS duration register on 5211 */ /* * Beacon control register [5210] */ #define AR5K_BCR … #define AR5K_BCR_AP … #define AR5K_BCR_ADHOC … #define AR5K_BCR_BDMAE … #define AR5K_BCR_TQ1FV … #define AR5K_BCR_TQ1V … #define AR5K_BCR_BCGET … /* * First RTS duration register [5211] */ #define AR5K_RTSD0 … #define AR5K_RTSD0_6 … #define AR5K_RTSD0_6_S … #define AR5K_RTSD0_9 … #define AR5K_RTSD0_9_S … #define AR5K_RTSD0_12 … #define AR5K_RTSD0_12_S … #define AR5K_RTSD0_18 … #define AR5K_RTSD0_18_S … /* * 0x002c is Beacon Status Register on 5210 * and second RTS duration register on 5211 */ /* * Beacon status register [5210] * * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. */ #define AR5K_BSR … #define AR5K_BSR_BDLYSW … #define AR5K_BSR_BDLYDMA … #define AR5K_BSR_TXQ1F … #define AR5K_BSR_ATIMDLY … #define AR5K_BSR_SNPADHOC … #define AR5K_BSR_SNPBDMAE … #define AR5K_BSR_SNPTQ1FV … #define AR5K_BSR_SNPTQ1V … #define AR5K_BSR_SNAPSHOTSVALID … #define AR5K_BSR_SWBA_CNT … /* * Second RTS duration register [5211] */ #define AR5K_RTSD1 … #define AR5K_RTSD1_24 … #define AR5K_RTSD1_24_S … #define AR5K_RTSD1_36 … #define AR5K_RTSD1_36_S … #define AR5K_RTSD1_48 … #define AR5K_RTSD1_48_S … #define AR5K_RTSD1_54 … #define AR5K_RTSD1_54_S … /* * Transmit configuration register */ #define AR5K_TXCFG … #define AR5K_TXCFG_SDMAMR … #define AR5K_TXCFG_SDMAMR_S … #define AR5K_TXCFG_B_MODE … #define AR5K_TXCFG_TXFSTP … #define AR5K_TXCFG_TXFULL … #define AR5K_TXCFG_TXFULL_S … #define AR5K_TXCFG_TXFULL_0B … #define AR5K_TXCFG_TXFULL_64B … #define AR5K_TXCFG_TXFULL_128B … #define AR5K_TXCFG_TXFULL_192B … #define AR5K_TXCFG_TXFULL_256B … #define AR5K_TXCFG_TXCONT_EN … #define AR5K_TXCFG_DMASIZE … #define AR5K_TXCFG_JUMBO_DESC_EN … #define AR5K_TXCFG_ADHOC_BCN_ATIM … #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS … #define AR5K_TXCFG_RTSRND … #define AR5K_TXCFG_FRMPAD_DIS … #define AR5K_TXCFG_RDY_CBR_DIS … #define AR5K_TXCFG_JUMBO_FRM_MODE … #define AR5K_TXCFG_DCU_DBL_BUF_DIS … #define AR5K_TXCFG_DCU_CACHING_DIS … /* * Receive configuration register */ #define AR5K_RXCFG … #define AR5K_RXCFG_SDMAMW … #define AR5K_RXCFG_SDMAMW_S … #define AR5K_RXCFG_ZLFDMA … #define AR5K_RXCFG_DEF_ANTENNA … #define AR5K_RXCFG_JUMBO_RXE … #define AR5K_RXCFG_JUMBO_WRAP … #define AR5K_RXCFG_SLE_ENTRY … /* * Receive jumbo descriptor last address register * Only found in 5211 (?) */ #define AR5K_RXJLA … /* * MIB control register */ #define AR5K_MIBC … #define AR5K_MIBC_COW … #define AR5K_MIBC_FMC … #define AR5K_MIBC_CMC … #define AR5K_MIBC_MCS … /* * Timeout prescale register */ #define AR5K_TOPS … #define AR5K_TOPS_M … /* * Receive timeout register (no frame received) */ #define AR5K_RXNOFRM … #define AR5K_RXNOFRM_M … /* * Transmit timeout register (no frame sent) */ #define AR5K_TXNOFRM … #define AR5K_TXNOFRM_M … #define AR5K_TXNOFRM_QCU … #define AR5K_TXNOFRM_QCU_S … /* * Receive frame gap timeout register */ #define AR5K_RPGTO … #define AR5K_RPGTO_M … /* * Receive frame count limit register */ #define AR5K_RFCNT … #define AR5K_RFCNT_M … #define AR5K_RFCNT_RFCL … /* * Misc settings register * (reserved0-3) */ #define AR5K_MISC … #define AR5K_MISC_DMA_OBS_M … #define AR5K_MISC_DMA_OBS_S … #define AR5K_MISC_MISC_OBS_M … #define AR5K_MISC_MISC_OBS_S … #define AR5K_MISC_MAC_OBS_LSB_M … #define AR5K_MISC_MAC_OBS_LSB_S … #define AR5K_MISC_MAC_OBS_MSB_M … #define AR5K_MISC_MAC_OBS_MSB_S … #define AR5K_MISC_LED_DECAY … #define AR5K_MISC_LED_BLINK … /* * QCU/DCU clock gating register (5311) * (reserved4-5) */ #define AR5K_QCUDCU_CLKGT … #define AR5K_QCUDCU_CLKGT_QCU … #define AR5K_QCUDCU_CLKGT_DCU … /* * Interrupt Status Registers * * For 5210 there is only one status register but for * 5211/5212 we have one primary and 4 secondary registers. * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. * Most of these bits are common for all chipsets. * * NOTE: On 5211+ TXOK, TXDESC, TXERR, TXEOL and TXURN contain * the logical OR from per-queue interrupt bits found on SISR registers * (see below). */ #define AR5K_ISR … #define AR5K_PISR … #define AR5K_ISR_RXOK … #define AR5K_ISR_RXDESC … #define AR5K_ISR_RXERR … #define AR5K_ISR_RXNOFRM … #define AR5K_ISR_RXEOL … #define AR5K_ISR_RXORN … #define AR5K_ISR_TXOK … #define AR5K_ISR_TXDESC … #define AR5K_ISR_TXERR … #define AR5K_ISR_TXNOFRM … #define AR5K_ISR_TXEOL … #define AR5K_ISR_TXURN … #define AR5K_ISR_MIB … #define AR5K_ISR_SWI … #define AR5K_ISR_RXPHY … #define AR5K_ISR_RXKCM … #define AR5K_ISR_SWBA … #define AR5K_ISR_BRSSI … #define AR5K_ISR_BMISS … #define AR5K_ISR_HIUERR … #define AR5K_ISR_BNR … #define AR5K_ISR_MCABT … #define AR5K_ISR_RXCHIRP … #define AR5K_ISR_SSERR … #define AR5K_ISR_DPERR … #define AR5K_ISR_RXDOPPLER … #define AR5K_ISR_TIM … #define AR5K_ISR_BCNMISC … #define AR5K_ISR_GPIO … #define AR5K_ISR_QCBRORN … #define AR5K_ISR_QCBRURN … #define AR5K_ISR_QTRIG … #define AR5K_ISR_BITS_FROM_SISRS … /* * Secondary status registers [5211+] (0 - 4) * * These give the status for each QCU, only QCUs 0-9 are * represented. */ #define AR5K_SISR0 … #define AR5K_SISR0_QCU_TXOK … #define AR5K_SISR0_QCU_TXOK_S … #define AR5K_SISR0_QCU_TXDESC … #define AR5K_SISR0_QCU_TXDESC_S … #define AR5K_SISR1 … #define AR5K_SISR1_QCU_TXERR … #define AR5K_SISR1_QCU_TXERR_S … #define AR5K_SISR1_QCU_TXEOL … #define AR5K_SISR1_QCU_TXEOL_S … #define AR5K_SISR2 … #define AR5K_SISR2_QCU_TXURN … #define AR5K_SISR2_QCU_TXURN_S … #define AR5K_SISR2_MCABT … #define AR5K_SISR2_SSERR … #define AR5K_SISR2_DPERR … #define AR5K_SISR2_TIM … #define AR5K_SISR2_CAB_END … #define AR5K_SISR2_DTIM_SYNC … #define AR5K_SISR2_BCN_TIMEOUT … #define AR5K_SISR2_CAB_TIMEOUT … #define AR5K_SISR2_DTIM … #define AR5K_SISR2_TSFOOR … #define AR5K_SISR3 … #define AR5K_SISR3_QCBRORN … #define AR5K_SISR3_QCBRORN_S … #define AR5K_SISR3_QCBRURN … #define AR5K_SISR3_QCBRURN_S … #define AR5K_SISR4 … #define AR5K_SISR4_QTRIG … #define AR5K_SISR4_QTRIG_S … /* * Shadow read-and-clear interrupt status registers [5211+] */ #define AR5K_RAC_PISR … #define AR5K_RAC_SISR0 … #define AR5K_RAC_SISR1 … #define AR5K_RAC_SISR2 … #define AR5K_RAC_SISR3 … #define AR5K_RAC_SISR4 … /* * Interrupt Mask Registers * * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. */ #define AR5K_IMR … #define AR5K_PIMR … #define AR5K_IMR_RXOK … #define AR5K_IMR_RXDESC … #define AR5K_IMR_RXERR … #define AR5K_IMR_RXNOFRM … #define AR5K_IMR_RXEOL … #define AR5K_IMR_RXORN … #define AR5K_IMR_TXOK … #define AR5K_IMR_TXDESC … #define AR5K_IMR_TXERR … #define AR5K_IMR_TXNOFRM … #define AR5K_IMR_TXEOL … #define AR5K_IMR_TXURN … #define AR5K_IMR_MIB … #define AR5K_IMR_SWI … #define AR5K_IMR_RXPHY … #define AR5K_IMR_RXKCM … #define AR5K_IMR_SWBA … #define AR5K_IMR_BRSSI … #define AR5K_IMR_BMISS … #define AR5K_IMR_HIUERR … #define AR5K_IMR_BNR … #define AR5K_IMR_MCABT … #define AR5K_IMR_RXCHIRP … #define AR5K_IMR_SSERR … #define AR5K_IMR_DPERR … #define AR5K_IMR_RXDOPPLER … #define AR5K_IMR_TIM … #define AR5K_IMR_BCNMISC … #define AR5K_IMR_GPIO … #define AR5K_IMR_QCBRORN … #define AR5K_IMR_QCBRURN … #define AR5K_IMR_QTRIG … /* * Secondary interrupt mask registers [5211+] (0 - 4) */ #define AR5K_SIMR0 … #define AR5K_SIMR0_QCU_TXOK … #define AR5K_SIMR0_QCU_TXOK_S … #define AR5K_SIMR0_QCU_TXDESC … #define AR5K_SIMR0_QCU_TXDESC_S … #define AR5K_SIMR1 … #define AR5K_SIMR1_QCU_TXERR … #define AR5K_SIMR1_QCU_TXERR_S … #define AR5K_SIMR1_QCU_TXEOL … #define AR5K_SIMR1_QCU_TXEOL_S … #define AR5K_SIMR2 … #define AR5K_SIMR2_QCU_TXURN … #define AR5K_SIMR2_QCU_TXURN_S … #define AR5K_SIMR2_MCABT … #define AR5K_SIMR2_SSERR … #define AR5K_SIMR2_DPERR … #define AR5K_SIMR2_TIM … #define AR5K_SIMR2_CAB_END … #define AR5K_SIMR2_DTIM_SYNC … #define AR5K_SIMR2_BCN_TIMEOUT … #define AR5K_SIMR2_CAB_TIMEOUT … #define AR5K_SIMR2_DTIM … #define AR5K_SIMR2_TSFOOR … #define AR5K_SIMR3 … #define AR5K_SIMR3_QCBRORN … #define AR5K_SIMR3_QCBRORN_S … #define AR5K_SIMR3_QCBRURN … #define AR5K_SIMR3_QCBRURN_S … #define AR5K_SIMR4 … #define AR5K_SIMR4_QTRIG … #define AR5K_SIMR4_QTRIG_S … /* * DMA Debug registers 0-7 * 0xe0 - 0xfc */ /* * Decompression mask registers [5212+] */ #define AR5K_DCM_ADDR … #define AR5K_DCM_DATA … /* * Wake On Wireless pattern control register [5212+] */ #define AR5K_WOW_PCFG … #define AR5K_WOW_PCFG_PAT_MATCH_EN … #define AR5K_WOW_PCFG_LONG_FRAME_POL … #define AR5K_WOW_PCFG_WOBMISS … #define AR5K_WOW_PCFG_PAT_0_EN … #define AR5K_WOW_PCFG_PAT_1_EN … #define AR5K_WOW_PCFG_PAT_2_EN … #define AR5K_WOW_PCFG_PAT_3_EN … #define AR5K_WOW_PCFG_PAT_4_EN … #define AR5K_WOW_PCFG_PAT_5_EN … /* * Wake On Wireless pattern index register (?) [5212+] */ #define AR5K_WOW_PAT_IDX … /* * Wake On Wireless pattern data register [5212+] */ #define AR5K_WOW_PAT_DATA … #define AR5K_WOW_PAT_DATA_0_3_V … #define AR5K_WOW_PAT_DATA_1_4_V … #define AR5K_WOW_PAT_DATA_2_5_V … #define AR5K_WOW_PAT_DATA_0_3_M … #define AR5K_WOW_PAT_DATA_1_4_M … #define AR5K_WOW_PAT_DATA_2_5_M … /* * Decompression configuration registers [5212+] */ #define AR5K_DCCFG … #define AR5K_DCCFG_GLOBAL_EN … #define AR5K_DCCFG_BYPASS_EN … #define AR5K_DCCFG_BCAST_EN … #define AR5K_DCCFG_MCAST_EN … /* * Compression configuration registers [5212+] */ #define AR5K_CCFG … #define AR5K_CCFG_WINDOW_SIZE … #define AR5K_CCFG_CPC_EN … #define AR5K_CCFG_CCU … #define AR5K_CCFG_CCU_CUP_EN … #define AR5K_CCFG_CCU_CREDIT … #define AR5K_CCFG_CCU_CD_THRES … #define AR5K_CCFG_CCU_CUP_LCNT … #define AR5K_CCFG_CCU_INIT … /* * Compression performance counter registers [5212+] */ #define AR5K_CPC0 … #define AR5K_CPC1 … #define AR5K_CPC2 … #define AR5K_CPC3 … #define AR5K_CPCOVF … /* * Queue control unit (QCU) registers [5211+] * * Card has 12 TX Queues but i see that only 0-9 are used (?) * both in binary HAL (see ah.h) and ar5k. Each queue has it's own * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) * configuration register (0x08c0 - 0x08ec), a ready time configuration * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some * global registers, QCU transmit enable/disable and "one shot arm (?)" * set/clear, which contain status for all queues (we shift by 1 for each * queue). To access these registers easily we define some macros here * that are used inside HAL. For more infos check out *_tx_queue functs. */ /* * Generic QCU Register access macros */ #define AR5K_QUEUE_REG(_r, _q) … #define AR5K_QCU_GLOBAL_READ(_r, _q) … #define AR5K_QCU_GLOBAL_WRITE(_r, _q) … /* * QCU Transmit descriptor pointer registers */ #define AR5K_QCU_TXDP_BASE … #define AR5K_QUEUE_TXDP(_q) … /* * QCU Transmit enable register */ #define AR5K_QCU_TXE … #define AR5K_ENABLE_QUEUE(_q) … #define AR5K_QUEUE_ENABLED(_q) … /* * QCU Transmit disable register */ #define AR5K_QCU_TXD … #define AR5K_DISABLE_QUEUE(_q) … #define AR5K_QUEUE_DISABLED(_q) … /* * QCU Constant Bit Rate configuration registers */ #define AR5K_QCU_CBRCFG_BASE … #define AR5K_QCU_CBRCFG_INTVAL … #define AR5K_QCU_CBRCFG_INTVAL_S … #define AR5K_QCU_CBRCFG_ORN_THRES … #define AR5K_QCU_CBRCFG_ORN_THRES_S … #define AR5K_QUEUE_CBRCFG(_q) … /* * QCU Ready time configuration registers */ #define AR5K_QCU_RDYTIMECFG_BASE … #define AR5K_QCU_RDYTIMECFG_INTVAL … #define AR5K_QCU_RDYTIMECFG_INTVAL_S … #define AR5K_QCU_RDYTIMECFG_ENABLE … #define AR5K_QUEUE_RDYTIMECFG(_q) … /* * QCU one shot arm set registers */ #define AR5K_QCU_ONESHOTARM_SET … #define AR5K_QCU_ONESHOTARM_SET_M … /* * QCU one shot arm clear registers */ #define AR5K_QCU_ONESHOTARM_CLEAR … #define AR5K_QCU_ONESHOTARM_CLEAR_M … /* * QCU misc registers */ #define AR5K_QCU_MISC_BASE … #define AR5K_QCU_MISC_FRSHED_M … #define AR5K_QCU_MISC_FRSHED_ASAP … #define AR5K_QCU_MISC_FRSHED_CBR … #define AR5K_QCU_MISC_FRSHED_DBA_GT … #define AR5K_QCU_MISC_FRSHED_TIM_GT … #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT … #define AR5K_QCU_MISC_ONESHOT_ENABLE … #define AR5K_QCU_MISC_CBREXP_DIS … #define AR5K_QCU_MISC_CBREXP_BCN_DIS … #define AR5K_QCU_MISC_BCN_ENABLE … #define AR5K_QCU_MISC_CBR_THRES_ENABLE … #define AR5K_QCU_MISC_RDY_VEOL_POLICY … #define AR5K_QCU_MISC_CBR_RESET_CNT … #define AR5K_QCU_MISC_DCU_EARLY … #define AR5K_QCU_MISC_DCU_CMP_EN … #define AR5K_QUEUE_MISC(_q) … /* * QCU status registers */ #define AR5K_QCU_STS_BASE … #define AR5K_QCU_STS_FRMPENDCNT … #define AR5K_QCU_STS_CBREXPCNT … #define AR5K_QUEUE_STATUS(_q) … /* * QCU ready time shutdown register */ #define AR5K_QCU_RDYTIMESHDN … #define AR5K_QCU_RDYTIMESHDN_M … /* * QCU compression buffer base registers [5212+] */ #define AR5K_QCU_CBB_SELECT … #define AR5K_QCU_CBB_ADDR … #define AR5K_QCU_CBB_ADDR_S … /* * QCU compression buffer configuration register [5212+] * (buffer size) */ #define AR5K_QCU_CBCFG … /* * Distributed Coordination Function (DCF) control unit (DCU) * registers [5211+] * * These registers control the various characteristics of each queue * for 802.11e (WME) compatibility so they go together with * QCU registers in pairs. For each queue we have a QCU mask register, * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), * a retry limit register (0x1080 - 0x10ac), a channel time register * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and * a sequence number register (0x1140 - 0x116c). It seems that "global" * registers here affect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). * We use the same macros here for easier register access. * */ /* * DCU QCU mask registers */ #define AR5K_DCU_QCUMASK_BASE … #define AR5K_DCU_QCUMASK_M … #define AR5K_QUEUE_QCUMASK(_q) … /* * DCU local Inter Frame Space settings register */ #define AR5K_DCU_LCL_IFS_BASE … #define AR5K_DCU_LCL_IFS_CW_MIN … #define AR5K_DCU_LCL_IFS_CW_MIN_S … #define AR5K_DCU_LCL_IFS_CW_MAX … #define AR5K_DCU_LCL_IFS_CW_MAX_S … #define AR5K_DCU_LCL_IFS_AIFS … #define AR5K_DCU_LCL_IFS_AIFS_S … #define AR5K_DCU_LCL_IFS_AIFS_MAX … #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) … /* * DCU retry limit registers * all these fields don't allow zero values */ #define AR5K_DCU_RETRY_LMT_BASE … #define AR5K_DCU_RETRY_LMT_RTS … #define AR5K_DCU_RETRY_LMT_RTS_S … #define AR5K_DCU_RETRY_LMT_STA_RTS … #define AR5K_DCU_RETRY_LMT_STA_RTS_S … #define AR5K_DCU_RETRY_LMT_STA_DATA … #define AR5K_DCU_RETRY_LMT_STA_DATA_S … #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) … /* * DCU channel time registers */ #define AR5K_DCU_CHAN_TIME_BASE … #define AR5K_DCU_CHAN_TIME_DUR … #define AR5K_DCU_CHAN_TIME_DUR_S … #define AR5K_DCU_CHAN_TIME_ENABLE … #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) … /* * DCU misc registers [5211+] * * Note: Arbiter lockout control controls the * behaviour on low priority queues when we have multiple queues * with pending frames. Intra-frame lockout means we wait until * the queue's current frame transmits (with post frame backoff and bursting) * before we transmit anything else and global lockout means we * wait for the whole queue to finish before higher priority queues * can transmit (this is used on beacon and CAB queues). * No lockout means there is no special handling. */ #define AR5K_DCU_MISC_BASE … #define AR5K_DCU_MISC_BACKOFF … #define AR5K_DCU_MISC_ETS_RTS_POL … #define AR5K_DCU_MISC_ETS_CW_POL … #define AR5K_DCU_MISC_FRAG_WAIT … #define AR5K_DCU_MISC_BACKOFF_FRAG … #define AR5K_DCU_MISC_HCFPOLL_ENABLE … #define AR5K_DCU_MISC_BACKOFF_PERSIST … #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE … #define AR5K_DCU_MISC_VIRTCOL … #define AR5K_DCU_MISC_VIRTCOL_NORMAL … #define AR5K_DCU_MISC_VIRTCOL_IGNORE … #define AR5K_DCU_MISC_BCN_ENABLE … #define AR5K_DCU_MISC_ARBLOCK_CTL … #define AR5K_DCU_MISC_ARBLOCK_CTL_S … #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE … #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM … #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL … #define AR5K_DCU_MISC_ARBLOCK_IGNORE … #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS … #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS … #define AR5K_DCU_MISC_VIRT_COLL_POLICY … #define AR5K_DCU_MISC_BLOWN_IFS_POLICY … #define AR5K_DCU_MISC_SEQNUM_CTL … #define AR5K_QUEUE_DFS_MISC(_q) … /* * DCU frame sequence number registers */ #define AR5K_DCU_SEQNUM_BASE … #define AR5K_DCU_SEQNUM_M … #define AR5K_QUEUE_DCU_SEQNUM(_q) … /* * DCU global IFS SIFS register */ #define AR5K_DCU_GBL_IFS_SIFS … #define AR5K_DCU_GBL_IFS_SIFS_M … /* * DCU global IFS slot interval register */ #define AR5K_DCU_GBL_IFS_SLOT … #define AR5K_DCU_GBL_IFS_SLOT_M … /* * DCU global IFS EIFS register */ #define AR5K_DCU_GBL_IFS_EIFS … #define AR5K_DCU_GBL_IFS_EIFS_M … /* * DCU global IFS misc register * * LFSR stands for Linear Feedback Shift Register * and it's used for generating pseudo-random * number sequences. * * (If i understand correctly, random numbers are * used for idle sensing -multiplied with cwmin/max etc-) */ #define AR5K_DCU_GBL_IFS_MISC … #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE … #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE … #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC … #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S … #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR … #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S … #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY … #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST … #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST … #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS … /* * DCU frame prefetch control register */ #define AR5K_DCU_FP … #define AR5K_DCU_FP_NOBURST_DCU_EN … #define AR5K_DCU_FP_NOBURST_EN … #define AR5K_DCU_FP_BURST_DCU_EN … /* * DCU transmit pause control/status register */ #define AR5K_DCU_TXP … #define AR5K_DCU_TXP_M … #define AR5K_DCU_TXP_STATUS … /* * DCU transmit filter table 0 (32 entries) * each entry contains a 32bit slice of the * 128bit tx filter for each DCU (4 slices per DCU) */ #define AR5K_DCU_TX_FILTER_0_BASE … #define AR5K_DCU_TX_FILTER_0(_n) … /* * DCU transmit filter table 1 (16 entries) */ #define AR5K_DCU_TX_FILTER_1_BASE … #define AR5K_DCU_TX_FILTER_1(_n) … /* * DCU clear transmit filter register */ #define AR5K_DCU_TX_FILTER_CLR … /* * DCU set transmit filter register */ #define AR5K_DCU_TX_FILTER_SET … /* * Reset control register */ #define AR5K_RESET_CTL … #define AR5K_RESET_CTL_PCU … #define AR5K_RESET_CTL_DMA … #define AR5K_RESET_CTL_BASEBAND … #define AR5K_RESET_CTL_MAC … #define AR5K_RESET_CTL_PHY … #define AR5K_RESET_CTL_PCI … /* * Sleep control register */ #define AR5K_SLEEP_CTL … #define AR5K_SLEEP_CTL_SLDUR … #define AR5K_SLEEP_CTL_SLDUR_S … #define AR5K_SLEEP_CTL_SLE … #define AR5K_SLEEP_CTL_SLE_S … #define AR5K_SLEEP_CTL_SLE_WAKE … #define AR5K_SLEEP_CTL_SLE_SLP … #define AR5K_SLEEP_CTL_SLE_ALLOW … #define AR5K_SLEEP_CTL_SLE_UNITS … #define AR5K_SLEEP_CTL_DUR_TIM_POL … #define AR5K_SLEEP_CTL_DUR_WRITE_POL … #define AR5K_SLEEP_CTL_SLE_POL … /* * Interrupt pending register */ #define AR5K_INTPEND … #define AR5K_INTPEND_M … /* * Sleep force register */ #define AR5K_SFR … #define AR5K_SFR_EN … /* * PCI configuration register * TODO: Fix LED stuff */ #define AR5K_PCICFG … #define AR5K_PCICFG_EEAE … #define AR5K_PCICFG_SLEEP_CLOCK_EN … #define AR5K_PCICFG_CLKRUNEN … #define AR5K_PCICFG_EESIZE … #define AR5K_PCICFG_EESIZE_S … #define AR5K_PCICFG_EESIZE_4K … #define AR5K_PCICFG_EESIZE_8K … #define AR5K_PCICFG_EESIZE_16K … #define AR5K_PCICFG_EESIZE_FAIL … #define AR5K_PCICFG_LED … #define AR5K_PCICFG_LED_NONE … #define AR5K_PCICFG_LED_PEND … #define AR5K_PCICFG_LED_ASSOC … #define AR5K_PCICFG_BUS_SEL … #define AR5K_PCICFG_CBEFIX_DIS … #define AR5K_PCICFG_SL_INTEN … #define AR5K_PCICFG_LED_BCTL … #define AR5K_PCICFG_RETRY_FIX … #define AR5K_PCICFG_SL_INPEN … #define AR5K_PCICFG_SPWR_DN … #define AR5K_PCICFG_LEDMODE … #define AR5K_PCICFG_LEDMODE_PROP … #define AR5K_PCICFG_LEDMODE_PROM … #define AR5K_PCICFG_LEDMODE_PWR … #define AR5K_PCICFG_LEDMODE_RAND … #define AR5K_PCICFG_LEDBLINK … #define AR5K_PCICFG_LEDBLINK_S … #define AR5K_PCICFG_LEDSLOW … #define AR5K_PCICFG_LEDSTATE … #define AR5K_PCICFG_SLEEP_CLOCK_RATE … #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S … /* * "General Purpose Input/Output" (GPIO) control register * * I'm not sure about this but after looking at the code * for all chipsets here is what i got. * * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) * Mode 0 -> always input * Mode 1 -> output when GPIODO for this GPIO is set to 0 * Mode 2 -> output when GPIODO for this GPIO is set to 1 * Mode 3 -> always output * * For more infos check out get_gpio/set_gpio and * set_gpio_input/set_gpio_output functs. * For more infos on gpio interrupt check out set_gpio_intr. */ #define AR5K_NUM_GPIO … #define AR5K_GPIOCR … #define AR5K_GPIOCR_INT_ENA … #define AR5K_GPIOCR_INT_SELL … #define AR5K_GPIOCR_INT_SELH … #define AR5K_GPIOCR_IN(n) … #define AR5K_GPIOCR_OUT0(n) … #define AR5K_GPIOCR_OUT1(n) … #define AR5K_GPIOCR_OUT(n) … #define AR5K_GPIOCR_INT_SEL(n) … /* * "General Purpose Input/Output" (GPIO) data output register */ #define AR5K_GPIODO … /* * "General Purpose Input/Output" (GPIO) data input register */ #define AR5K_GPIODI … #define AR5K_GPIODI_M … /* * Silicon revision register */ #define AR5K_SREV … #define AR5K_SREV_REV … #define AR5K_SREV_REV_S … #define AR5K_SREV_VER … #define AR5K_SREV_VER_S … /* * TXE write posting register */ #define AR5K_TXEPOST … /* * QCU sleep mask */ #define AR5K_QCU_SLEEP_MASK … /* 0x4068 is compression buffer configuration * register on 5414 and pm configuration register * on 5424 and newer pci-e chips. */ /* * Compression buffer configuration * register (enable/disable) [5414] */ #define AR5K_5414_CBCFG … #define AR5K_5414_CBCFG_BUF_DIS … /* * PCI-E Power management configuration * and status register [5424+] */ #define AR5K_PCIE_PM_CTL … /* Only 5424 */ #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 … #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR … #define AR5K_PCIE_PM_CTL_L0_L0S_EN … #define AR5K_PCIE_PM_CTL_LDRESET_EN … /* Wake On Wireless */ #define AR5K_PCIE_PM_CTL_PME_EN … #define AR5K_PCIE_PM_CTL_AUX_PWR_DET … #define AR5K_PCIE_PM_CTL_PME_CLEAR … #define AR5K_PCIE_PM_CTL_PSM_D0 … #define AR5K_PCIE_PM_CTL_PSM_D1 … #define AR5K_PCIE_PM_CTL_PSM_D2 … #define AR5K_PCIE_PM_CTL_PSM_D3 … /* * PCI-E Workaround enable register */ #define AR5K_PCIE_WAEN … /* * PCI-E Serializer/Deserializer * registers */ #define AR5K_PCIE_SERDES … #define AR5K_PCIE_SERDES_RESET … /*====EEPROM REGISTERS====*/ /* * EEPROM access registers * * Here we got a difference between 5210/5211-12 * read data register for 5210 is at 0x6800 and * status register is at 0x6c00. There is also * no eeprom command register on 5210 and the * offsets are different. * * To read eeprom data for a specific offset: * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) * read AR5K_EEPROM_BASE +(4 * offset) * check the eeprom status register * and read eeprom data register. * * 5211 - write offset to AR5K_EEPROM_BASE * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD * check the eeprom status register * and read eeprom data register. * * To write eeprom data for a specific offset: * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) * write data to AR5K_EEPROM_BASE +(4 * offset) * check the eeprom status register * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD * 5212 write offset to AR5K_EEPROM_BASE * write data to data register * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD * check the eeprom status register * * For more infos check eeprom_* functs and the ar5k.c * file posted in madwifi-devel mailing list. * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 * */ #define AR5K_EEPROM_BASE … /* * EEPROM data register */ #define AR5K_EEPROM_DATA_5211 … #define AR5K_EEPROM_DATA_5210 … #define AR5K_EEPROM_DATA … /* * EEPROM command register */ #define AR5K_EEPROM_CMD … #define AR5K_EEPROM_CMD_READ … #define AR5K_EEPROM_CMD_WRITE … #define AR5K_EEPROM_CMD_RESET … /* * EEPROM status register */ #define AR5K_EEPROM_STAT_5210 … #define AR5K_EEPROM_STAT_5211 … #define AR5K_EEPROM_STATUS … #define AR5K_EEPROM_STAT_RDERR … #define AR5K_EEPROM_STAT_RDDONE … #define AR5K_EEPROM_STAT_WRERR … #define AR5K_EEPROM_STAT_WRDONE … /* * EEPROM config register */ #define AR5K_EEPROM_CFG … #define AR5K_EEPROM_CFG_SIZE … #define AR5K_EEPROM_CFG_SIZE_AUTO … #define AR5K_EEPROM_CFG_SIZE_4KBIT … #define AR5K_EEPROM_CFG_SIZE_8KBIT … #define AR5K_EEPROM_CFG_SIZE_16KBIT … #define AR5K_EEPROM_CFG_WR_WAIT_DIS … #define AR5K_EEPROM_CFG_CLK_RATE … #define AR5K_EEPROM_CFG_CLK_RATE_S … #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ … #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ … #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ … #define AR5K_EEPROM_CFG_PROT_KEY … #define AR5K_EEPROM_CFG_PROT_KEY_S … #define AR5K_EEPROM_CFG_LIND_EN … /* * TODO: Wake On Wireless registers * Range 0x7000 - 0x7ce0 */ /* * Protocol Control Unit (PCU) registers */ /* * Used for checking initial register writes * during channel reset (see reset func) */ #define AR5K_PCU_MIN … #define AR5K_PCU_MAX … /* * First station id register (Lower 32 bits of MAC address) */ #define AR5K_STA_ID0 … #define AR5K_STA_ID0_ARRD_L32 … /* * Second station id register (Upper 16 bits of MAC address + PCU settings) */ #define AR5K_STA_ID1 … #define AR5K_STA_ID1_ADDR_U16 … #define AR5K_STA_ID1_AP … #define AR5K_STA_ID1_ADHOC … #define AR5K_STA_ID1_PWR_SV … #define AR5K_STA_ID1_NO_KEYSRCH … #define AR5K_STA_ID1_NO_PSPOLL … #define AR5K_STA_ID1_PCF_5211 … #define AR5K_STA_ID1_PCF_5210 … #define AR5K_STA_ID1_PCF … #define AR5K_STA_ID1_DEFAULT_ANTENNA … #define AR5K_STA_ID1_DESC_ANTENNA … #define AR5K_STA_ID1_RTS_DEF_ANTENNA … #define AR5K_STA_ID1_ACKCTS_6MB … #define AR5K_STA_ID1_BASE_RATE_11B … #define AR5K_STA_ID1_SELFGEN_DEF_ANT … #define AR5K_STA_ID1_CRYPT_MIC_EN … #define AR5K_STA_ID1_KEYSRCH_MODE … #define AR5K_STA_ID1_PRESERVE_SEQ_NUM … #define AR5K_STA_ID1_CBCIV_ENDIAN … #define AR5K_STA_ID1_KEYSRCH_MCAST … #define AR5K_STA_ID1_ANTENNA_SETTINGS … /* * First BSSID register (MAC address, lower 32bits) */ #define AR5K_BSS_ID0 … /* * Second BSSID register (MAC address in upper 16 bits) * * AID: Association ID */ #define AR5K_BSS_ID1 … #define AR5K_BSS_ID1_AID … #define AR5K_BSS_ID1_AID_S … /* * Backoff slot time register */ #define AR5K_SLOT_TIME … /* * ACK/CTS timeout register */ #define AR5K_TIME_OUT … #define AR5K_TIME_OUT_ACK … #define AR5K_TIME_OUT_ACK_S … #define AR5K_TIME_OUT_CTS … #define AR5K_TIME_OUT_CTS_S … /* * RSSI threshold register */ #define AR5K_RSSI_THR … #define AR5K_RSSI_THR_M … #define AR5K_RSSI_THR_BMISS_5210 … #define AR5K_RSSI_THR_BMISS_5210_S … #define AR5K_RSSI_THR_BMISS_5211 … #define AR5K_RSSI_THR_BMISS_5211_S … #define AR5K_RSSI_THR_BMISS … #define AR5K_RSSI_THR_BMISS_S … /* * 5210 has more PCU registers because there is no QCU/DCU * so queue parameters are set here, this way a lot common * registers have different address for 5210. To make things * easier we define a macro based on ah->ah_version for common * registers with different addresses and common flags. */ /* * Retry limit register * * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) */ #define AR5K_NODCU_RETRY_LMT … #define AR5K_NODCU_RETRY_LMT_SH_RETRY … #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S … #define AR5K_NODCU_RETRY_LMT_LG_RETRY … #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S … #define AR5K_NODCU_RETRY_LMT_SSH_RETRY … #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S … #define AR5K_NODCU_RETRY_LMT_SLG_RETRY … #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S … #define AR5K_NODCU_RETRY_LMT_CW_MIN … #define AR5K_NODCU_RETRY_LMT_CW_MIN_S … /* * Transmit latency register */ #define AR5K_USEC_5210 … #define AR5K_USEC_5211 … #define AR5K_USEC … #define AR5K_USEC_1 … #define AR5K_USEC_1_S … #define AR5K_USEC_32 … #define AR5K_USEC_32_S … #define AR5K_USEC_TX_LATENCY_5211 … #define AR5K_USEC_TX_LATENCY_5211_S … #define AR5K_USEC_RX_LATENCY_5211 … #define AR5K_USEC_RX_LATENCY_5211_S … #define AR5K_USEC_TX_LATENCY_5210 … #define AR5K_USEC_TX_LATENCY_5210_S … #define AR5K_USEC_RX_LATENCY_5210 … #define AR5K_USEC_RX_LATENCY_5210_S … /* * PCU beacon control register */ #define AR5K_BEACON_5210 … #define AR5K_BEACON_5211 … #define AR5K_BEACON … #define AR5K_BEACON_PERIOD … #define AR5K_BEACON_PERIOD_S … #define AR5K_BEACON_TIM … #define AR5K_BEACON_TIM_S … #define AR5K_BEACON_ENABLE … #define AR5K_BEACON_RESET_TSF … /* * CFP period register */ #define AR5K_CFP_PERIOD_5210 … #define AR5K_CFP_PERIOD_5211 … #define AR5K_CFP_PERIOD … /* * Next beacon time register */ #define AR5K_TIMER0_5210 … #define AR5K_TIMER0_5211 … #define AR5K_TIMER0 … /* * Next DMA beacon alert register */ #define AR5K_TIMER1_5210 … #define AR5K_TIMER1_5211 … #define AR5K_TIMER1 … /* * Next software beacon alert register */ #define AR5K_TIMER2_5210 … #define AR5K_TIMER2_5211 … #define AR5K_TIMER2 … /* * Next ATIM window time register */ #define AR5K_TIMER3_5210 … #define AR5K_TIMER3_5211 … #define AR5K_TIMER3 … /* * 5210 First inter frame spacing register (IFS) */ #define AR5K_IFS0 … #define AR5K_IFS0_SIFS … #define AR5K_IFS0_SIFS_S … #define AR5K_IFS0_DIFS … #define AR5K_IFS0_DIFS_S … /* * 5210 Second inter frame spacing register (IFS) */ #define AR5K_IFS1 … #define AR5K_IFS1_PIFS … #define AR5K_IFS1_PIFS_S … #define AR5K_IFS1_EIFS … #define AR5K_IFS1_EIFS_S … #define AR5K_IFS1_CS_EN … #define AR5K_IFS1_CS_EN_S … /* * CFP duration register */ #define AR5K_CFP_DUR_5210 … #define AR5K_CFP_DUR_5211 … #define AR5K_CFP_DUR … /* * Receive filter register */ #define AR5K_RX_FILTER_5210 … #define AR5K_RX_FILTER_5211 … #define AR5K_RX_FILTER … #define AR5K_RX_FILTER_UCAST … #define AR5K_RX_FILTER_MCAST … #define AR5K_RX_FILTER_BCAST … #define AR5K_RX_FILTER_CONTROL … #define AR5K_RX_FILTER_BEACON … #define AR5K_RX_FILTER_PROM … #define AR5K_RX_FILTER_XRPOLL … #define AR5K_RX_FILTER_PROBEREQ … #define AR5K_RX_FILTER_PHYERR_5212 … #define AR5K_RX_FILTER_RADARERR_5212 … #define AR5K_RX_FILTER_PHYERR_5211 … #define AR5K_RX_FILTER_RADARERR_5211 … #define AR5K_RX_FILTER_PHYERR … #define AR5K_RX_FILTER_RADARERR … /* * Multicast filter register (lower 32 bits) */ #define AR5K_MCAST_FILTER0_5210 … #define AR5K_MCAST_FILTER0_5211 … #define AR5K_MCAST_FILTER0 … /* * Multicast filter register (higher 16 bits) */ #define AR5K_MCAST_FILTER1_5210 … #define AR5K_MCAST_FILTER1_5211 … #define AR5K_MCAST_FILTER1 … /* * Transmit mask register (lower 32 bits) [5210] */ #define AR5K_TX_MASK0 … /* * Transmit mask register (higher 16 bits) [5210] */ #define AR5K_TX_MASK1 … /* * Clear transmit mask [5210] */ #define AR5K_CLR_TMASK … /* * Trigger level register (before transmission) [5210] */ #define AR5K_TRIG_LVL … /* * PCU Diagnostic register * * Used for tweaking/diagnostics. */ #define AR5K_DIAG_SW_5210 … #define AR5K_DIAG_SW_5211 … #define AR5K_DIAG_SW … #define AR5K_DIAG_SW_DIS_WEP_ACK … #define AR5K_DIAG_SW_DIS_ACK … #define AR5K_DIAG_SW_DIS_CTS … #define AR5K_DIAG_SW_DIS_ENC … #define AR5K_DIAG_SW_DIS_DEC … #define AR5K_DIAG_SW_DIS_TX_5210 … #define AR5K_DIAG_SW_DIS_RX_5210 … #define AR5K_DIAG_SW_DIS_RX_5211 … #define AR5K_DIAG_SW_DIS_RX … #define AR5K_DIAG_SW_LOOP_BACK_5210 … #define AR5K_DIAG_SW_LOOP_BACK_5211 … #define AR5K_DIAG_SW_LOOP_BACK … #define AR5K_DIAG_SW_CORR_FCS_5210 … #define AR5K_DIAG_SW_CORR_FCS_5211 … #define AR5K_DIAG_SW_CORR_FCS … #define AR5K_DIAG_SW_CHAN_INFO_5210 … #define AR5K_DIAG_SW_CHAN_INFO_5211 … #define AR5K_DIAG_SW_CHAN_INFO … #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 … #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 … #define AR5K_DIAG_SW_EN_SCRAM_SEED … #define AR5K_DIAG_SW_ECO_ENABLE … #define AR5K_DIAG_SW_SCVRAM_SEED … #define AR5K_DIAG_SW_SCRAM_SEED_M … #define AR5K_DIAG_SW_SCRAM_SEED_S … #define AR5K_DIAG_SW_DIS_SEQ_INC_5210 … #define AR5K_DIAG_SW_FRAME_NV0_5210 … #define AR5K_DIAG_SW_FRAME_NV0_5211 … #define AR5K_DIAG_SW_FRAME_NV0 … #define AR5K_DIAG_SW_OBSPT_M … #define AR5K_DIAG_SW_OBSPT_S … #define AR5K_DIAG_SW_RX_CLEAR_HIGH … #define AR5K_DIAG_SW_IGNORE_CARR_SENSE … #define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH … #define AR5K_DIAG_SW_PHEAR_ME … /* * TSF (clock) register (lower 32 bits) */ #define AR5K_TSF_L32_5210 … #define AR5K_TSF_L32_5211 … #define AR5K_TSF_L32 … /* * TSF (clock) register (higher 32 bits) */ #define AR5K_TSF_U32_5210 … #define AR5K_TSF_U32_5211 … #define AR5K_TSF_U32 … /* * Last beacon timestamp register (Read Only) */ #define AR5K_LAST_TSTP … /* * ADDAC test register [5211+] */ #define AR5K_ADDAC_TEST … #define AR5K_ADDAC_TEST_TXCONT … #define AR5K_ADDAC_TEST_TST_MODE … #define AR5K_ADDAC_TEST_LOOP_EN … #define AR5K_ADDAC_TEST_LOOP_LEN … #define AR5K_ADDAC_TEST_USE_U8 … #define AR5K_ADDAC_TEST_MSB … #define AR5K_ADDAC_TEST_TRIG_SEL … #define AR5K_ADDAC_TEST_TRIG_PTY … #define AR5K_ADDAC_TEST_RXCONT … #define AR5K_ADDAC_TEST_CAPTURE … #define AR5K_ADDAC_TEST_TST_ARM … /* * Default antenna register [5211+] */ #define AR5K_DEFAULT_ANTENNA … /* * Frame control QoS mask register (?) [5211+] * (FC_QOS_MASK) */ #define AR5K_FRAME_CTL_QOSM … /* * Seq mask register (?) [5211+] */ #define AR5K_SEQ_MASK … /* * Retry count register [5210] */ #define AR5K_RETRY_CNT … #define AR5K_RETRY_CNT_SSH … #define AR5K_RETRY_CNT_SLG … /* * Back-off status register [5210] */ #define AR5K_BACKOFF … #define AR5K_BACKOFF_CW … #define AR5K_BACKOFF_CNT … /* * NAV register (current) */ #define AR5K_NAV_5210 … #define AR5K_NAV_5211 … #define AR5K_NAV … /* * MIB counters: * * max value is 0xc000, if this is reached we get a MIB interrupt. * they can be controlled via AR5K_MIBC and are cleared on read. */ /* * RTS success (MIB counter) */ #define AR5K_RTS_OK_5210 … #define AR5K_RTS_OK_5211 … #define AR5K_RTS_OK … /* * RTS failure (MIB counter) */ #define AR5K_RTS_FAIL_5210 … #define AR5K_RTS_FAIL_5211 … #define AR5K_RTS_FAIL … /* * ACK failure (MIB counter) */ #define AR5K_ACK_FAIL_5210 … #define AR5K_ACK_FAIL_5211 … #define AR5K_ACK_FAIL … /* * FCS failure (MIB counter) */ #define AR5K_FCS_FAIL_5210 … #define AR5K_FCS_FAIL_5211 … #define AR5K_FCS_FAIL … /* * Beacon count register */ #define AR5K_BEACON_CNT_5210 … #define AR5K_BEACON_CNT_5211 … #define AR5K_BEACON_CNT … /*===5212 Specific PCU registers===*/ /* * Transmit power control register */ #define AR5K_TPC … #define AR5K_TPC_ACK … #define AR5K_TPC_ACK_S … #define AR5K_TPC_CTS … #define AR5K_TPC_CTS_S … #define AR5K_TPC_CHIRP … #define AR5K_TPC_CHIRP_S … #define AR5K_TPC_DOPPLER … #define AR5K_TPC_DOPPLER_S … /* * XR (eXtended Range) mode register */ #define AR5K_XRMODE … #define AR5K_XRMODE_POLL_TYPE_M … #define AR5K_XRMODE_POLL_TYPE_S … #define AR5K_XRMODE_POLL_SUBTYPE_M … #define AR5K_XRMODE_POLL_SUBTYPE_S … #define AR5K_XRMODE_POLL_WAIT_ALL … #define AR5K_XRMODE_SIFS_DELAY … #define AR5K_XRMODE_FRAME_HOLD_M … #define AR5K_XRMODE_FRAME_HOLD_S … /* * XR delay register */ #define AR5K_XRDELAY … #define AR5K_XRDELAY_SLOT_DELAY_M … #define AR5K_XRDELAY_SLOT_DELAY_S … #define AR5K_XRDELAY_CHIRP_DELAY_M … #define AR5K_XRDELAY_CHIRP_DELAY_S … /* * XR timeout register */ #define AR5K_XRTIMEOUT … #define AR5K_XRTIMEOUT_CHIRP_M … #define AR5K_XRTIMEOUT_CHIRP_S … #define AR5K_XRTIMEOUT_POLL_M … #define AR5K_XRTIMEOUT_POLL_S … /* * XR chirp register */ #define AR5K_XRCHIRP … #define AR5K_XRCHIRP_SEND … #define AR5K_XRCHIRP_GAP … /* * XR stomp register */ #define AR5K_XRSTOMP … #define AR5K_XRSTOMP_TX … #define AR5K_XRSTOMP_RX … #define AR5K_XRSTOMP_TX_RSSI … #define AR5K_XRSTOMP_TX_BSSID … #define AR5K_XRSTOMP_DATA … #define AR5K_XRSTOMP_RSSI_THRES … /* * First enhanced sleep register */ #define AR5K_SLEEP0 … #define AR5K_SLEEP0_NEXT_DTIM … #define AR5K_SLEEP0_NEXT_DTIM_S … #define AR5K_SLEEP0_ASSUME_DTIM … #define AR5K_SLEEP0_ENH_SLEEP_EN … #define AR5K_SLEEP0_CABTO … #define AR5K_SLEEP0_CABTO_S … /* * Second enhanced sleep register */ #define AR5K_SLEEP1 … #define AR5K_SLEEP1_NEXT_TIM … #define AR5K_SLEEP1_NEXT_TIM_S … #define AR5K_SLEEP1_BEACON_TO … #define AR5K_SLEEP1_BEACON_TO_S … /* * Third enhanced sleep register */ #define AR5K_SLEEP2 … #define AR5K_SLEEP2_TIM_PER … #define AR5K_SLEEP2_TIM_PER_S … #define AR5K_SLEEP2_DTIM_PER … #define AR5K_SLEEP2_DTIM_PER_S … /* * TX power control (TPC) register * * XXX: PCDAC steps (0.5dBm) or dBm ? * */ #define AR5K_TXPC … #define AR5K_TXPC_ACK_M … #define AR5K_TXPC_ACK_S … #define AR5K_TXPC_CTS_M … #define AR5K_TXPC_CTS_S … #define AR5K_TXPC_CHIRP_M … #define AR5K_TXPC_CHIRP_S … #define AR5K_TXPC_DOPPLER … #define AR5K_TXPC_DOPPLER_S … /* * Profile count registers * * These registers can be cleared and frozen with ATH5K_MIBC, but they do not * generate a MIB interrupt. * Instead of overflowing, they shift by one bit to the right. All registers * shift together, i.e. when one reaches the max, all shift at the same time by * one bit to the right. This way we should always get consistent values. */ #define AR5K_PROFCNT_TX … #define AR5K_PROFCNT_RX … #define AR5K_PROFCNT_RXCLR … #define AR5K_PROFCNT_CYCLE … /* * Quiet period control registers */ #define AR5K_QUIET_CTL1 … #define AR5K_QUIET_CTL1_NEXT_QT_TSF … #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S … #define AR5K_QUIET_CTL1_QT_EN … #define AR5K_QUIET_CTL1_ACK_CTS_EN … #define AR5K_QUIET_CTL2 … #define AR5K_QUIET_CTL2_QT_PER … #define AR5K_QUIET_CTL2_QT_PER_S … #define AR5K_QUIET_CTL2_QT_DUR … #define AR5K_QUIET_CTL2_QT_DUR_S … /* * TSF parameter register */ #define AR5K_TSF_PARM … #define AR5K_TSF_PARM_INC … #define AR5K_TSF_PARM_INC_S … /* * QoS NOACK policy */ #define AR5K_QOS_NOACK … #define AR5K_QOS_NOACK_2BIT_VALUES … #define AR5K_QOS_NOACK_2BIT_VALUES_S … #define AR5K_QOS_NOACK_BIT_OFFSET … #define AR5K_QOS_NOACK_BIT_OFFSET_S … #define AR5K_QOS_NOACK_BYTE_OFFSET … #define AR5K_QOS_NOACK_BYTE_OFFSET_S … /* * PHY error filter register */ #define AR5K_PHY_ERR_FIL … #define AR5K_PHY_ERR_FIL_RADAR … #define AR5K_PHY_ERR_FIL_OFDM … #define AR5K_PHY_ERR_FIL_CCK … /* * XR latency register */ #define AR5K_XRLAT_TX … /* * ACK SIFS register */ #define AR5K_ACKSIFS … #define AR5K_ACKSIFS_INC … /* * MIC QoS control register (?) */ #define AR5K_MIC_QOS_CTL … #define AR5K_MIC_QOS_CTL_OFF(_n) … #define AR5K_MIC_QOS_CTL_MQ_EN … /* * MIC QoS select register (?) */ #define AR5K_MIC_QOS_SEL … #define AR5K_MIC_QOS_SEL_OFF(_n) … /* * Misc mode control register (?) */ #define AR5K_MISC_MODE … #define AR5K_MISC_MODE_FBSSID_MATCH … #define AR5K_MISC_MODE_ACKSIFS_MEM … #define AR5K_MISC_MODE_COMBINED_MIC … /* more bits */ /* * OFDM Filter counter */ #define AR5K_OFDM_FIL_CNT … /* * CCK Filter counter */ #define AR5K_CCK_FIL_CNT … /* * PHY Error Counters (same masks as AR5K_PHY_ERR_FIL) */ #define AR5K_PHYERR_CNT1 … #define AR5K_PHYERR_CNT1_MASK … #define AR5K_PHYERR_CNT2 … #define AR5K_PHYERR_CNT2_MASK … /* if the PHY Error Counters reach this maximum, we get MIB interrupts */ #define ATH5K_PHYERR_CNT_MAX … /* * TSF Threshold register (?) */ #define AR5K_TSF_THRES … /* * TODO: Wake On Wireless registers * Range: 0x8147 - 0x818c */ /* * Rate -> ACK SIFS mapping table (32 entries) */ #define AR5K_RATE_ACKSIFS_BASE … #define AR5K_RATE_ACKSIFS(_n) … #define AR5K_RATE_ACKSIFS_NORMAL … #define AR5K_RATE_ACKSIFS_TURBO … /* * Rate -> duration mapping table (32 entries) */ #define AR5K_RATE_DUR_BASE … #define AR5K_RATE_DUR(_n) … /* * Rate -> db mapping table * (8 entries, each one has 4 8bit fields) */ #define AR5K_RATE2DB_BASE … #define AR5K_RATE2DB(_n) … /* * db -> Rate mapping table * (8 entries, each one has 4 8bit fields) */ #define AR5K_DB2RATE_BASE … #define AR5K_DB2RATE(_n) … /*===5212 end===*/ #define AR5K_KEYTABLE_SIZE_5210 … #define AR5K_KEYTABLE_SIZE_5211 … /*===PHY REGISTERS===*/ /* * PHY registers start */ #define AR5K_PHY_BASE … #define AR5K_PHY(_n) … /* * TST_2 (Misc config parameters) */ #define AR5K_PHY_TST2 … #define AR5K_PHY_TST2_TRIG_SEL … #define AR5K_PHY_TST2_TRIG … #define AR5K_PHY_TST2_CBUS_MODE … #define AR5K_PHY_TST2_CLK32 … #define AR5K_PHY_TST2_CHANCOR_DUMP_EN … #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP … #define AR5K_PHY_TST2_RFSILENT_EN … #define AR5K_PHY_TST2_ALT_RFDATA … #define AR5K_PHY_TST2_MINI_OBS_EN … #define AR5K_PHY_TST2_RX2_IS_RX5_INV … #define AR5K_PHY_TST2_SLOW_CLK160 … #define AR5K_PHY_TST2_AGC_OBS_SEL_3 … #define AR5K_PHY_TST2_BBB_OBS_SEL … #define AR5K_PHY_TST2_ADC_OBS_SEL … #define AR5K_PHY_TST2_RX_CLR_SEL … #define AR5K_PHY_TST2_FORCE_AGC_CLR … #define AR5K_PHY_SHIFT_2GHZ … #define AR5K_PHY_SHIFT_5GHZ … /* * PHY frame control register [5110] /turbo mode register [5111+] * * There is another frame control register for [5111+] * at address 0x9944 (see below) but the 2 first flags * are common here between 5110 frame control register * and [5111+] turbo mode register, so this also works as * a "turbo mode register" for 5110. We treat this one as * a frame control register for 5110 below. */ #define AR5K_PHY_TURBO … #define AR5K_PHY_TURBO_MODE … #define AR5K_PHY_TURBO_SHORT … #define AR5K_PHY_TURBO_MIMO … /* * PHY agility command register * (aka TST_1) */ #define AR5K_PHY_AGC … #define AR5K_PHY_TST1 … #define AR5K_PHY_AGC_DISABLE … #define AR5K_PHY_TST1_TXHOLD … #define AR5K_PHY_TST1_TXSRC_SRC … #define AR5K_PHY_TST1_TXSRC_SRC_S … #define AR5K_PHY_TST1_TXSRC_ALT … #define AR5K_PHY_TST1_TXSRC_ALT_S … /* * PHY timing register 3 [5112+] */ #define AR5K_PHY_TIMING_3 … #define AR5K_PHY_TIMING_3_DSC_MAN … #define AR5K_PHY_TIMING_3_DSC_MAN_S … #define AR5K_PHY_TIMING_3_DSC_EXP … #define AR5K_PHY_TIMING_3_DSC_EXP_S … /* * PHY chip revision register */ #define AR5K_PHY_CHIP_ID … /* * PHY activation register */ #define AR5K_PHY_ACT … #define AR5K_PHY_ACT_ENABLE … #define AR5K_PHY_ACT_DISABLE … /* * PHY RF control registers */ #define AR5K_PHY_RF_CTL2 … #define AR5K_PHY_RF_CTL2_TXF2TXD_START … #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S … #define AR5K_PHY_RF_CTL3 … #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON … #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S … #define AR5K_PHY_ADC_CTL … #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF … #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S … #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF … #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF … #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF … #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON … #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S … #define AR5K_PHY_RF_CTL4 … #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON … #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON … #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF … #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF … /* * Pre-Amplifier control register * (XPA -> external pre-amplifier) */ #define AR5K_PHY_PA_CTL … #define AR5K_PHY_PA_CTL_XPA_A_HI … #define AR5K_PHY_PA_CTL_XPA_B_HI … #define AR5K_PHY_PA_CTL_XPA_A_EN … #define AR5K_PHY_PA_CTL_XPA_B_EN … /* * PHY settling register */ #define AR5K_PHY_SETTLING … #define AR5K_PHY_SETTLING_AGC … #define AR5K_PHY_SETTLING_AGC_S … #define AR5K_PHY_SETTLING_SWITCH … #define AR5K_PHY_SETTLING_SWITCH_S … /* * PHY Gain registers */ #define AR5K_PHY_GAIN … #define AR5K_PHY_GAIN_TXRX_ATTEN … #define AR5K_PHY_GAIN_TXRX_ATTEN_S … #define AR5K_PHY_GAIN_TXRX_RF_MAX … #define AR5K_PHY_GAIN_TXRX_RF_MAX_S … #define AR5K_PHY_GAIN_OFFSET … #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG … /* * Desired ADC/PGA size register * (for more infos read ANI patent) */ #define AR5K_PHY_DESIRED_SIZE … #define AR5K_PHY_DESIRED_SIZE_ADC … #define AR5K_PHY_DESIRED_SIZE_ADC_S … #define AR5K_PHY_DESIRED_SIZE_PGA … #define AR5K_PHY_DESIRED_SIZE_PGA_S … #define AR5K_PHY_DESIRED_SIZE_TOT … #define AR5K_PHY_DESIRED_SIZE_TOT_S … /* * PHY signal register * (for more infos read ANI patent) */ #define AR5K_PHY_SIG … #define AR5K_PHY_SIG_FIRSTEP … #define AR5K_PHY_SIG_FIRSTEP_S … #define AR5K_PHY_SIG_FIRPWR … #define AR5K_PHY_SIG_FIRPWR_S … /* * PHY coarse agility control register * (for more infos read ANI patent) */ #define AR5K_PHY_AGCCOARSE … #define AR5K_PHY_AGCCOARSE_LO … #define AR5K_PHY_AGCCOARSE_LO_S … #define AR5K_PHY_AGCCOARSE_HI … #define AR5K_PHY_AGCCOARSE_HI_S … /* * PHY agility control register */ #define AR5K_PHY_AGCCTL … #define AR5K_PHY_AGCCTL_CAL … #define AR5K_PHY_AGCCTL_NF … #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS … #define AR5K_PHY_AGCCTL_NF_EN … #define AR5K_PHY_AGCTL_FLTR_CAL … #define AR5K_PHY_AGCCTL_NF_NOUPDATE … /* * PHY noise floor status register (CCA = Clear Channel Assessment) */ #define AR5K_PHY_NF … #define AR5K_PHY_NF_M … #define AR5K_PHY_NF_SVAL(_n) … #define AR5K_PHY_NF_THRESH62 … #define AR5K_PHY_NF_THRESH62_S … #define AR5K_PHY_NF_MINCCA_PWR … #define AR5K_PHY_NF_MINCCA_PWR_S … /* * PHY ADC saturation register [5110] */ #define AR5K_PHY_ADCSAT … #define AR5K_PHY_ADCSAT_ICNT … #define AR5K_PHY_ADCSAT_ICNT_S … #define AR5K_PHY_ADCSAT_THR … #define AR5K_PHY_ADCSAT_THR_S … /* * PHY Weak ofdm signal detection threshold registers (ANI) [5212+] */ /* High thresholds */ #define AR5K_PHY_WEAK_OFDM_HIGH_THR … #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT … #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S … #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 … #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S … #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 … #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S … /* Low thresholds */ #define AR5K_PHY_WEAK_OFDM_LOW_THR … #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN … #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT … #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S … #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 … #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S … #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 … #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S … /* * PHY sleep registers [5112+] */ #define AR5K_PHY_SCR … #define AR5K_PHY_SLMT … #define AR5K_PHY_SLMT_32MHZ … #define AR5K_PHY_SCAL … #define AR5K_PHY_SCAL_32MHZ … #define AR5K_PHY_SCAL_32MHZ_5311 … #define AR5K_PHY_SCAL_32MHZ_2417 … #define AR5K_PHY_SCAL_32MHZ_HB63 … /* * PHY PLL (Phase Locked Loop) control register */ #define AR5K_PHY_PLL … #define AR5K_PHY_PLL_20MHZ … /* 40MHz -> 5GHz band */ #define AR5K_PHY_PLL_40MHZ_5211 … #define AR5K_PHY_PLL_40MHZ_5212 … #define AR5K_PHY_PLL_40MHZ_5413 … #define AR5K_PHY_PLL_40MHZ … /* 44MHz -> 2.4GHz band */ #define AR5K_PHY_PLL_44MHZ_5211 … #define AR5K_PHY_PLL_44MHZ_5212 … #define AR5K_PHY_PLL_44MHZ … #define AR5K_PHY_PLL_RF5111 … #define AR5K_PHY_PLL_RF5112 … #define AR5K_PHY_PLL_HALF_RATE … #define AR5K_PHY_PLL_QUARTER_RATE … /* * RF Buffer register * * It's obvious from the code that 0x989c is the buffer register but * for the other special registers that we write to after sending each * packet, i have no idea. So I'll name them BUFFER_CONTROL_X registers * for now. It's interesting that they are also used for some other operations. */ #define AR5K_RF_BUFFER … #define AR5K_RF_BUFFER_CONTROL_0 … #define AR5K_RF_BUFFER_CONTROL_1 … #define AR5K_RF_BUFFER_CONTROL_2 … #define AR5K_RF_BUFFER_CONTROL_3 … /* Channel set on 5111 */ /* Used to read radio revision*/ #define AR5K_RF_BUFFER_CONTROL_4 … /* Bank 0,1,2,6 on 5111 */ /* Bank 1 on 5112 */ /* Used during activation on 5111 */ #define AR5K_RF_BUFFER_CONTROL_5 … /* Used during activation on 5111 */ /* Channel on 5112 */ /* Bank 6 on 5112 */ #define AR5K_RF_BUFFER_CONTROL_6 … /* * PHY RF stage register [5210] */ #define AR5K_PHY_RFSTG … #define AR5K_PHY_RFSTG_DISABLE … /* * BIN masks (?) */ #define AR5K_PHY_BIN_MASK_1 … #define AR5K_PHY_BIN_MASK_2 … #define AR5K_PHY_BIN_MASK_3 … #define AR5K_PHY_BIN_MASK_CTL … #define AR5K_PHY_BIN_MASK_CTL_MASK_4 … #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S … #define AR5K_PHY_BIN_MASK_CTL_RATE … #define AR5K_PHY_BIN_MASK_CTL_RATE_S … /* * PHY Antenna control register */ #define AR5K_PHY_ANT_CTL … #define AR5K_PHY_ANT_CTL_TXRX_EN … #define AR5K_PHY_ANT_CTL_SECTORED_ANT … #define AR5K_PHY_ANT_CTL_HITUNE5 … #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE … #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S … /* * PHY receiver delay register [5111+] */ #define AR5K_PHY_RX_DELAY … #define AR5K_PHY_RX_DELAY_M … /* * PHY max rx length register (?) [5111] */ #define AR5K_PHY_MAX_RX_LEN … /* * PHY timing register 4 * I(nphase)/Q(adrature) calibration register [5111+] */ #define AR5K_PHY_IQ … #define AR5K_PHY_IQ_CORR_Q_Q_COFF … #define AR5K_PHY_IQ_CORR_Q_Q_COFF_S … #define AR5K_PHY_IQ_CORR_Q_I_COFF … #define AR5K_PHY_IQ_CORR_Q_I_COFF_S … #define AR5K_PHY_IQ_CORR_ENABLE … #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX … #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S … #define AR5K_PHY_IQ_RUN … #define AR5K_PHY_IQ_USE_PT_DF … #define AR5K_PHY_IQ_EARLY_TRIG_THR … #define AR5K_PHY_IQ_PILOT_MASK_EN … #define AR5K_PHY_IQ_CHAN_MASK_EN … #define AR5K_PHY_IQ_SPUR_FILT_EN … #define AR5K_PHY_IQ_SPUR_RSSI_EN … /* * PHY timing register 5 * OFDM Self-correlator Cyclic RSSI threshold params * (Check out bb_cycpwr_thr1 on ANI patent) */ #define AR5K_PHY_OFDM_SELFCORR … #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN … #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 … #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S … #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 … #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN … #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR … #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI … /* * PHY-only warm reset register */ #define AR5K_PHY_WARM_RESET … /* * PHY-only control register */ #define AR5K_PHY_CTL … #define AR5K_PHY_CTL_RX_DRAIN_RATE … #define AR5K_PHY_CTL_LATE_TX_SIG_SYM … #define AR5K_PHY_CTL_GEN_SCRAMBLER … #define AR5K_PHY_CTL_TX_ANT_SEL … #define AR5K_PHY_CTL_TX_ANT_STATIC … #define AR5K_PHY_CTL_RX_ANT_SEL … #define AR5K_PHY_CTL_RX_ANT_STATIC … #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN … /* * PHY PAPD probe register [5111+] */ #define AR5K_PHY_PAPD_PROBE … #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR … #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS … #define AR5K_PHY_PAPD_PROBE_COMP_GAIN … #define AR5K_PHY_PAPD_PROBE_TXPOWER … #define AR5K_PHY_PAPD_PROBE_TXPOWER_S … #define AR5K_PHY_PAPD_PROBE_TX_NEXT … #define AR5K_PHY_PAPD_PROBE_PREDIST_EN … #define AR5K_PHY_PAPD_PROBE_TYPE … #define AR5K_PHY_PAPD_PROBE_TYPE_S … #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM … #define AR5K_PHY_PAPD_PROBE_TYPE_XR … #define AR5K_PHY_PAPD_PROBE_TYPE_CCK … #define AR5K_PHY_PAPD_PROBE_GAINF … #define AR5K_PHY_PAPD_PROBE_GAINF_S … #define AR5K_PHY_PAPD_PROBE_INI_5111 … #define AR5K_PHY_PAPD_PROBE_INI_5112 … /* * PHY TX rate power registers [5112+] */ #define AR5K_PHY_TXPOWER_RATE1 … #define AR5K_PHY_TXPOWER_RATE2 … #define AR5K_PHY_TXPOWER_RATE_MAX … #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE … #define AR5K_PHY_TXPOWER_RATE3 … #define AR5K_PHY_TXPOWER_RATE4 … /* * PHY frame control register [5111+] */ #define AR5K_PHY_FRAME_CTL_5210 … #define AR5K_PHY_FRAME_CTL_5211 … #define AR5K_PHY_FRAME_CTL … /*---[5111+]---*/ #define AR5K_PHY_FRAME_CTL_WIN_LEN … #define AR5K_PHY_FRAME_CTL_WIN_LEN_S … #define AR5K_PHY_FRAME_CTL_TX_CLIP … #define AR5K_PHY_FRAME_CTL_TX_CLIP_S … #define AR5K_PHY_FRAME_CTL_PREP_CHINFO … #define AR5K_PHY_FRAME_CTL_EMU … #define AR5K_PHY_FRAME_CTL_EMU_S … /*---[5110/5111]---*/ #define AR5K_PHY_FRAME_CTL_TIMING_ERR … #define AR5K_PHY_FRAME_CTL_PARITY_ERR … #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR … #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR … #define AR5K_PHY_FRAME_CTL_SERVICE_ERR … #define AR5K_PHY_FRAME_CTL_TXURN_ERR … #define AR5K_PHY_FRAME_CTL_INI … /* * PHY Tx Power adjustment register [5212A+] */ #define AR5K_PHY_TX_PWR_ADJ … #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA … #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S … #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX … #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S … /* * PHY radar detection register [5111+] */ #define AR5K_PHY_RADAR … #define AR5K_PHY_RADAR_ENABLE … #define AR5K_PHY_RADAR_DISABLE … #define AR5K_PHY_RADAR_INBANDTHR … #define AR5K_PHY_RADAR_INBANDTHR_S … #define AR5K_PHY_RADAR_PRSSI_THR … #define AR5K_PHY_RADAR_PRSSI_THR_S … #define AR5K_PHY_RADAR_PHEIGHT_THR … #define AR5K_PHY_RADAR_PHEIGHT_THR_S … #define AR5K_PHY_RADAR_RSSI_THR … #define AR5K_PHY_RADAR_RSSI_THR_S … #define AR5K_PHY_RADAR_FIRPWR_THR … #define AR5K_PHY_RADAR_FIRPWR_THRS … /* * PHY antenna switch table registers */ #define AR5K_PHY_ANT_SWITCH_TABLE_0 … #define AR5K_PHY_ANT_SWITCH_TABLE_1 … /* * PHY Noise floor threshold */ #define AR5K_PHY_NFTHRES … /* * Sigma Delta register (?) [5213] */ #define AR5K_PHY_SIGMA_DELTA … #define AR5K_PHY_SIGMA_DELTA_ADC_SEL … #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S … #define AR5K_PHY_SIGMA_DELTA_FILT2 … #define AR5K_PHY_SIGMA_DELTA_FILT2_S … #define AR5K_PHY_SIGMA_DELTA_FILT1 … #define AR5K_PHY_SIGMA_DELTA_FILT1_S … #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP … #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S … /* * RF restart register [5112+] (?) */ #define AR5K_PHY_RESTART … #define AR5K_PHY_RESTART_DIV_GC … #define AR5K_PHY_RESTART_DIV_GC_S … /* * RF Bus access request register (for synth-only channel switching) */ #define AR5K_PHY_RFBUS_REQ … #define AR5K_PHY_RFBUS_REQ_REQUEST … /* * Spur mitigation masks (?) */ #define AR5K_PHY_TIMING_7 … #define AR5K_PHY_TIMING_8 … #define AR5K_PHY_TIMING_8_PILOT_MASK_2 … #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S … #define AR5K_PHY_BIN_MASK2_1 … #define AR5K_PHY_BIN_MASK2_2 … #define AR5K_PHY_BIN_MASK2_3 … #define AR5K_PHY_BIN_MASK2_4 … #define AR5K_PHY_BIN_MASK2_4_MASK_4 … #define AR5K_PHY_BIN_MASK2_4_MASK_4_S … #define AR5K_PHY_TIMING_9 … #define AR5K_PHY_TIMING_10 … #define AR5K_PHY_TIMING_10_PILOT_MASK_2 … #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S … /* * Spur mitigation control */ #define AR5K_PHY_TIMING_11 … #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE … #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S … #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD … #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S … #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC … #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR … /* * Gain tables */ #define AR5K_BB_GAIN_BASE … #define AR5K_BB_GAIN(_n) … #define AR5K_RF_GAIN_BASE … #define AR5K_RF_GAIN(_n) … /* * PHY timing IQ calibration result register [5111+] */ #define AR5K_PHY_IQRES_CAL_PWR_I … #define AR5K_PHY_IQRES_CAL_PWR_Q … #define AR5K_PHY_IQRES_CAL_CORR … /* * PHY current RSSI register [5111+] */ #define AR5K_PHY_CURRENT_RSSI … /* * PHY RF Bus grant register */ #define AR5K_PHY_RFBUS_GRANT … #define AR5K_PHY_RFBUS_GRANT_OK … /* * PHY ADC test register */ #define AR5K_PHY_ADC_TEST … #define AR5K_PHY_ADC_TEST_I … #define AR5K_PHY_ADC_TEST_Q … /* * PHY DAC test register */ #define AR5K_PHY_DAC_TEST … #define AR5K_PHY_DAC_TEST_I … #define AR5K_PHY_DAC_TEST_Q … /* * PHY PTAT register (?) */ #define AR5K_PHY_PTAT … /* * PHY Illegal TX rate register [5112+] */ #define AR5K_PHY_BAD_TX_RATE … /* * PHY SPUR Power register [5112+] */ #define AR5K_PHY_SPUR_PWR … #define AR5K_PHY_SPUR_PWR_I … #define AR5K_PHY_SPUR_PWR_Q … #define AR5K_PHY_SPUR_PWR_FILT … /* * PHY Channel status register [5112+] (?) */ #define AR5K_PHY_CHAN_STATUS … #define AR5K_PHY_CHAN_STATUS_BT_ACT … #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW … #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC … #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP … /* * Heavy clip enable register */ #define AR5K_PHY_HEAVY_CLIP_ENABLE … /* * PHY clock sleep registers [5112+] */ #define AR5K_PHY_SCLOCK … #define AR5K_PHY_SCLOCK_32MHZ … #define AR5K_PHY_SDELAY … #define AR5K_PHY_SDELAY_32MHZ … #define AR5K_PHY_SPENDING … /* * PHY PAPD I (power?) table (?) * (92! entries) */ #define AR5K_PHY_PAPD_I_BASE … #define AR5K_PHY_PAPD_I(_n) … /* * PHY PCDAC TX power table */ #define AR5K_PHY_PCDAC_TXPOWER_BASE … #define AR5K_PHY_PCDAC_TXPOWER(_n) … /* * PHY mode register [5111+] */ #define AR5K_PHY_MODE … #define AR5K_PHY_MODE_MOD … #define AR5K_PHY_MODE_MOD_OFDM … #define AR5K_PHY_MODE_MOD_CCK … #define AR5K_PHY_MODE_FREQ … #define AR5K_PHY_MODE_FREQ_5GHZ … #define AR5K_PHY_MODE_FREQ_2GHZ … #define AR5K_PHY_MODE_MOD_DYN … #define AR5K_PHY_MODE_RAD … #define AR5K_PHY_MODE_RAD_RF5111 … #define AR5K_PHY_MODE_RAD_RF5112 … #define AR5K_PHY_MODE_XR … #define AR5K_PHY_MODE_HALF_RATE … #define AR5K_PHY_MODE_QUARTER_RATE … /* * PHY CCK transmit control register [5111+ (?)] */ #define AR5K_PHY_CCKTXCTL … #define AR5K_PHY_CCKTXCTL_WORLD … #define AR5K_PHY_CCKTXCTL_JAPAN … #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS … #define AR5K_PHY_CCKTXCTK_DAC_SCALE … /* * PHY CCK Cross-correlator Barker RSSI threshold register [5212+] */ #define AR5K_PHY_CCK_CROSSCORR … #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR … #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S … /* Same address is used for antenna diversity activation */ #define AR5K_PHY_FAST_ANT_DIV … #define AR5K_PHY_FAST_ANT_DIV_EN … /* * PHY 2GHz gain register [5111+] */ #define AR5K_PHY_GAIN_2GHZ … #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX … #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S … #define AR5K_PHY_GAIN_2GHZ_INI_5111 … #define AR5K_PHY_CCK_RX_CTL_4 … #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT … #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S … #define AR5K_PHY_DAG_CCK_CTL … #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR … #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR … #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S … #define AR5K_PHY_FAST_ADC … #define AR5K_PHY_BLUETOOTH … /* * Transmit Power Control register * [2413+] */ #define AR5K_PHY_TPC_RG1 … #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN … #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S … #define AR5K_PHY_TPC_RG1_PDGAIN_1 … #define AR5K_PHY_TPC_RG1_PDGAIN_1_S … #define AR5K_PHY_TPC_RG1_PDGAIN_2 … #define AR5K_PHY_TPC_RG1_PDGAIN_2_S … #define AR5K_PHY_TPC_RG1_PDGAIN_3 … #define AR5K_PHY_TPC_RG1_PDGAIN_3_S … #define AR5K_PHY_TPC_RG5 … #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP … #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 … #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S … /* * PHY PDADC Tx power table */ #define AR5K_PHY_PDADC_TXPOWER_BASE … #define AR5K_PHY_PDADC_TXPOWER(_n) … /* * Platform registers for WiSoC */ #define AR5K_AR5312_RESET … #define AR5K_AR5312_RESET_BB0_COLD … #define AR5K_AR5312_RESET_BB1_COLD … #define AR5K_AR5312_RESET_WMAC0 … #define AR5K_AR5312_RESET_BB0_WARM … #define AR5K_AR5312_RESET_WMAC1 … #define AR5K_AR5312_RESET_BB1_WARM … #define AR5K_AR5312_ENABLE … #define AR5K_AR5312_ENABLE_WLAN0 … #define AR5K_AR5312_ENABLE_WLAN1 … #define AR5K_AR2315_RESET … #define AR5K_AR2315_RESET_WMAC … #define AR5K_AR2315_RESET_BB_WARM … #define AR5K_AR2315_AHB_ARB_CTL … #define AR5K_AR2315_AHB_ARB_CTL_WLAN … #define AR5K_AR2315_BYTESWAP … #define AR5K_AR2315_BYTESWAP_WMAC …
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