/* * Copyright (c) 2004-2008 Reyk Floeter <[email protected]> * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]> * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ /*************************************\ * DMA and interrupt masking functions * \*************************************/ /** * DOC: DMA and interrupt masking functions * * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and * handle queue setup for 5210 chipset (rest are handled on qcu.c). * Also we setup interrupt mask register (IMR) and read the various interrupt * status registers (ISR). */ #define pr_fmt(fmt) … #include "ath5k.h" #include "reg.h" #include "debug.h" /*********\ * Receive * \*********/ /** * ath5k_hw_start_rx_dma() - Start DMA receive * @ah: The &struct ath5k_hw */ void ath5k_hw_start_rx_dma(struct ath5k_hw *ah) { … } /** * ath5k_hw_stop_rx_dma() - Stop DMA receive * @ah: The &struct ath5k_hw */ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) { … } /** * ath5k_hw_get_rxdp() - Get RX Descriptor's address * @ah: The &struct ath5k_hw */ u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah) { … } /** * ath5k_hw_set_rxdp() - Set RX Descriptor's address * @ah: The &struct ath5k_hw * @phys_addr: RX descriptor address * * Returns -EIO if rx is active */ int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) { … } /**********\ * Transmit * \**********/ /** * ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue * @ah: The &struct ath5k_hw * @queue: The hw queue number * * Start DMA transmit for a specific queue and since 5210 doesn't have * QCU/DCU, set up queue parameters for 5210 here based on queue type (one * queue for normal data and one queue for beacons). For queue setup * on newer chips check out qcu.c. Returns -EINVAL if queue number is out * of range or if queue is already disabled. * * NOTE: Must be called after setting up tx control descriptor for that * queue (see below). */ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) { … } /** * ath5k_hw_stop_tx_dma() - Stop DMA transmit on a specific queue * @ah: The &struct ath5k_hw * @queue: The hw queue number * * Stop DMA transmit on a specific hw queue and drain queue so we don't * have any pending frames. Returns -EBUSY if we still have pending frames, * -EINVAL if queue number is out of range or inactive. */ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) { … } /** * ath5k_hw_stop_beacon_queue() - Stop beacon queue * @ah: The &struct ath5k_hw * @queue: The queue number * * Returns -EIO if queue didn't stop */ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue) { … } /** * ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue * @ah: The &struct ath5k_hw * @queue: The hw queue number * * Get TX descriptor's address for a specific queue. For 5210 we ignore * the queue number and use tx queue type since we only have 2 queues. * We use TXDP0 for normal data queue and TXDP1 for beacon queue. * For newer chips with QCU/DCU we just read the corresponding TXDP register. * * XXX: Is TXDP read and clear ? */ u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) { … } /** * ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue * @ah: The &struct ath5k_hw * @queue: The hw queue number * @phys_addr: The physical address * * Set TX descriptor's address for a specific queue. For 5210 we ignore * the queue number and we use tx queue type since we only have 2 queues * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. * For newer chips with QCU/DCU we just set the corresponding TXDP register. * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still * active. */ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) { … } /** * ath5k_hw_update_tx_triglevel() - Update tx trigger level * @ah: The &struct ath5k_hw * @increase: Flag to force increase of trigger level * * This function increases/decreases the tx trigger level for the tx fifo * buffer (aka FIFO threshold) that is used to indicate when PCU flushes * the buffer and transmits its data. Lowering this results sending small * frames more quickly but can lead to tx underruns, raising it a lot can * result other problems. Right now we start with the lowest possible * (64Bytes) and if we get tx underrun we increase it using the increase * flag. Returns -EIO if we have reached maximum/minimum. * * XXX: Link this with tx DMA size ? * XXX2: Use it to save interrupts ? */ int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) { … } /*******************\ * Interrupt masking * \*******************/ /** * ath5k_hw_is_intr_pending() - Check if we have pending interrupts * @ah: The &struct ath5k_hw * * Check if we have pending interrupts to process. Returns 1 if we * have pending interrupts and 0 if we haven't. */ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah) { … } /** * ath5k_hw_get_isr() - Get interrupt status * @ah: The @struct ath5k_hw * @interrupt_mask: Driver's interrupt mask used to filter out * interrupts in sw. * * This function is used inside our interrupt handler to determine the reason * for the interrupt by reading Primary Interrupt Status Register. Returns an * abstract interrupt status mask which is mostly ISR with some uncommon bits * being mapped on some standard non hw-specific positions * (check out &ath5k_int). * * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this * function gets called are cleared on return. */ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) { … } /** * ath5k_hw_set_imr() - Set interrupt mask * @ah: The &struct ath5k_hw * @new_mask: The new interrupt mask to be set * * Set the interrupt mask in hw to save interrupts. We do that by mapping * ath5k_int bits to hw-specific bits to remove abstraction and writing * Interrupt Mask Register. */ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) { … } /********************\ Init/Stop functions \********************/ /** * ath5k_hw_dma_init() - Initialize DMA unit * @ah: The &struct ath5k_hw * * Set DMA size and pre-enable interrupts * (driver handles tx/rx buffer setup and * dma start/stop) * * XXX: Save/restore RXDP/TXDP registers ? */ void ath5k_hw_dma_init(struct ath5k_hw *ah) { … } /** * ath5k_hw_dma_stop() - stop DMA unit * @ah: The &struct ath5k_hw * * Stop tx/rx DMA and interrupts. Returns * -EBUSY if tx or rx dma failed to stop. * * XXX: Sometimes DMA unit hangs and we have * stuck frames on tx queues, only a reset * can fix that. */ int ath5k_hw_dma_stop(struct ath5k_hw *ah) { … }
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