/* * RF Buffer handling functions * * Copyright (c) 2009 Nick Kossifidis <[email protected]> * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ /** * DOC: RF Buffer registers * * There are some special registers on the RF chip * that control various operation settings related mostly to * the analog parts (channel, gain adjustment etc). * * We don't write on those registers directly but * we send a data packet on the chip, using a special register, * that holds all the settings we need. After we've sent the * data packet, we write on another special register to notify hw * to apply the settings. This is done so that control registers * can be dynamically programmed during operation and the settings * are applied faster on the hw. * * We call each data packet an "RF Bank" and all the data we write * (all RF Banks) "RF Buffer". This file holds initial RF Buffer * data for the different RF chips, and various info to match RF * Buffer offsets with specific RF registers so that we can access * them. We tweak these settings on rfregs_init function. * * Also check out reg.h and U.S. Patent 6677779 B1 (about buffer * registers and control registers): * * https://www.google.com/patents?id=qNURAAAAEBAJ */ /** * struct ath5k_ini_rfbuffer - Initial RF Buffer settings * @rfb_bank: RF Bank number * @rfb_ctrl_register: RF Buffer control register * @rfb_mode_data: RF Buffer data for each mode * * Struct to hold default mode specific RF * register values (RF Banks) for each chip. */ struct ath5k_ini_rfbuffer { … }; /** * struct ath5k_rfb_field - An RF Buffer field (register/value) * @len: Field length * @pos: Offset on the raw packet * @col: Used for shifting * * Struct to hold RF Buffer field * infos used to access certain RF * analog registers */ struct ath5k_rfb_field { … }; /** * struct ath5k_rf_reg - RF analog register definition * @bank: RF Buffer Bank number * @index: Register's index on ath5k_rf_regx_idx * @field: The &struct ath5k_rfb_field * * We use this struct to define the set of RF registers * on each chip that we want to tweak. Some RF registers * are common between different chip versions so this saves * us space and complexity because we can refer to an rf * register by it's index no matter what chip we work with * as long as it has that register. */ struct ath5k_rf_reg { … }; /** * enum ath5k_rf_regs_idx - Map RF registers to indexes * * We do this to handle common bits and make our * life easier by using an index for each register * instead of a full rfb_field */ enum ath5k_rf_regs_idx { … }; /*******************\ * RF5111 (Sombrero) * \*******************/ /* BANK 2 len pos col */ #define AR5K_RF5111_RF_TURBO … /* BANK 6 len pos col */ #define AR5K_RF5111_OB_2GHZ … #define AR5K_RF5111_DB_2GHZ … #define AR5K_RF5111_OB_5GHZ … #define AR5K_RF5111_DB_5GHZ … #define AR5K_RF5111_PWD_XPD … #define AR5K_RF5111_XPD_GAIN … /* Access to PWD registers */ #define AR5K_RF5111_PWD(_n) … /* BANK 7 len pos col */ #define AR5K_RF5111_GAIN_I … #define AR5K_RF5111_PLO_SEL … #define AR5K_RF5111_RFGAIN_SEL … #define AR5K_RF5111_RFGAIN_STEP … /* Only on AR5212 BaseBand and up */ #define AR5K_RF5111_WAIT_S … #define AR5K_RF5111_WAIT_I … #define AR5K_RF5111_MAX_TIME … static const struct ath5k_rf_reg rf_regs_5111[] = …; /* Default mode specific settings */ static const struct ath5k_ini_rfbuffer rfb_5111[] = …; /***********************\ * RF5112/RF2112 (Derby) * \***********************/ /* BANK 2 (Common) len pos col */ #define AR5K_RF5112X_RF_TURBO … /* BANK 7 (Common) len pos col */ #define AR5K_RF5112X_GAIN_I … #define AR5K_RF5112X_MIXVGA_OVR … #define AR5K_RF5112X_MIXGAIN_OVR … #define AR5K_RF5112X_MIXGAIN_STEP … #define AR5K_RF5112X_PD_DELAY_A … #define AR5K_RF5112X_PD_DELAY_B … #define AR5K_RF5112X_PD_DELAY_XR … #define AR5K_RF5112X_PD_PERIOD_A … #define AR5K_RF5112X_PD_PERIOD_B … #define AR5K_RF5112X_PD_PERIOD_XR … /* RFX112 (Derby 1) */ /* BANK 6 len pos col */ #define AR5K_RF5112_OB_2GHZ … #define AR5K_RF5112_DB_2GHZ … #define AR5K_RF5112_OB_5GHZ … #define AR5K_RF5112_DB_5GHZ … #define AR5K_RF5112_FIXED_BIAS_A … #define AR5K_RF5112_FIXED_BIAS_B … #define AR5K_RF5112_XPD_SEL … #define AR5K_RF5112_XPD_GAIN … /* Access to PWD registers */ #define AR5K_RF5112_PWD(_n) … static const struct ath5k_rf_reg rf_regs_5112[] = …; /* Default mode specific settings */ static const struct ath5k_ini_rfbuffer rfb_5112[] = …; /* RFX112A (Derby 2) */ /* BANK 6 len pos col */ #define AR5K_RF5112A_OB_2GHZ … #define AR5K_RF5112A_DB_2GHZ … #define AR5K_RF5112A_OB_5GHZ … #define AR5K_RF5112A_DB_5GHZ … #define AR5K_RF5112A_FIXED_BIAS_A … #define AR5K_RF5112A_FIXED_BIAS_B … #define AR5K_RF5112A_XPD_SEL … #define AR5K_RF5112A_PDGAINLO … #define AR5K_RF5112A_PDGAINHI … /* Access to PWD registers */ #define AR5K_RF5112A_PWD(_n) … /* Voltage regulators */ #define AR5K_RF5112A_HIGH_VC_CP … #define AR5K_RF5112A_MID_VC_CP … #define AR5K_RF5112A_LOW_VC_CP … #define AR5K_RF5112A_PUSH_UP … /* Power consumption */ #define AR5K_RF5112A_PAD2GND … #define AR5K_RF5112A_XB2_LVL … #define AR5K_RF5112A_XB5_LVL … static const struct ath5k_rf_reg rf_regs_5112a[] = …; /* Default mode specific settings */ static const struct ath5k_ini_rfbuffer rfb_5112a[] = …; /******************\ * RF2413 (Griffin) * \******************/ /* BANK 2 len pos col */ #define AR5K_RF2413_RF_TURBO … /* BANK 6 len pos col */ #define AR5K_RF2413_OB_2GHZ … #define AR5K_RF2413_DB_2GHZ … static const struct ath5k_rf_reg rf_regs_2413[] = …; /* Default mode specific settings * XXX: a/aTurbo ??? */ static const struct ath5k_ini_rfbuffer rfb_2413[] = …; /***************************\ * RF2315/RF2316 (Cobra SoC) * \***************************/ /* BANK 2 len pos col */ #define AR5K_RF2316_RF_TURBO … /* BANK 6 len pos col */ #define AR5K_RF2316_OB_2GHZ … #define AR5K_RF2316_DB_2GHZ … static const struct ath5k_rf_reg rf_regs_2316[] = …; /* Default mode specific settings */ static const struct ath5k_ini_rfbuffer rfb_2316[] = …; /******************************\ * RF5413/RF5424 (Eagle/Condor) * \******************************/ /* BANK 6 len pos col */ #define AR5K_RF5413_OB_2GHZ … #define AR5K_RF5413_DB_2GHZ … #define AR5K_RF5413_OB_5GHZ … #define AR5K_RF5413_DB_5GHZ … #define AR5K_RF5413_PWD_ICLOBUF2G … #define AR5K_RF5413_DERBY_CHAN_SEL_MODE … static const struct ath5k_rf_reg rf_regs_5413[] = …; /* Default mode specific settings */ static const struct ath5k_ini_rfbuffer rfb_5413[] = …; /***************************\ * RF2425/RF2417 (Swan/Nala) * * AR2317 (Spider SoC) * \***************************/ /* BANK 2 len pos col */ #define AR5K_RF2425_RF_TURBO … /* BANK 6 len pos col */ #define AR5K_RF2425_OB_2GHZ … #define AR5K_RF2425_DB_2GHZ … static const struct ath5k_rf_reg rf_regs_2425[] = …; /* Default mode specific settings */ static const struct ath5k_ini_rfbuffer rfb_2425[] = …; /* * TODO: Handle the few differences with swan during * bank modification and get rid of this */ static const struct ath5k_ini_rfbuffer rfb_2317[] = …; /* * TODO: Handle the few differences with swan during * bank modification and get rid of this */ static const struct ath5k_ini_rfbuffer rfb_2417[] = …;
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