/* * Copyright (c) 2010-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef AR9003_EEPROM_H #define AR9003_EEPROM_H #include <linux/types.h> #define AR9300_EEP_VER … #define AR9300_EEP_VER_MINOR_MASK … #define AR9300_EEP_MINOR_VER_1 … #define AR9300_EEP_MINOR_VER … /* 16-bit offset location start of calibration struct */ #define AR9300_EEP_START_LOC … #define AR9300_NUM_5G_CAL_PIERS … #define AR9300_NUM_2G_CAL_PIERS … #define AR9300_NUM_5G_20_TARGET_POWERS … #define AR9300_NUM_5G_40_TARGET_POWERS … #define AR9300_NUM_2G_CCK_TARGET_POWERS … #define AR9300_NUM_2G_20_TARGET_POWERS … #define AR9300_NUM_2G_40_TARGET_POWERS … /* #define AR9300_NUM_CTLS 21 */ #define AR9300_NUM_CTLS_5G … #define AR9300_NUM_CTLS_2G … #define AR9300_NUM_BAND_EDGES_5G … #define AR9300_NUM_BAND_EDGES_2G … #define AR9300_EEPMISC_WOW … #define AR9300_CUSTOMER_DATA_SIZE … #define AR9300_MAX_CHAINS … #define AR9300_ANT_16S … #define AR9300_FUTURE_MODAL_SZ … #define AR9300_PAPRD_RATE_MASK … #define AR9300_PAPRD_SCALE_1 … #define AR9300_PAPRD_SCALE_1_S … #define AR9300_PAPRD_SCALE_2 … #define AR9300_PAPRD_SCALE_2_S … #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE … /* Delta from which to start power to pdadc table */ /* This offset is used in both open loop and closed loop power control * schemes. In open loop power control, it is not really needed, but for * the "sake of consistency" it was kept. For certain AP designs, this * value is overwritten by the value in the flag "pwrTableOffset" just * before writing the pdadc vs pwr into the chip registers. */ #define AR9300_PWR_TABLE_OFFSET … /* Noise power data definitions * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET * (e.g. -25 = (-25/4 - 90) = -96.25 dBm) * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm * resolution (2 bits) is 0.25dBm */ #define NOISE_PWR_DATA_OFFSET … #define NOISE_PWR_DBM_2_INT(_p) … #define N2DBM(_p) … /* byte addressable */ #define AR9300_EEPROM_SIZE … #define AR9300_BASE_ADDR_4K … #define AR9300_BASE_ADDR … #define AR9300_BASE_ADDR_512 … /* AR5416_EEPMISC_BIG_ENDIAN not set indicates little endian */ #define AR9300_EEPMISC_LITTLE_ENDIAN … #define AR9300_OTP_BASE(_ah) … #define AR9300_OTP_STATUS(_ah) … #define AR9300_OTP_STATUS_TYPE … #define AR9300_OTP_STATUS_VALID … #define AR9300_OTP_STATUS_ACCESS_BUSY … #define AR9300_OTP_STATUS_SM_BUSY … #define AR9300_OTP_READ_DATA(_ah) … enum targetPowerHTRates { … }; enum targetPowerLegacyRates { … }; enum targetPowerCckRates { … }; enum ar9300_Rates { … }; struct eepFlags { … } __packed; enum CompressAlgorithm { … }; struct ar9300_base_eep_hdr { … } __packed; struct ar9300_modal_eep_header { … } __packed; struct ar9300_cal_data_per_freq_op_loop { … } __packed; struct cal_tgt_pow_legacy { … } __packed; struct cal_tgt_pow_ht { … } __packed; struct cal_ctl_data_2g { … } __packed; struct cal_ctl_data_5g { … } __packed; #define MAX_BASE_EXTENSION_FUTURE … struct ar9300_BaseExtension_1 { … } __packed; struct ar9300_BaseExtension_2 { … } __packed; struct ar9300_eeprom { … } __packed; s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz); u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz); u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz); u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz); u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz); unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, struct ath9k_channel *chan); void ar9003_hw_internal_regulator_apply(struct ath_hw *ah); int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray); #endif
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