/* * Copyright (c) 2008-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef EEPROM_H #define EEPROM_H #define AR_EEPROM_MODAL_SPURS … #include "../ath.h" #include <net/cfg80211.h> #include "ar9003_eeprom.h" /* helpers to swap EEPROM fields, which are stored as __le16 or __le32. Since * we are 100% sure about it we __force these to u16/u32 for the swab calls to * silence the sparse checks. These macros are used when we have a Big Endian * EEPROM (according to AR5416_EEPMISC_BIG_ENDIAN) and need to convert the * fields to __le16/__le32. */ #define EEPROM_FIELD_SWAB16(field) … #define EEPROM_FIELD_SWAB32(field) … #ifdef __BIG_ENDIAN #define AR5416_EEPROM_MAGIC … #else #define AR5416_EEPROM_MAGIC … #endif #define CTRY_DEBUG … #define CTRY_DEFAULT … #define AR_EEPROM_EEPCAP_COMPRESS_DIS … #define AR_EEPROM_EEPCAP_AES_DIS … #define AR_EEPROM_EEPCAP_FASTFRAME_DIS … #define AR_EEPROM_EEPCAP_BURST_DIS … #define AR_EEPROM_EEPCAP_MAXQCU … #define AR_EEPROM_EEPCAP_MAXQCU_S … #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN … #define AR_EEPROM_EEPCAP_KC_ENTRIES … #define AR_EEPROM_EEPCAP_KC_ENTRIES_S … #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND … #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN … #define AR_EEPROM_EEREGCAP_EN_KK_U2 … #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND … #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD … #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A … #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 … #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 … #define AR5416_EEPROM_MAGIC_OFFSET … #define AR5416_EEPROM_S … #define AR5416_EEPROM_OFFSET … #define AR5416_EEPROM_MAX … #define AR5416_EEPROM_START_ADDR(_ah) … #define SD_NO_CTL … #define NO_CTL … #define CTL_MODE_M … #define CTL_11A … #define CTL_11B … #define CTL_11G … #define CTL_2GHT20 … #define CTL_5GHT20 … #define CTL_2GHT40 … #define CTL_5GHT40 … #define EXT_ADDITIVE … #define CTL_11A_EXT … #define CTL_11G_EXT … #define CTL_11B_EXT … #define SUB_NUM_CTL_MODES_AT_5G_40 … #define SUB_NUM_CTL_MODES_AT_2G_40 … #define POWER_CORRECTION_FOR_TWO_CHAIN … #define POWER_CORRECTION_FOR_THREE_CHAIN … /* * For AR9285 and later chipsets, the following bits are not being programmed * in EEPROM and so need to be enabled always. * * Bit 0: en_fcc_mid * Bit 1: en_jap_mid * Bit 2: en_fcc_dfs_ht40 * Bit 3: en_jap_ht40 * Bit 4: en_jap_dfs_ht40 */ #define AR9285_RDEXT_DEFAULT … #define ATH9K_POW_SM(_r, _s) … #define FREQ2FBIN(x, y) … #define FBIN2FREQ(x, y) … #define ath9k_hw_use_flash(_ah) … #define OLC_FOR_AR9280_20_LATER(_ah) … #define OLC_FOR_AR9287_10_LATER(_ah) … #define EEP_RFSILENT_ENABLED … #define EEP_RFSILENT_ENABLED_S … #define EEP_RFSILENT_POLARITY … #define EEP_RFSILENT_POLARITY_S … #define EEP_RFSILENT_GPIO_SEL … #define EEP_RFSILENT_GPIO_SEL_S … #define AR5416_OPFLAGS_11A … #define AR5416_OPFLAGS_11G … #define AR5416_OPFLAGS_N_5G_HT40 … #define AR5416_OPFLAGS_N_2G_HT40 … #define AR5416_OPFLAGS_N_5G_HT20 … #define AR5416_OPFLAGS_N_2G_HT20 … #define AR5416_EEP_NO_BACK_VER … #define AR5416_EEP_VER … #define AR5416_EEP_VER_MAJOR_SHIFT … #define AR5416_EEP_VER_MAJOR_MASK … #define AR5416_EEP_VER_MINOR_MASK … #define AR5416_EEP_MINOR_VER_2 … #define AR5416_EEP_MINOR_VER_3 … #define AR5416_EEP_MINOR_VER_7 … #define AR5416_EEP_MINOR_VER_9 … #define AR5416_EEP_MINOR_VER_16 … #define AR5416_EEP_MINOR_VER_17 … #define AR5416_EEP_MINOR_VER_19 … #define AR5416_EEP_MINOR_VER_20 … #define AR5416_EEP_MINOR_VER_21 … #define AR5416_EEP_MINOR_VER_22 … #define AR5416_NUM_5G_CAL_PIERS … #define AR5416_NUM_2G_CAL_PIERS … #define AR5416_NUM_5G_20_TARGET_POWERS … #define AR5416_NUM_5G_40_TARGET_POWERS … #define AR5416_NUM_2G_CCK_TARGET_POWERS … #define AR5416_NUM_2G_20_TARGET_POWERS … #define AR5416_NUM_2G_40_TARGET_POWERS … #define AR5416_NUM_CTLS … #define AR5416_NUM_BAND_EDGES … #define AR5416_NUM_PD_GAINS … #define AR5416_PD_GAINS_IN_MASK … #define AR5416_PD_GAIN_ICEPTS … #define AR5416_NUM_PDADC_VALUES … #define AR5416_BCHAN_UNUSED … #define AR5416_MAX_PWR_RANGE_IN_HALF_DB … #define AR5416_MAX_CHAINS … #define AR9300_MAX_CHAINS … #define AR5416_PWR_TABLE_OFFSET_DB … /* Rx gain type values */ #define AR5416_EEP_RXGAIN_23DB_BACKOFF … #define AR5416_EEP_RXGAIN_13DB_BACKOFF … #define AR5416_EEP_RXGAIN_ORIG … /* Tx gain type values */ #define AR5416_EEP_TXGAIN_ORIGINAL … #define AR5416_EEP_TXGAIN_HIGH_POWER … /* Endianness of EEPROM content */ #define AR5416_EEPMISC_BIG_ENDIAN … #define AR5416_EEP4K_START_LOC … #define AR5416_EEP4K_NUM_2G_CAL_PIERS … #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS … #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS … #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS … #define AR5416_EEP4K_NUM_CTLS … #define AR5416_EEP4K_NUM_BAND_EDGES … #define AR5416_EEP4K_NUM_PD_GAINS … #define AR5416_EEP4K_MAX_CHAINS … #define AR9280_TX_GAIN_TABLE_SIZE … #define AR9287_EEP_VER … #define AR9287_EEP_MINOR_VER_1 … #define AR9287_EEP_MINOR_VER_2 … #define AR9287_EEP_MINOR_VER_3 … #define AR9287_EEP_MINOR_VER … #define AR9287_EEP_MINOR_VER_b … #define AR9287_EEP_NO_BACK_VER … #define AR9287_EEP_START_LOC … #define AR9287_HTC_EEP_START_LOC … #define AR9287_NUM_2G_CAL_PIERS … #define AR9287_NUM_2G_CCK_TARGET_POWERS … #define AR9287_NUM_2G_20_TARGET_POWERS … #define AR9287_NUM_2G_40_TARGET_POWERS … #define AR9287_NUM_CTLS … #define AR9287_NUM_BAND_EDGES … #define AR9287_PD_GAIN_ICEPTS … #define AR9287_EEPMISC_WOW … #define AR9287_MAX_CHAINS … #define AR9287_ANT_16S … #define AR9287_DATA_SZ … #define AR9287_PWR_TABLE_OFFSET_DB … #define AR9287_CHECKSUM_LOCATION … #define CTL_EDGE_TPOWER(_ctl) … #define CTL_EDGE_FLAGS(_ctl) … #define LNA_CTL_BUF_MODE … #define LNA_CTL_ISEL_LO … #define LNA_CTL_ISEL_HI … #define LNA_CTL_BUF_IN … #define LNA_CTL_FEM_BAND … #define LNA_CTL_LOCAL_BIAS … #define LNA_CTL_FORCE_XPA … #define LNA_CTL_USE_ANT1 … enum eeprom_param { … }; enum ar5416_rates { … }; enum ath9k_hal_freq_band { … }; struct base_eep_header { … } __packed; struct base_eep_header_4k { … } __packed; struct spur_chan { … } __packed; struct modal_eep_header { … } __packed; struct calDataPerFreqOpLoop { … } __packed; struct modal_eep_4k_header { … } __packed; struct base_eep_ar9287_header { … } __packed; struct modal_eep_ar9287_header { … } __packed; struct cal_data_per_freq { … } __packed; struct cal_data_per_freq_4k { … } __packed; struct cal_target_power_leg { … } __packed; struct cal_target_power_ht { … } __packed; struct cal_ctl_edges { … } __packed; struct cal_data_op_loop_ar9287 { … } __packed; struct cal_data_per_freq_ar9287 { … } __packed; cal_data_per_freq_ar9287_u __packed; struct cal_ctl_data_ar9287 { … } __packed; struct cal_ctl_data { … } __packed; struct cal_ctl_data_4k { … } __packed; struct ar5416_eeprom_def { … } __packed; struct ar5416_eeprom_4k { … } __packed; struct ar9287_eeprom { … } __packed; enum reg_ext_bitmap { … }; struct ath9k_country_entry { … }; struct eeprom_ops { … }; void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val); int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, int16_t targetLeft, int16_t targetRight); bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, u16 *indexL, u16 *indexR); bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size); bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size); bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev); void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, int eep_start_loc, int size); void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, u8 *pVpdList, u16 numIntercepts, u8 *pRetVpdList); void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, struct cal_target_power_leg *pNewPower, u16 numRates, bool isExtTarget); void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, struct cal_target_power_ht *pNewPower, u16 numRates, bool isHt40Target); u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, bool is2GHz, int num_band_edges); u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit, u8 antenna_reduction); void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); int ath9k_hw_eeprom_init(struct ath_hw *ah); void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, void *pRawDataSet, u8 *bChans, u16 availPiers, u16 tPdGainOverlap, u16 *pPdGainBoundaries, u8 *pPDADCValues, u16 numXpdGains); static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) { … } #define ar5416_get_ntxchains(_txchainmask) … extern const struct eeprom_ops eep_def_ops; extern const struct eeprom_ops eep_4k_ops; extern const struct eeprom_ops eep_ar9287_ops; extern const struct eeprom_ops eep_ar9287_ops; extern const struct eeprom_ops eep_ar9300_ops; #endif /* EEPROM_H */
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