/* * Copyright (c) 2015 Qualcomm Atheros Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef REG_MCI_H #define REG_MCI_H #define AR_MCI_COMMAND0 … #define AR_MCI_COMMAND0_HEADER … #define AR_MCI_COMMAND0_HEADER_S … #define AR_MCI_COMMAND0_LEN … #define AR_MCI_COMMAND0_LEN_S … #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP … #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S … #define AR_MCI_COMMAND1 … #define AR_MCI_COMMAND2 … #define AR_MCI_COMMAND2_RESET_TX … #define AR_MCI_COMMAND2_RESET_TX_S … #define AR_MCI_COMMAND2_RESET_RX … #define AR_MCI_COMMAND2_RESET_RX_S … #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES … #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S … #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP … #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S … #define AR_MCI_RX_CTRL … #define AR_MCI_TX_CTRL … /* * 0 = no division, * 1 = divide by 2, * 2 = divide by 4, * 3 = divide by 8 */ #define AR_MCI_TX_CTRL_CLK_DIV … #define AR_MCI_TX_CTRL_CLK_DIV_S … #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE … #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S … #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ … #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S … #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM … #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S … #define AR_MCI_MSG_ATTRIBUTES_TABLE … #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM … #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S … #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR … #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S … #define AR_MCI_SCHD_TABLE_0 … #define AR_MCI_SCHD_TABLE_1 … #define AR_MCI_GPM_0 … #define AR_MCI_GPM_1 … #define AR_MCI_GPM_WRITE_PTR … #define AR_MCI_GPM_WRITE_PTR_S … #define AR_MCI_GPM_BUF_LEN … #define AR_MCI_GPM_BUF_LEN_S … #define AR_MCI_INTERRUPT_RAW … #define AR_MCI_INTERRUPT_EN … #define AR_MCI_INTERRUPT_SW_MSG_DONE … #define AR_MCI_INTERRUPT_SW_MSG_DONE_S … #define AR_MCI_INTERRUPT_CPU_INT_MSG … #define AR_MCI_INTERRUPT_CPU_INT_MSG_S … #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL … #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S … #define AR_MCI_INTERRUPT_RX_INVALID_HDR … #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S … #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL … #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S … #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL … #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S … #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL … #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S … #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL … #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S … #define AR_MCI_INTERRUPT_RX_MSG … #define AR_MCI_INTERRUPT_RX_MSG_S … #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE … #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S … #define AR_MCI_INTERRUPT_BT_PRI … #define AR_MCI_INTERRUPT_BT_PRI_S … #define AR_MCI_INTERRUPT_BT_PRI_THRESH … #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S … #define AR_MCI_INTERRUPT_BT_FREQ … #define AR_MCI_INTERRUPT_BT_FREQ_S … #define AR_MCI_INTERRUPT_BT_STOMP … #define AR_MCI_INTERRUPT_BT_STOMP_S … #define AR_MCI_INTERRUPT_BB_AIC_IRQ … #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S … #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT … #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S … #define AR_MCI_REMOTE_CPU_INT … #define AR_MCI_REMOTE_CPU_INT_EN … #define AR_MCI_INTERRUPT_RX_MSG_RAW … #define AR_MCI_INTERRUPT_RX_MSG_EN … #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET … #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S … #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL … #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S … #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK … #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S … #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO … #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S … #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST … #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S … #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO … #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S … #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT … #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S … #define AR_MCI_INTERRUPT_RX_MSG_GPM … #define AR_MCI_INTERRUPT_RX_MSG_GPM_S … #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO … #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S … #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING … #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S … #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING … #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S … #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE … #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S … #define AR_MCI_CPU_INT … #define AR_MCI_RX_STATUS … #define AR_MCI_RX_LAST_SCHD_MSG_INDEX … #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S … #define AR_MCI_RX_REMOTE_SLEEP … #define AR_MCI_RX_REMOTE_SLEEP_S … #define AR_MCI_RX_MCI_CLK_REQ … #define AR_MCI_RX_MCI_CLK_REQ_S … #define AR_MCI_CONT_STATUS … #define AR_MCI_CONT_RSSI_POWER … #define AR_MCI_CONT_RSSI_POWER_S … #define AR_MCI_CONT_PRIORITY … #define AR_MCI_CONT_PRIORITY_S … #define AR_MCI_CONT_TXRX … #define AR_MCI_CONT_TXRX_S … #define AR_MCI_BT_PRI0 … #define AR_MCI_BT_PRI1 … #define AR_MCI_BT_PRI2 … #define AR_MCI_BT_PRI3 … #define AR_MCI_BT_PRI … #define AR_MCI_WL_FREQ0 … #define AR_MCI_WL_FREQ1 … #define AR_MCI_WL_FREQ2 … #define AR_MCI_GAIN … #define AR_MCI_WBTIMER1 … #define AR_MCI_WBTIMER2 … #define AR_MCI_WBTIMER3 … #define AR_MCI_WBTIMER4 … #define AR_MCI_MAXGAIN … #define AR_MCI_HW_SCHD_TBL_CTL … #define AR_MCI_HW_SCHD_TBL_D0 … #define AR_MCI_HW_SCHD_TBL_D1 … #define AR_MCI_HW_SCHD_TBL_D2 … #define AR_MCI_HW_SCHD_TBL_D3 … #define AR_MCI_TX_PAYLOAD0 … #define AR_MCI_TX_PAYLOAD1 … #define AR_MCI_TX_PAYLOAD2 … #define AR_MCI_TX_PAYLOAD3 … #define AR_BTCOEX_WBTIMER … #define AR_BTCOEX_CTRL … #define AR_BTCOEX_CTRL_AR9462_MODE … #define AR_BTCOEX_CTRL_AR9462_MODE_S … #define AR_BTCOEX_CTRL_WBTIMER_EN … #define AR_BTCOEX_CTRL_WBTIMER_EN_S … #define AR_BTCOEX_CTRL_MCI_MODE_EN … #define AR_BTCOEX_CTRL_MCI_MODE_EN_S … #define AR_BTCOEX_CTRL_LNA_SHARED … #define AR_BTCOEX_CTRL_LNA_SHARED_S … #define AR_BTCOEX_CTRL_PA_SHARED … #define AR_BTCOEX_CTRL_PA_SHARED_S … #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN … #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S … #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN … #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S … #define AR_BTCOEX_CTRL_NUM_ANTENNAS … #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S … #define AR_BTCOEX_CTRL_RX_CHAIN_MASK … #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S … #define AR_BTCOEX_CTRL_AGGR_THRESH … #define AR_BTCOEX_CTRL_AGGR_THRESH_S … #define AR_BTCOEX_CTRL_1_CHAIN_BCN … #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S … #define AR_BTCOEX_CTRL_1_CHAIN_ACK … #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S … #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN … #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S … #define AR_BTCOEX_CTRL_REDUCE_TXPWR … #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S … #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 … #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S … #define AR_BTCOEX_CTRL_SPDT_POLARITY … #define AR_BTCOEX_CTRL_SPDT_POLARITY_S … #define AR_BTCOEX_WL_WEIGHTS0 … #define AR_BTCOEX_WL_WEIGHTS1 … #define AR_BTCOEX_WL_WEIGHTS2 … #define AR_BTCOEX_WL_WEIGHTS3 … #define AR_BTCOEX_MAX_TXPWR(_x) … #define AR_BTCOEX_WL_LNA … #define AR_BTCOEX_RFGAIN_CTRL … #define AR_BTCOEX_WL_LNA_TIMEOUT … #define AR_BTCOEX_WL_LNA_TIMEOUT_S … #define AR_BTCOEX_CTRL2 … #define AR_BTCOEX_CTRL2_TXPWR_THRESH … #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S … #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK … #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S … #define AR_BTCOEX_CTRL2_RX_DEWEIGHT … #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S … #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL … #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S … #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL … #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S … #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE … #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S … #define AR_BTCOEX_CTRL_SPDT_ENABLE … #define AR_BTCOEX_CTRL_SPDT_ENABLE_S … #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL … #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S … #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT … #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S … #define AR_GLB_WLAN_UART_INTF_EN … #define AR_GLB_WLAN_UART_INTF_EN_S … #define AR_GLB_DS_JTAG_DISABLE … #define AR_GLB_DS_JTAG_DISABLE_S … #define AR_BTCOEX_RC … #define AR_BTCOEX_MAX_RFGAIN(_x) … #define AR_BTCOEX_DBG … #define AR_MCI_LAST_HW_MSG_HDR … #define AR_MCI_LAST_HW_MSG_BDY … #define AR_MCI_SCHD_TABLE_2 … #define AR_MCI_SCHD_TABLE_2_MEM_BASED … #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S … #define AR_MCI_SCHD_TABLE_2_HW_BASED … #define AR_MCI_SCHD_TABLE_2_HW_BASED_S … #define AR_BTCOEX_CTRL3 … #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT … #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S … #define AR_GLB_SWREG_DISCONT_MODE … #define AR_GLB_SWREG_DISCONT_EN_BT_WLAN … #define AR_MCI_MISC … #define AR_MCI_MISC_HW_FIX_EN … #define AR_MCI_MISC_HW_FIX_EN_S … #define AR_MCI_DBG_CNT_CTRL … #define AR_MCI_DBG_CNT_CTRL_ENABLE … #define AR_MCI_DBG_CNT_CTRL_ENABLE_S … #define AR_MCI_DBG_CNT_CTRL_BT_LINKID … #define AR_MCI_DBG_CNT_CTRL_BT_LINKID_S … #define MCI_STAT_ALL_BT_LINKID … #define AR_MCI_INTERRUPT_DEFAULT … #define AR_MCI_INTERRUPT_MSG_FAIL_MASK … #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK … #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT … #endif /* REG_MCI_H */
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