/* * Copyright (c) 2008-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef HW_H #define HW_H #include <linux/if_ether.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/firmware.h> #include "mac.h" #include "ani.h" #include "eeprom.h" #include "calib.h" #include "reg.h" #include "reg_mci.h" #include "phy.h" #include "btcoex.h" #include "dynack.h" #include "../regd.h" #define ATHEROS_VENDOR_ID … #define AR5416_DEVID_PCI … #define AR5416_DEVID_PCIE … #define AR9160_DEVID_PCI … #define AR9280_DEVID_PCI … #define AR9280_DEVID_PCIE … #define AR9285_DEVID_PCIE … #define AR2427_DEVID_PCIE … #define AR9287_DEVID_PCI … #define AR9287_DEVID_PCIE … #define AR9300_DEVID_PCIE … #define AR9300_DEVID_AR9340 … #define AR9300_DEVID_AR9485_PCIE … #define AR9300_DEVID_AR9580 … #define AR9300_DEVID_AR9462 … #define AR9300_DEVID_AR9330 … #define AR9300_DEVID_QCA955X … #define AR9485_DEVID_AR1111 … #define AR9300_DEVID_AR9565 … #define AR9300_DEVID_AR953X … #define AR9300_DEVID_QCA956X … #define AR5416_AR9100_DEVID … #define AR_SUBVENDOR_ID_NOG … #define AR_SUBVENDOR_ID_NEW_A … #define AR5416_MAGIC … #define AR9280_COEX2WIRE_SUBSYSID … #define AT9285_COEX3WIRE_SA_SUBSYSID … #define AT9285_COEX3WIRE_DA_SUBSYSID … #define ATH_AMPDU_LIMIT_MAX … #define ATH_DEFAULT_NOISE_FLOOR … #define ATH9K_RSSI_BAD … #define ATH9K_NUM_CHANNELS … /* Register read/write primitives */ #define REG_WRITE(_ah, _reg, _val) … #define REG_READ(_ah, _reg) … #define REG_READ_MULTI(_ah, _addr, _val, _cnt) … #define REG_RMW(_ah, _reg, _set, _clr) … #define ENABLE_REGWRITE_BUFFER(_ah) … #define REGWRITE_BUFFER_FLUSH(_ah) … #define ENABLE_REG_RMW_BUFFER(_ah) … #define REG_RMW_BUFFER_FLUSH(_ah) … #define PR_EEP(_s, _val) … #define SM(_v, _f) … #define MS(_v, _f) … #define REG_RMW_FIELD(_a, _r, _f, _v) … #define REG_READ_FIELD(_a, _r, _f) … #define REG_SET_BIT(_a, _r, _f) … #define REG_CLR_BIT(_a, _r, _f) … #define DO_DELAY(x) … #define REG_WRITE_ARRAY(iniarray, column, regWr) … #define REG_READ_ARRAY(ah, array, size) … #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT … #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED … #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED … #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME … #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL … #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED … #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED … #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA … #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK … #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA … #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK … #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX … #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX … #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX … #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX … #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE … #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA … #define AR_GPIOD_MASK … #define BASE_ACTIVATE_DELAY … #define RTC_PLL_SETTLE_DELAY … #define COEF_SCALE_S … #define HT40_CHANNEL_CENTER_SHIFT … #define ATH9K_ANTENNA0_CHAINMASK … #define ATH9K_ANTENNA1_CHAINMASK … #define ATH9K_NUM_DMA_DEBUG_REGS … #define ATH9K_NUM_QUEUES … #define MAX_RATE_POWER … #define MAX_COMBINED_POWER … #define AH_WAIT_TIMEOUT … #define AH_TSF_WRITE_TIMEOUT … #define AH_TIME_QUANTUM … #define AR_KEYTABLE_SIZE … #define POWER_UP_TIME … #define SPUR_RSSI_THRESH … #define UPPER_5G_SUB_BAND_START … #define MID_5G_SUB_BAND_START … #define CAB_TIMEOUT_VAL … #define BEACON_TIMEOUT_VAL … #define MIN_BEACON_TIMEOUT_VAL … #define SLEEP_SLOP … #define INIT_CONFIG_STATUS … #define INIT_RSSI_THR … #define INIT_BCON_CNTRL_REG … #define TU_TO_USEC(_tu) … #define ATH9K_HW_RX_HP_QDEPTH … #define ATH9K_HW_RX_LP_QDEPTH … #define PAPRD_GAIN_TABLE_ENTRIES … #define PAPRD_TABLE_SZ … #define PAPRD_IDEAL_AGC2_PWR_RANGE … /* * Wake on Wireless */ /* Keep Alive Frame */ #define KAL_FRAME_LEN … #define KAL_FRAME_TYPE … #define KAL_FRAME_SUB_TYPE … #define KAL_DURATION_ID … #define KAL_NUM_DATA_WORDS … #define KAL_NUM_DESC_WORDS … #define KAL_ANTENNA_MODE … #define KAL_TO_DS … #define KAL_DELAY … #define KAL_TIMEOUT … #define MAX_PATTERN_SIZE … #define MAX_PATTERN_MASK_SIZE … #define MAX_NUM_PATTERN … #define MAX_NUM_PATTERN_LEGACY … #define MAX_NUM_USER_PATTERN … /* * WoW trigger mapping to hardware code */ #define AH_WOW_USER_PATTERN_EN … #define AH_WOW_MAGIC_PATTERN_EN … #define AH_WOW_LINK_CHANGE … #define AH_WOW_BEACON_MISS … enum ath_hw_txq_subtype { … }; enum ath_ini_subsys { … }; enum ath9k_hw_caps { … }; /* * WoW device capabilities * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching * an exact user defined pattern or de-authentication/disassoc pattern. * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four * bytes of the pattern for user defined pattern, de-authentication and * disassociation patterns for all types of possible frames recieved * of those types. */ struct ath9k_hw_wow { … }; struct ath9k_hw_capabilities { … }; #define AR_NO_SPUR … #define AR_BASE_FREQ_2GHZ … #define AR_BASE_FREQ_5GHZ … #define AR_SPUR_FEEQ_BOUND_HT40 … #define AR_SPUR_FEEQ_BOUND_HT20 … enum ath9k_hw_hang_checks { … }; #define AR_PCIE_PLL_PWRSAVE_CONTROL … #define AR_PCIE_PLL_PWRSAVE_ON_D3 … #define AR_PCIE_PLL_PWRSAVE_ON_D0 … #define AR_PCIE_CDR_PWRSAVE_ON_D3 … #define AR_PCIE_CDR_PWRSAVE_ON_D0 … struct ath9k_ops_config { … }; enum ath9k_int { … }; #define MAX_RTT_TABLE_ENTRY … #define MAX_IQCAL_MEASUREMENT … #define MAX_CL_TAB_ENTRY … #define CL_TAB_ENTRY(reg_base) … enum ath9k_cal_flags { … }; struct ath9k_hw_cal_data { … }; struct ath9k_channel { … }; #define CHANNEL_5GHZ … #define CHANNEL_HALF … #define CHANNEL_QUARTER … #define CHANNEL_HT … #define CHANNEL_HT40PLUS … #define CHANNEL_HT40MINUS … #define IS_CHAN_5GHZ(_c) … #define IS_CHAN_2GHZ(_c) … #define IS_CHAN_HALF_RATE(_c) … #define IS_CHAN_QUARTER_RATE(_c) … #define IS_CHAN_A_FAST_CLOCK(_ah, _c) … #define IS_CHAN_HT(_c) … #define IS_CHAN_HT20(_c) … #define IS_CHAN_HT40(_c) … #define IS_CHAN_HT40PLUS(_c) … #define IS_CHAN_HT40MINUS(_c) … enum ath9k_power_mode { … }; enum ser_reg_mode { … }; enum ath9k_rx_qtype { … }; struct ath9k_beacon_state { … }; struct chan_centers { … }; enum { … }; struct ath9k_hw_version { … }; /* Generic TSF timer definitions */ #define ATH_MAX_GEN_TIMER … #define AR_GENTMR_BIT(_index) … struct ath_gen_timer_configuration { … }; struct ath_gen_timer { … }; struct ath_gen_timer_table { … }; struct ath_hw_antcomb_conf { … }; /** * struct ath_hw_radar_conf - radar detection initialization parameters * * @pulse_inband: threshold for checking the ratio of in-band power * to total power for short radar pulses (half dB steps) * @pulse_inband_step: threshold for checking an in-band power to total * power ratio increase for short radar pulses (half dB steps) * @pulse_height: threshold for detecting the beginning of a short * radar pulse (dB step) * @pulse_rssi: threshold for detecting if a short radar pulse is * gone (dB step) * @pulse_maxlen: maximum pulse length (0.8 us steps) * * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) * @radar_inband: threshold for checking the ratio of in-band power * to total power for long radar pulses (half dB steps) * @fir_power: threshold for detecting the end of a long radar pulse (dB) * * @ext_channel: enable extension channel radar detection */ struct ath_hw_radar_conf { … }; /** * struct ath_hw_private_ops - callbacks used internally by hardware code * * This structure contains private callbacks designed to only be used internally * by the hardware core. * * @init_cal_settings: setup types of calibrations supported * @init_cal: starts actual calibration * * @init_mode_gain_regs: Initialize TX/RX gain registers * * @rf_set_freq: change frequency * @spur_mitigate_freq: spur mitigation * @set_rf_regs: * @compute_pll_control: compute the PLL control value to use for * AR_RTC_PLL_CONTROL for a given channel * @setup_calibration: set up calibration * @iscal_supported: used to query if a type of calibration is supported * * @ani_cache_ini_regs: cache the values for ANI from the initial * register settings through the register initialization. */ struct ath_hw_private_ops { … }; /** * struct ath_spec_scan - parameters for Atheros spectral scan * * @enabled: enable/disable spectral scan * @short_repeat: controls whether the chip is in spectral scan mode * for 4 usec (enabled) or 204 usec (disabled) * @count: number of scan results requested. There are special meanings * in some chip revisions: * AR92xx: highest bit set (>=128) for endless mode * (spectral scan won't stopped until explicitly disabled) * AR9300 and newer: 0 for endless mode * @endless: true if endless mode is intended. Otherwise, count value is * corrected to the next possible value. * @period: time duration between successive spectral scan entry points * (period*256*Tclk). Tclk = ath_common->clockrate * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS * * Note: Tclk = 40MHz or 44MHz depending upon operating mode. * Typically it's 44MHz in 2/5GHz on later chips, but there's * a "fast clock" check for this in 5GHz. * */ struct ath_spec_scan { … }; /** * struct ath_hw_ops - callbacks used by hardware code and driver code * * This structure contains callbacks designed to be used internally by * hardware code and also by the lower level driver. * * @config_pci_powersave: * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC * * @spectral_scan_config: set parameters for spectral scan and enable/disable it * @spectral_scan_trigger: trigger a spectral scan run * @spectral_scan_wait: wait for a spectral scan run to finish */ struct ath_hw_ops { … }; struct ath_nf_limits { … }; enum ath_cal_list { … }; /* ah_flags */ #define AH_USE_EEPROM … #define AH_UNPLUGGED … #define AH_FASTCC … #define AH_NO_EEP_SWAP … struct ath_hw { … }; struct ath_bus_ops { … }; static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) { … } static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) { … } static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) { … } static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) { … } static inline u8 get_streams(int mask) { … } /* Initialization, Detach, Reset */ void ath9k_hw_deinit(struct ath_hw *ah); int ath9k_hw_init(struct ath_hw *ah); int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, bool fastcc); int ath9k_hw_fill_cap_info(struct ath_hw *ah); u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); /* GPIO / RFKILL / Antennae */ void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label); void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, u32 ah_signal_type); void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio); u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); /* General Operation */ void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, int hw_delay); bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, int column, unsigned int *writecnt); void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size); u32 ath9k_hw_reverse_bits(u32 val, u32 n); u16 ath9k_hw_computetxtime(struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, bool shortPreamble); void ath9k_hw_get_channel_centers(struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers); u32 ath9k_hw_getrxfilter(struct ath_hw *ah); void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); bool ath9k_hw_phy_disable(struct ath_hw *ah); bool ath9k_hw_disable(struct ath_hw *ah); void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); void ath9k_hw_setopmode(struct ath_hw *ah); void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); void ath9k_hw_write_associd(struct ath_hw *ah); u32 ath9k_hw_gettsf32(struct ath_hw *ah); u64 ath9k_hw_gettsf64(struct ath_hw *ah); void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); void ath9k_hw_reset_tsf(struct ath_hw *ah); u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur); void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); void ath9k_hw_init_global_settings(struct ath_hw *ah); u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs); void ath9k_hw_check_nav(struct ath_hw *ah); bool ath9k_hw_check_alive(struct ath_hw *ah); bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); /* Generic hw timer primitives */ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, void (*trigger)(void *), void (*overflow)(void *), void *arg, u8 timer_index); void ath9k_hw_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer, u32 timer_next, u32 timer_period); void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah); void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); void ath_gen_timer_isr(struct ath_hw *hw); void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); /* PHY */ void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent); void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, bool test); /* * Code Specific to AR5008, AR9001 or AR9002, * we stuff these here to avoid callbacks for AR9003. */ int ar9002_hw_rf_claim(struct ath_hw *ah); void ar9002_hw_enable_async_fifo(struct ath_hw *ah); /* * Code specific to AR9003, we stuff these here to avoid callbacks * for older families */ bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); void ar9003_hw_disable_phy_restart(struct ath_hw *ah); void ar9003_paprd_enable(struct ath_hw *ah, bool val); void ar9003_paprd_populate_single_table(struct ath_hw *ah, struct ath9k_hw_cal_data *caldata, int chain); int ar9003_paprd_create_curve(struct ath_hw *ah, struct ath9k_hw_cal_data *caldata, int chain); void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); int ar9003_paprd_init_table(struct ath_hw *ah); bool ar9003_paprd_is_done(struct ath_hw *ah); bool ar9003_is_paprd_enabled(struct ath_hw *ah); void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, struct ath9k_channel *chan); void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan, int bin); void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, struct ath9k_channel *chan, int ht40_delta); /* Hardware family op attach helpers */ int ar5008_hw_attach_phy_ops(struct ath_hw *ah); void ar9002_hw_attach_phy_ops(struct ath_hw *ah); void ar9003_hw_attach_phy_ops(struct ath_hw *ah); void ar9002_hw_attach_calib_ops(struct ath_hw *ah); void ar9003_hw_attach_calib_ops(struct ath_hw *ah); int ar9002_hw_attach_ops(struct ath_hw *ah); void ar9003_hw_attach_ops(struct ath_hw *ah); void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us); void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us); void ath9k_hw_setslottime(struct ath_hw *ah, u32 us); #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT void ar9003_hw_attach_aic_ops(struct ath_hw *ah); static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) { … } static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) { … } void ath9k_hw_btcoex_enable(struct ath_hw *ah); static inline enum ath_btcoex_scheme ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) { … } #else static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah) { } static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) { return false; } static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) { return false; } static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) { } static inline enum ath_btcoex_scheme ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) { return ATH_BTCOEX_CFG_NONE; } #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ #ifdef CONFIG_ATH9K_WOW int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, u8 *user_mask, int pattern_count, int pattern_len); u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); #else static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, u8 *user_mask, int pattern_count, int pattern_len) { return 0; } static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) { return 0; } static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) { } #endif #define ATH9K_CLOCK_RATE_CCK … #define ATH9K_CLOCK_RATE_5GHZ_OFDM … #define ATH9K_CLOCK_RATE_2GHZ_OFDM … #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM … #endif
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