/* * Copyright (c) 2010-2011 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef AR9003_PHY_H #define AR9003_PHY_H /* * Channel Register Map */ #define AR_CHAN_BASE … #define AR_PHY_TIMING1 … #define AR_PHY_TIMING2 … #define AR_PHY_TIMING3 … #define AR_PHY_TIMING4 … #define AR_PHY_TIMING5 … #define AR_PHY_TIMING6 … #define AR_PHY_TIMING11 … #define AR_PHY_SPUR_REG … #define AR_PHY_RX_IQCAL_CORR_B0 … #define AR_PHY_TX_IQCAL_CONTROL_3 … #define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT … #define AR_PHY_TIMING11_SPUR_FREQ_SD … #define AR_PHY_TIMING11_SPUR_FREQ_SD_S … #define AR_PHY_TIMING11_SPUR_DELTA_PHASE … #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S … #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC … #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S … #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR … #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S … #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT … #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S … #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM … #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S … #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH … #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S … #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI … #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S … #define AR_PHY_SPUR_REG_MASK_RATE_CNTL … #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S … #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN … #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S … #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN … #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S … #define AR_PHY_FIND_SIG_LOW … #define AR_PHY_SFCORR … #define AR_PHY_SFCORR_LOW … #define AR_PHY_SFCORR_EXT … #define AR_PHY_EXT_CCA … #define AR_PHY_RADAR_0 … #define AR_PHY_RADAR_1 … #define AR_PHY_RADAR_EXT … #define AR_PHY_MULTICHAIN_CTRL … #define AR_PHY_PERCHAIN_CSD … #define AR_PHY_TX_PHASE_RAMP_0 … #define AR_PHY_ADC_GAIN_DC_CORR_0 … #define AR_PHY_IQ_ADC_MEAS_0_B0 … #define AR_PHY_IQ_ADC_MEAS_1_B0 … #define AR_PHY_IQ_ADC_MEAS_2_B0 … #define AR_PHY_IQ_ADC_MEAS_3_B0 … /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */ #define AR_PHY_TX_PHASE_RAMP_0_9300_10 … #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 … #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 … #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 … #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 … #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 … #define AR_PHY_TX_CRC … #define AR_PHY_TST_DAC_CONST … #define AR_PHY_SPUR_REPORT_0 … #define AR_PHY_CHAN_INFO_TAB_0 … /* * Channel Field Definitions */ #define AR_PHY_TIMING2_USE_FORCE_PPM … #define AR_PHY_TIMING2_FORCE_PPM_VAL … #define AR_PHY_TIMING3_DSC_MAN … #define AR_PHY_TIMING3_DSC_MAN_S … #define AR_PHY_TIMING3_DSC_EXP … #define AR_PHY_TIMING3_DSC_EXP_S … #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX … #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S … #define AR_PHY_TIMING4_DO_CAL … #define AR_PHY_TIMING4_ENABLE_PILOT_MASK … #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S … #define AR_PHY_TIMING4_ENABLE_CHAN_MASK … #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S … #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER … #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S … #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI … #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S … #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE … #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE … #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW … #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW … #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S … #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW … #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S … #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW … #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S … #define AR_PHY_SFCORR_M2COUNT_THR … #define AR_PHY_SFCORR_M2COUNT_THR_S … #define AR_PHY_SFCORR_M1_THRESH … #define AR_PHY_SFCORR_M1_THRESH_S … #define AR_PHY_SFCORR_M2_THRESH … #define AR_PHY_SFCORR_M2_THRESH_S … #define AR_PHY_SFCORR_EXT_M1_THRESH … #define AR_PHY_SFCORR_EXT_M1_THRESH_S … #define AR_PHY_SFCORR_EXT_M2_THRESH … #define AR_PHY_SFCORR_EXT_M2_THRESH_S … #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW … #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S … #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW … #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S … #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD … #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S … #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S … #define AR_PHY_EXT_CCA_THRESH62 … #define AR_PHY_EXT_CCA_THRESH62_S … #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX … #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX_S … #define AR_PHY_EXT_MINCCA_PWR … #define AR_PHY_EXT_MINCCA_PWR_S … #define AR_PHY_EXT_CYCPWR_THR1 … #define AR_PHY_EXT_CYCPWR_THR1_S … #define AR_PHY_TIMING5_CYCPWR_THR1 … #define AR_PHY_TIMING5_CYCPWR_THR1_S … #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE … #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S … #define AR_PHY_TIMING5_CYCPWR_THR1A … #define AR_PHY_TIMING5_CYCPWR_THR1A_S … #define AR_PHY_TIMING5_RSSI_THR1A … #define AR_PHY_TIMING5_RSSI_THR1A_S … #define AR_PHY_TIMING5_RSSI_THR1A_ENA … #define AR_PHY_RADAR_0_ENA … #define AR_PHY_RADAR_0_FFT_ENA … #define AR_PHY_RADAR_0_INBAND … #define AR_PHY_RADAR_0_INBAND_S … #define AR_PHY_RADAR_0_PRSSI … #define AR_PHY_RADAR_0_PRSSI_S … #define AR_PHY_RADAR_0_HEIGHT … #define AR_PHY_RADAR_0_HEIGHT_S … #define AR_PHY_RADAR_0_RRSSI … #define AR_PHY_RADAR_0_RRSSI_S … #define AR_PHY_RADAR_0_FIRPWR … #define AR_PHY_RADAR_0_FIRPWR_S … #define AR_PHY_RADAR_1_RELPWR_ENA … #define AR_PHY_RADAR_1_USE_FIR128 … #define AR_PHY_RADAR_1_RELPWR_THRESH … #define AR_PHY_RADAR_1_RELPWR_THRESH_S … #define AR_PHY_RADAR_1_BLOCK_CHECK … #define AR_PHY_RADAR_1_MAX_RRSSI … #define AR_PHY_RADAR_1_RELSTEP_CHECK … #define AR_PHY_RADAR_1_RELSTEP_THRESH … #define AR_PHY_RADAR_1_RELSTEP_THRESH_S … #define AR_PHY_RADAR_1_MAXLEN … #define AR_PHY_RADAR_1_MAXLEN_S … #define AR_PHY_RADAR_EXT_ENA … #define AR_PHY_RADAR_DC_PWR_THRESH … #define AR_PHY_RADAR_DC_PWR_THRESH_S … #define AR_PHY_RADAR_LB_DC_CAP … #define AR_PHY_RADAR_LB_DC_CAP_S … #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW … #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S … #define AR_PHY_FIND_SIG_LOW_FIRPWR … #define AR_PHY_FIND_SIG_LOW_FIRPWR_S … #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT … #define AR_PHY_FIND_SIG_LOW_RELSTEP … #define AR_PHY_FIND_SIG_LOW_RELSTEP_S … #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT … #define AR_PHY_CHAN_INFO_TAB_S2_READ … #define AR_PHY_CHAN_INFO_TAB_S2_READ_S … #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF … #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S … #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF … #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S … #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE … #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF … #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S … #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF … #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S … /* * MRC Register Map */ #define AR_MRC_BASE … #define AR_PHY_TIMING_3A … #define AR_PHY_LDPC_CNTL1 … #define AR_PHY_LDPC_CNTL2 … #define AR_PHY_PILOT_SPUR_MASK … #define AR_PHY_CHAN_SPUR_MASK … #define AR_PHY_SGI_DELTA … #define AR_PHY_ML_CNTL_1 … #define AR_PHY_ML_CNTL_2 … #define AR_PHY_TST_ADC … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_S … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B … #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B_S … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_S … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B … #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B_S … /* * MRC Feild Definitions */ #define AR_PHY_SGI_DSC_MAN … #define AR_PHY_SGI_DSC_MAN_S … #define AR_PHY_SGI_DSC_EXP … #define AR_PHY_SGI_DSC_EXP_S … /* * BBB Register Map */ #define AR_BBB_BASE … /* * AGC Register Map */ #define AR_AGC_BASE … #define AR_PHY_SETTLING … #define AR_PHY_FORCEMAX_GAINS_0 … #define AR_PHY_GAINS_MINOFF0 … #define AR_PHY_DESIRED_SZ … #define AR_PHY_FIND_SIG … #define AR_PHY_AGC … #define AR_PHY_EXT_ATTEN_CTL_0 … #define AR_PHY_CCA_0 … #define AR_PHY_CCA_CTRL_0 … #define AR_PHY_RESTART … /* * Antenna Diversity settings */ #define AR_PHY_MC_GAIN_CTRL … #define AR_ANT_DIV_CTRL_ALL … #define AR_ANT_DIV_CTRL_ALL_S … #define AR_ANT_DIV_ENABLE … #define AR_ANT_DIV_ENABLE_S … #define AR_PHY_ANT_FAST_DIV_BIAS … #define AR_PHY_ANT_FAST_DIV_BIAS_S … #define AR_PHY_ANT_SW_RX_PROT … #define AR_PHY_ANT_SW_RX_PROT_S … #define AR_PHY_ANT_DIV_LNADIV … #define AR_PHY_ANT_DIV_LNADIV_S … #define AR_PHY_ANT_DIV_ALT_LNACONF … #define AR_PHY_ANT_DIV_ALT_LNACONF_S … #define AR_PHY_ANT_DIV_MAIN_LNACONF … #define AR_PHY_ANT_DIV_MAIN_LNACONF_S … #define AR_PHY_ANT_DIV_ALT_GAINTB … #define AR_PHY_ANT_DIV_ALT_GAINTB_S … #define AR_PHY_ANT_DIV_MAIN_GAINTB … #define AR_PHY_ANT_DIV_MAIN_GAINTB_S … #define AR_PHY_EXTCHN_PWRTHR1 … #define AR_PHY_EXT_CHN_WIN … #define AR_PHY_20_40_DET_THR … #define AR_PHY_RIFS_SRCH … #define AR_PHY_PEAK_DET_CTRL_1 … #define AR_PHY_PEAK_DET_CTRL_2 … #define AR_PHY_RX_GAIN_BOUNDS_1 … #define AR_PHY_RX_GAIN_BOUNDS_2 … #define AR_PHY_RSSI_0 … #define AR_PHY_SPUR_CCK_REP0 … #define AR_PHY_CCK_DETECT … #define AR_FAST_DIV_ENABLE … #define AR_FAST_DIV_ENABLE_S … #define AR_PHY_DAG_CTRLCCK … #define AR_PHY_IQCORR_CTRL_CCK … #define AR_PHY_CCK_SPUR_MIT … #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR … #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S … #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE … #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S … #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT … #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S … #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ … #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S … #define AR_PHY_MRC_CCK_CTRL … #define AR_PHY_MRC_CCK_ENABLE … #define AR_PHY_MRC_CCK_ENABLE_S … #define AR_PHY_MRC_CCK_MUX_REG … #define AR_PHY_MRC_CCK_MUX_REG_S … #define AR_PHY_RX_OCGAIN … #define AR_PHY_CCA_NOM_VAL_9300_2GHZ … #define AR_PHY_CCA_NOM_VAL_9300_5GHZ … #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ … #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ … #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ … #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ … #define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ … #define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ … #define AR_PHY_CCA_NOM_VAL_9462_2GHZ … #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ … #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ … #define AR_PHY_CCA_NOM_VAL_9462_5GHZ … #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ … #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ … #define AR_PHY_CCA_NOM_VAL_9330_2GHZ … #define AR9300_EXT_LNA_CTL_GPIO_AR9485 … /* * AGC Field Definitions */ #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN … #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S … #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN … #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S … #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN … #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S … #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN … #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S … #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN … #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S … #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB … #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S … #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB … #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S … #define AR_PHY_RXGAIN_TXRX_ATTEN … #define AR_PHY_RXGAIN_TXRX_ATTEN_S … #define AR_PHY_RXGAIN_TXRX_RF_MAX … #define AR_PHY_RXGAIN_TXRX_RF_MAX_S … #define AR9280_PHY_RXGAIN_TXRX_ATTEN … #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S … #define AR9280_PHY_RXGAIN_TXRX_MARGIN … #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S … #define AR_PHY_SETTLING_SWITCH … #define AR_PHY_SETTLING_SWITCH_S … #define AR_PHY_DESIRED_SZ_ADC … #define AR_PHY_DESIRED_SZ_ADC_S … #define AR_PHY_DESIRED_SZ_PGA … #define AR_PHY_DESIRED_SZ_PGA_S … #define AR_PHY_DESIRED_SZ_TOT_DES … #define AR_PHY_DESIRED_SZ_TOT_DES_S … #define AR_PHY_MINCCA_PWR … #define AR_PHY_MINCCA_PWR_S … #define AR_PHY_CCA_THRESH62 … #define AR_PHY_CCA_THRESH62_S … #define AR9280_PHY_MINCCA_PWR … #define AR9280_PHY_MINCCA_PWR_S … #define AR9280_PHY_CCA_THRESH62 … #define AR9280_PHY_CCA_THRESH62_S … #define AR_PHY_EXT_CCA0_THRESH62 … #define AR_PHY_EXT_CCA0_THRESH62_S … #define AR_PHY_EXT_CCA0_THRESH62_1 … #define AR_PHY_EXT_CCA0_THRESH62_1_S … #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK … #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S … #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME … #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S … #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV … #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR … #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S … #define AR_PHY_DAG_CTRLCCK_RSSI_THR … #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S … #define AR_PHY_RIFS_INIT_DELAY … #define AR_PHY_AGC_QUICK_DROP … #define AR_PHY_AGC_QUICK_DROP_S … #define AR_PHY_AGC_COARSE_LOW … #define AR_PHY_AGC_COARSE_LOW_S … #define AR_PHY_AGC_COARSE_HIGH … #define AR_PHY_AGC_COARSE_HIGH_S … #define AR_PHY_AGC_COARSE_PWR_CONST … #define AR_PHY_AGC_COARSE_PWR_CONST_S … #define AR_PHY_FIND_SIG_FIRSTEP … #define AR_PHY_FIND_SIG_FIRSTEP_S … #define AR_PHY_FIND_SIG_FIRPWR … #define AR_PHY_FIND_SIG_FIRPWR_S … #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT … #define AR_PHY_FIND_SIG_RELPWR … #define AR_PHY_FIND_SIG_RELPWR_S … #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT … #define AR_PHY_FIND_SIG_RELSTEP … #define AR_PHY_FIND_SIG_RELSTEP_S … #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT … #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG … #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S … #define AR_PHY_RESTART_DIV_GC … #define AR_PHY_RESTART_DIV_GC_S … #define AR_PHY_RESTART_ENA … #define AR_PHY_DC_RESTART_DIS … #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON … #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S … #define AR_PHY_TPC_OLPC_GAIN_DELTA … #define AR_PHY_TPC_OLPC_GAIN_DELTA_S … #define AR_PHY_TPC_6_ERROR_EST_MODE … #define AR_PHY_TPC_6_ERROR_EST_MODE_S … /* * SM Register Map */ #define AR_SM_BASE … #define AR_PHY_D2_CHIP_ID … #define AR_PHY_GEN_CTRL … #define AR_PHY_MODE … #define AR_PHY_ACTIVE … #define AR_PHY_SPUR_MASK_A(_ah) … #define AR_PHY_SPUR_MASK_B(_ah) … #define AR_PHY_SPECTRAL_SCAN … #define AR_PHY_RADAR_BW_FILTER … #define AR_PHY_SEARCH_START_DELAY … #define AR_PHY_MAX_RX_LEN … #define AR_PHY_FRAME_CTL … #define AR_PHY_RFBUS_REQ … #define AR_PHY_RFBUS_GRANT … #define AR_PHY_RIFS … #define AR_PHY_RX_CLR_DELAY … #define AR_PHY_RX_DELAY … #define AR_PHY_XPA_TIMING_CTL … #define AR_PHY_MISC_PA_CTL … #define AR_PHY_SWITCH_CHAIN_0 … #define AR_PHY_SWITCH_COM … #define AR_PHY_SWITCH_COM_2 … #define AR_PHY_RX_CHAINMASK … #define AR_PHY_CAL_CHAINMASK … #define AR_PHY_CALMODE … #define AR_PHY_FCAL_1 … #define AR_PHY_FCAL_2_0 … #define AR_PHY_DFT_TONE_CTL_0 … #define AR_PHY_CL_CAL_CTL … #define AR_PHY_CL_TAB_0 … #define AR_PHY_SYNTH_CONTROL … #define AR_PHY_ADDAC_CLK_SEL … #define AR_PHY_PLL_CTL … #define AR_PHY_ANALOG_SWAP … #define AR_PHY_ADDAC_PARA_CTL … #define AR_PHY_XPA_CFG … #define AR_PHY_FLC_PWR_THRESH … #define AR_PHY_FLC_PWR_THRESH_S … #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW … #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S … #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A … #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S … #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A … #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S … #define AR_PHY_TEST(_ah) … #define AR_PHY_TEST_BBB_OBS_SEL … #define AR_PHY_TEST_BBB_OBS_SEL_S … #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S … #define AR_PHY_TEST_RX_OBS_SEL_BIT5 … #define AR_PHY_TEST_CHAIN_SEL … #define AR_PHY_TEST_CHAIN_SEL_S … #define AR_PHY_TEST_CTL_STATUS(_ah) … #define AR_PHY_TEST_CTL_TSTDAC_EN … #define AR_PHY_TEST_CTL_TSTDAC_EN_S … #define AR_PHY_TEST_CTL_TX_OBS_SEL … #define AR_PHY_TEST_CTL_TX_OBS_SEL_S … #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL … #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S … #define AR_PHY_TEST_CTL_TSTADC_EN … #define AR_PHY_TEST_CTL_TSTADC_EN_S … #define AR_PHY_TEST_CTL_RX_OBS_SEL … #define AR_PHY_TEST_CTL_RX_OBS_SEL_S … #define AR_PHY_TEST_CTL_DEBUGPORT_SEL … #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S … #define AR_PHY_TSTDAC(_ah) … #define AR_PHY_CHAN_STATUS(_ah) … #define AR_PHY_CHAN_INFO_MEMORY(_ah) … #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ … #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S … #define AR_PHY_CHNINFO_NOISEPWR(_ah) … #define AR_PHY_CHNINFO_GAINDIFF(_ah) … #define AR_PHY_CHNINFO_FINETIM(_ah) … #define AR_PHY_CHAN_INFO_GAIN_0(_ah) … #define AR_PHY_SCRAMBLER_SEED(_ah) … #define AR_PHY_CCK_TX_CTRL(_ah) … #define AR_PHY_HEAVYCLIP_CTL(_ah) … #define AR_PHY_HEAVYCLIP_20 … #define AR_PHY_HEAVYCLIP_40 … #define AR_PHY_HEAVYCLIP_1 … #define AR_PHY_HEAVYCLIP_2 … #define AR_PHY_HEAVYCLIP_3 … #define AR_PHY_HEAVYCLIP_4 … #define AR_PHY_HEAVYCLIP_5 … #define AR_PHY_ILLEGAL_TXRATE … #define AR_PHY_POWER_TX_RATE(_d) … #define AR_PHY_PWRTX_MAX … #define AR_PHY_POWER_TX_SUB … #define AR_PHY_TPC_1 … #define AR_PHY_TPC_1_FORCED_DAC_GAIN … #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S … #define AR_PHY_TPC_1_FORCE_DAC_GAIN … #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S … #define AR_PHY_TPC_4_B0 … #define AR_PHY_TPC_5_B0 … #define AR_PHY_TPC_6_B0 … #define AR_PHY_TPC_11_B0 … #define AR_PHY_TPC_11_B1 … #define AR_PHY_TPC_11_B2 … #define AR_PHY_TPC_11_OLPC_GAIN_DELTA … #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S … #define AR_PHY_TPC_12 … #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 … #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S … #define AR_PHY_TPC_18 … #define AR_PHY_TPC_18_THERM_CAL_VALUE … #define AR_PHY_TPC_18_THERM_CAL_VALUE_S … #define AR_PHY_TPC_18_VOLT_CAL_VALUE … #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S … #define AR_PHY_TPC_19 … #define AR_PHY_TPC_19_ALPHA_VOLT … #define AR_PHY_TPC_19_ALPHA_VOLT_S … #define AR_PHY_TPC_19_ALPHA_THERM … #define AR_PHY_TPC_19_ALPHA_THERM_S … #define AR_PHY_TX_FORCED_GAIN … #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN … #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN … #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN … #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN … #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND … #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S … #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL … #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S … #define AR_PHY_PDADC_TAB_0 … #define AR_PHY_TXGAIN_TABLE … #define AR_PHY_TX_IQCAL_CONTROL_0(_ah) … #define AR_PHY_TX_IQCAL_CONTROL_1(_ah) … #define AR_PHY_TX_IQCAL_START(_ah) … #define AR_PHY_TX_IQCAL_STATUS_B0(_ah) … #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_ah, _i) … #define AR_PHY_RTT_CTRL … #define AR_PHY_WATCHDOG_STATUS … #define AR_PHY_WATCHDOG_CTL_1 … #define AR_PHY_WATCHDOG_CTL_2 … #define AR_PHY_WATCHDOG_CTL … #define AR_PHY_ONLY_WARMRESET … #define AR_PHY_ONLY_CTL … #define AR_PHY_ECO_CTRL … #define AR_PHY_BB_THERM_ADC_1 … #define AR_PHY_BB_THERM_ADC_1_INIT_THERM … #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S … #define AR_PHY_BB_THERM_ADC_3 … #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN … #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN_S … #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET … #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S … #define AR_PHY_BB_THERM_ADC_4 … #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE … #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S … #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE … #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S … #define AR_PHY_65NM_CH0_TXRF3 … #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G … #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S … #define AR_PHY_65NM_CH0_SYNTH4 … #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT … #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S … #define AR_PHY_65NM_CH0_SYNTH7 … #define AR_PHY_65NM_CH0_SYNTH12 … #define AR_PHY_65NM_CH0_BIAS1 … #define AR_PHY_65NM_CH0_BIAS2 … #define AR_PHY_65NM_CH0_BIAS4 … #define AR_PHY_65NM_CH0_RXTX2 … #define AR_PHY_65NM_CH1_RXTX2 … #define AR_PHY_65NM_CH2_RXTX2 … #define AR_PHY_65NM_CH0_RXTX4 … #define AR_PHY_65NM_CH1_RXTX4 … #define AR_PHY_65NM_CH2_RXTX4 … #define AR_PHY_65NM_CH0_BB1 … #define AR_PHY_65NM_CH0_BB2 … #define AR_PHY_65NM_CH0_BB3 … #define AR_PHY_65NM_CH1_BB1 … #define AR_PHY_65NM_CH1_BB2 … #define AR_PHY_65NM_CH1_BB3 … #define AR_PHY_65NM_CH2_BB1 … #define AR_PHY_65NM_CH2_BB2 … #define AR_PHY_65NM_CH2_BB3 … #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 … #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S … #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK … #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S … #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK … #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S … #define AR_CH0_TOP(_ah) … #define AR_CH0_TOP_XPABIASLVL … #define AR_CH0_TOP_XPABIASLVL_S … #define AR_SWITCH_TABLE_COM_ALL … #define AR_SWITCH_TABLE_COM_ALL_S … #define AR_SWITCH_TABLE_COM_AR9462_ALL … #define AR_SWITCH_TABLE_COM_AR9462_ALL_S … #define AR_SWITCH_TABLE_COM_AR9550_ALL … #define AR_SWITCH_TABLE_COM_AR9550_ALL_S … #define AR_SWITCH_TABLE_COM_SPDT … #define AR_SWITCH_TABLE_COM_SPDT_ALL … #define AR_SWITCH_TABLE_COM_SPDT_ALL_S … #define AR_SWITCH_TABLE_COM2_ALL … #define AR_SWITCH_TABLE_COM2_ALL_S … #define AR_SWITCH_TABLE_ALL … #define AR_SWITCH_TABLE_ALL_S … #define AR_CH0_THERM(_ah) … #define AR_CH0_THERM_XPABIASLVL_MSB … #define AR_CH0_THERM_XPABIASLVL_MSB_S … #define AR_CH0_THERM_XPASHORT2GND … #define AR_CH0_THERM_XPASHORT2GND_S … #define AR_CH0_THERM_LOCAL … #define AR_CH0_THERM_START … #define AR_CH0_THERM_SAR_ADC_OUT … #define AR_CH0_THERM_SAR_ADC_OUT_S … #define AR_CH0_TOP2(_ah) … #define AR_CH0_TOP2_XPABIASLVL … #define AR_CH0_TOP2_XPABIASLVL_S … #define AR_CH0_XTAL(_ah) … #define AR_CH0_XTAL_CAPINDAC … #define AR_CH0_XTAL_CAPINDAC_S … #define AR_CH0_XTAL_CAPOUTDAC … #define AR_CH0_XTAL_CAPOUTDAC_S … #define AR_PHY_PMU1(_ah) … #define AR_PHY_PMU1_PWD … #define AR_PHY_PMU1_PWD_S … #define AR_PHY_PMU2(_ah) … #define AR_PHY_PMU2_PGM … #define AR_PHY_PMU2_PGM_S … #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT … #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S … #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT … #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S … #define AR_PHY_LNAGAIN_LONG_SHIFT … #define AR_PHY_LNAGAIN_LONG_SHIFT_S … #define AR_PHY_MXRGAIN_LONG_SHIFT … #define AR_PHY_MXRGAIN_LONG_SHIFT_S … #define AR_PHY_VGAGAIN_LONG_SHIFT … #define AR_PHY_VGAGAIN_LONG_SHIFT_S … #define AR_PHY_SCFIR_GAIN_LONG_SHIFT … #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S … #define AR_PHY_MANRXGAIN_LONG_SHIFT … #define AR_PHY_MANRXGAIN_LONG_SHIFT_S … /* * SM Field Definitions */ #define AR_PHY_CL_CAL_ENABLE … #define AR_PHY_PARALLEL_CAL_ENABLE … #define AR_PHY_TPCRG1_PD_CAL_ENABLE … #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S … #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC … #define AR_PHY_FCAL20_CAP_STATUS_0 … #define AR_PHY_FCAL20_CAP_STATUS_0_S … #define AR_PHY_RFBUS_REQ_EN … #define AR_PHY_RFBUS_GRANT_EN … #define AR_PHY_GC_TURBO_MODE … #define AR_PHY_GC_TURBO_SHORT … #define AR_PHY_GC_DYN2040_EN … #define AR_PHY_GC_DYN2040_PRI_ONLY … #define AR_PHY_GC_DYN2040_PRI_CH … #define AR_PHY_GC_DYN2040_PRI_CH_S … #define AR_PHY_GC_DYN2040_EXT_CH … #define AR_PHY_GC_HT_EN … #define AR_PHY_GC_SHORT_GI_40 … #define AR_PHY_GC_WALSH … #define AR_PHY_GC_SINGLE_HT_LTF1 … #define AR_PHY_GC_GF_DETECT_EN … #define AR_PHY_GC_ENABLE_DAC_FIFO … #define AR_PHY_RX_DELAY_DELAY … #define AR_PHY_CALMODE_IQ … #define AR_PHY_CALMODE_ADC_GAIN … #define AR_PHY_CALMODE_ADC_DC_PER … #define AR_PHY_CALMODE_ADC_DC_INIT … #define AR_PHY_SWAP_ALT_CHAIN … #define AR_PHY_MODE_OFDM … #define AR_PHY_MODE_CCK … #define AR_PHY_MODE_DYNAMIC … #define AR_PHY_MODE_DYNAMIC_S … #define AR_PHY_MODE_HALF … #define AR_PHY_MODE_QUARTER … #define AR_PHY_MAC_CLK_MODE … #define AR_PHY_MODE_DYN_CCK_DISABLE … #define AR_PHY_MODE_SVD_HALF … #define AR_PHY_ACTIVE_EN … #define AR_PHY_ACTIVE_DIS … #define AR_PHY_FORCE_XPA_CFG … #define AR_PHY_FORCE_XPA_CFG_S … #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF … #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S … #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF … #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S … #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON … #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S … #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON … #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S … #define AR_PHY_TX_END_TO_A2_RX_ON … #define AR_PHY_TX_END_TO_A2_RX_ON_S … #define AR_PHY_TX_END_DATA_START … #define AR_PHY_TX_END_DATA_START_S … #define AR_PHY_TX_END_PA_ON … #define AR_PHY_TX_END_PA_ON_S … #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP … #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 … #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S … #define AR_PHY_TPCRG1_NUM_PD_GAIN … #define AR_PHY_TPCRG1_NUM_PD_GAIN_S … #define AR_PHY_TPCRG1_PD_GAIN_1 … #define AR_PHY_TPCRG1_PD_GAIN_1_S … #define AR_PHY_TPCRG1_PD_GAIN_2 … #define AR_PHY_TPCRG1_PD_GAIN_2_S … #define AR_PHY_TPCRG1_PD_GAIN_3 … #define AR_PHY_TPCRG1_PD_GAIN_3_S … #define AR_PHY_TPCGR1_FORCED_DAC_GAIN … #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S … #define AR_PHY_TPCGR1_FORCE_DAC_GAIN … #define AR_PHY_TXGAIN_FORCE … #define AR_PHY_TXGAIN_FORCE_S … #define AR_PHY_TXGAIN_FORCED_PADVGNRA … #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S … #define AR_PHY_TXGAIN_FORCED_PADVGNRB … #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S … #define AR_PHY_TXGAIN_FORCED_PADVGNRD … #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S … #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN … #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S … #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN … #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S … #define AR_PHY_POWER_TX_RATE_MAX … #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE … #define PHY_AGC_CLR … #define RFSILENT_BB … #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK … #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT … #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT … #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK … #define AR_PHY_RX_DELAY_DELAY … #define AR_PHY_CCK_TX_CTRL_JAPAN … #define AR_PHY_SPECTRAL_SCAN_ENABLE … #define AR_PHY_SPECTRAL_SCAN_ENABLE_S … #define AR_PHY_SPECTRAL_SCAN_ACTIVE … #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S … #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD … #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S … #define AR_PHY_SPECTRAL_SCAN_PERIOD … #define AR_PHY_SPECTRAL_SCAN_PERIOD_S … #define AR_PHY_SPECTRAL_SCAN_COUNT … #define AR_PHY_SPECTRAL_SCAN_COUNT_S … #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT … #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S … #define AR_PHY_SPECTRAL_SCAN_PRIORITY … #define AR_PHY_SPECTRAL_SCAN_PRIORITY_S … #define AR_PHY_SPECTRAL_SCAN_USE_ERR5 … #define AR_PHY_SPECTRAL_SCAN_USE_ERR5_S … #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT … #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT_S … #define AR_PHY_CHANNEL_STATUS_RX_CLEAR … #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION … #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S … #define AR_PHY_RTT_CTRL_RESTORE_MASK … #define AR_PHY_RTT_CTRL_RESTORE_MASK_S … #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE … #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S … #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS … #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S … #define AR_PHY_RTT_SW_RTT_TABLE_WRITE … #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S … #define AR_PHY_RTT_SW_RTT_TABLE_ADDR … #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S … #define AR_PHY_RTT_SW_RTT_TABLE_DATA … #define AR_PHY_RTT_SW_RTT_TABLE_DATA_S … #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL … #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S … #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT … #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S … #define AR_PHY_TX_IQCAL_START_DO_CAL … #define AR_PHY_TX_IQCAL_START_DO_CAL_S … #define AR_PHY_TX_IQCAL_STATUS_FAILED … #define AR_PHY_CALIBRATED_GAINS_0 … #define AR_PHY_CALIBRATED_GAINS_0_S … #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE … #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S … #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE … #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S … #define AR_PHY_65NM_CH0_RXTX4_THERM_ON … #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S … #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR … #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S … #define AR_PHY_65NM_RXTX4_XLNA_BIAS … #define AR_PHY_65NM_RXTX4_XLNA_BIAS_S … /* * Channel 1 Register Map */ #define AR_CHAN1_BASE … #define AR_PHY_EXT_CCA_1 … #define AR_PHY_TX_PHASE_RAMP_1 … #define AR_PHY_ADC_GAIN_DC_CORR_1 … #define AR_PHY_SPUR_REPORT_1 … #define AR_PHY_CHAN_INFO_TAB_1 … #define AR_PHY_RX_IQCAL_CORR_B1 … /* * Channel 1 Field Definitions */ #define AR_PHY_CH1_EXT_MINCCA_PWR … #define AR_PHY_CH1_EXT_MINCCA_PWR_S … /* * AGC 1 Register Map */ #define AR_AGC1_BASE … #define AR_PHY_FORCEMAX_GAINS_1 … #define AR_PHY_EXT_ATTEN_CTL_1 … #define AR_PHY_CCA_1 … #define AR_PHY_CCA_CTRL_1 … #define AR_PHY_RSSI_1 … #define AR_PHY_SPUR_CCK_REP_1 … #define AR_PHY_RX_OCGAIN_2 … /* * AGC 1 Field Definitions */ #define AR_PHY_CH1_MINCCA_PWR … #define AR_PHY_CH1_MINCCA_PWR_S … /* * SM 1 Register Map */ #define AR_SM1_BASE … #define AR_PHY_SWITCH_CHAIN_1 … #define AR_PHY_FCAL_2_1 … #define AR_PHY_DFT_TONE_CTL_1 … #define AR_PHY_CL_TAB_1 … #define AR_PHY_CHAN_INFO_GAIN_1 … #define AR_PHY_TPC_4_B1 … #define AR_PHY_TPC_5_B1 … #define AR_PHY_TPC_6_B1 … #define AR_PHY_TPC_11_B1 … #define AR_PHY_PDADC_TAB_1(_ah) … #define AR_PHY_TPC_19_B1 … #define AR_PHY_TPC_19_B1_ALPHA_THERM … #define AR_PHY_TPC_19_B1_ALPHA_THERM_S … #define AR_PHY_TX_IQCAL_STATUS_B1 … #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) … #define AR_PHY_RTT_TABLE_SW_INTF_B(i) … #define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) … /* * Channel 2 Register Map */ #define AR_CHAN2_BASE … #define AR_PHY_EXT_CCA_2 … #define AR_PHY_TX_PHASE_RAMP_2 … #define AR_PHY_ADC_GAIN_DC_CORR_2 … #define AR_PHY_SPUR_REPORT_2 … #define AR_PHY_CHAN_INFO_TAB_2 … #define AR_PHY_RX_IQCAL_CORR_B2 … /* * Channel 2 Field Definitions */ #define AR_PHY_CH2_EXT_MINCCA_PWR … #define AR_PHY_CH2_EXT_MINCCA_PWR_S … /* * AGC 2 Register Map */ #define AR_AGC2_BASE … #define AR_PHY_FORCEMAX_GAINS_2 … #define AR_PHY_EXT_ATTEN_CTL_2 … #define AR_PHY_CCA_2 … #define AR_PHY_CCA_CTRL_2 … #define AR_PHY_RSSI_2 … /* * AGC 2 Field Definitions */ #define AR_PHY_CH2_MINCCA_PWR … #define AR_PHY_CH2_MINCCA_PWR_S … /* * SM 2 Register Map */ #define AR_SM2_BASE … #define AR_PHY_SWITCH_CHAIN_2 … #define AR_PHY_FCAL_2_2 … #define AR_PHY_DFT_TONE_CTL_2 … #define AR_PHY_CL_TAB_2 … #define AR_PHY_CHAN_INFO_GAIN_2 … #define AR_PHY_TPC_4_B2 … #define AR_PHY_TPC_5_B2 … #define AR_PHY_TPC_6_B2 … #define AR_PHY_TPC_11_B2 … #define AR_PHY_TPC_19_B2 … #define AR_PHY_TX_IQCAL_STATUS_B2 … #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) … #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED … /* GLB Registers */ #define AR_GLB_BASE … #define AR_GLB_GPIO_CONTROL … #define AR_PHY_GLB_CONTROL … #define AR_GLB_SCRATCH(_ah) … #define AR_GLB_STATUS … /* * Misc helper defines */ #define AR_PHY_CHAIN_OFFSET … #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) … #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) … #define AR_PHY_SWITCH_CHAIN(_i) … #define AR_PHY_EXT_ATTEN_CTL(_i) … #define AR_PHY_RXGAIN(_i) … #define AR_PHY_TPCRG5(_i) … #define AR_PHY_PDADC_TAB(_i) … #define AR_PHY_CAL_MEAS_0(_i) … #define AR_PHY_CAL_MEAS_1(_i) … #define AR_PHY_CAL_MEAS_2(_i) … #define AR_PHY_CAL_MEAS_3(_i) … #define AR_PHY_CAL_MEAS_0_9300_10(_i) … #define AR_PHY_CAL_MEAS_1_9300_10(_i) … #define AR_PHY_CAL_MEAS_2_9300_10(_i) … #define AR_PHY_CAL_MEAS_3_9300_10(_i) … #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE … #define AR_PHY_WATCHDOG_IDLE_ENABLE … #define AR_PHY_WATCHDOG_IDLE_MASK … #define AR_PHY_WATCHDOG_NON_IDLE_MASK … #define AR_PHY_WATCHDOG_RST_ENABLE … #define AR_PHY_WATCHDOG_IRQ_ENABLE … #define AR_PHY_WATCHDOG_CNTL2_MASK … #define AR_PHY_WATCHDOG_INFO … #define AR_PHY_WATCHDOG_INFO_S … #define AR_PHY_WATCHDOG_DET_HANG … #define AR_PHY_WATCHDOG_DET_HANG_S … #define AR_PHY_WATCHDOG_RADAR_SM … #define AR_PHY_WATCHDOG_RADAR_SM_S … #define AR_PHY_WATCHDOG_RX_OFDM_SM … #define AR_PHY_WATCHDOG_RX_OFDM_SM_S … #define AR_PHY_WATCHDOG_RX_CCK_SM … #define AR_PHY_WATCHDOG_RX_CCK_SM_S … #define AR_PHY_WATCHDOG_TX_OFDM_SM … #define AR_PHY_WATCHDOG_TX_OFDM_SM_S … #define AR_PHY_WATCHDOG_TX_CCK_SM … #define AR_PHY_WATCHDOG_TX_CCK_SM_S … #define AR_PHY_WATCHDOG_AGC_SM … #define AR_PHY_WATCHDOG_AGC_SM_S … #define AR_PHY_WATCHDOG_SRCH_SM … #define AR_PHY_WATCHDOG_SRCH_SM_S … #define AR_PHY_WATCHDOG_STATUS_CLR … /* * PAPRD registers */ #define AR_PHY_XPA_TIMING_CTL … #define AR_PHY_PAPRD_AM2AM … #define AR_PHY_PAPRD_AM2AM_MASK … #define AR_PHY_PAPRD_AM2AM_MASK_S … #define AR_PHY_PAPRD_AM2PM … #define AR_PHY_PAPRD_AM2PM_MASK … #define AR_PHY_PAPRD_AM2PM_MASK_S … #define AR_PHY_PAPRD_HT40 … #define AR_PHY_PAPRD_HT40_MASK … #define AR_PHY_PAPRD_HT40_MASK_S … #define AR_PHY_PAPRD_CTRL0_B0 … #define AR_PHY_PAPRD_CTRL0_B1 … #define AR_PHY_PAPRD_CTRL0_B2 … #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE … #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S … #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK … #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S … #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH … #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S … #define AR_PHY_PAPRD_CTRL1_B0 … #define AR_PHY_PAPRD_CTRL1_B1 … #define AR_PHY_PAPRD_CTRL1_B2 … #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA … #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S … #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE … #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S … #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE … #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S … #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL … #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S … #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK … #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S … #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT … #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S … #define AR_PHY_PAPRD_TRAINER_CNTL1(_ah) … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP … #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S … #define AR_PHY_PAPRD_TRAINER_CNTL2(_ah) … #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN … #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S … #define AR_PHY_PAPRD_TRAINER_CNTL3(_ah) … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE … #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S … #define AR_PHY_PAPRD_TRAINER_CNTL4(_ah) … #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES … #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S … #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA … #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S … #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR … #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S … #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 … #define AR_PHY_PAPRD_PRE_POST_SCALING … #define AR_PHY_PAPRD_PRE_POST_SCALING_S … #define AR_PHY_PAPRD_TRAINER_STAT1(_ah) … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR … #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S … #define AR_PHY_PAPRD_TRAINER_STAT2(_ah) … #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL … #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S … #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX … #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S … #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX … #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S … #define AR_PHY_PAPRD_TRAINER_STAT3(_ah) … #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT … #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S … #define AR_PHY_PAPRD_MEM_TAB_B0 … #define AR_PHY_PAPRD_MEM_TAB_B1 … #define AR_PHY_PAPRD_MEM_TAB_B2 … #define AR_PHY_PA_GAIN123_B0 … #define AR_PHY_PA_GAIN123_B1 … #define AR_PHY_PA_GAIN123_B2 … #define AR_PHY_PA_GAIN123_PA_GAIN1 … #define AR_PHY_PA_GAIN123_PA_GAIN1_S … #define AR_PHY_POWERTX_RATE5 … #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 … #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S … #define AR_PHY_POWERTX_RATE6 … #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 … #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S … #define AR_PHY_POWERTX_RATE8 … #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 … #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S … #define AR_PHY_CL_TAB_CL_GAIN_MOD … #define AR_PHY_CL_TAB_CL_GAIN_MOD_S … #define AR_BTCOEX_WL_LNADIV … #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD … #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S … #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY … #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S … #define AR_BTCOEX_WL_LNADIV_FORCE_ON … #define AR_BTCOEX_WL_LNADIV_FORCE_ON_S … #define AR_BTCOEX_WL_LNADIV_MODE_OPTION … #define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S … #define AR_BTCOEX_WL_LNADIV_MODE … #define AR_BTCOEX_WL_LNADIV_MODE_S … #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ … #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S … #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE … #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S … #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT … #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S … #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD … #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S … /* Manual Peak detector calibration */ #define AR_PHY_65NM_BASE … #define AR_PHY_65NM_RXRF_GAINSTAGES(i) … #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE … #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE_S … #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC … #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC_S … #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR … #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_S … #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR … #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_S … #define AR_PHY_65NM_RXTX2(i) … #define AR_PHY_65NM_RXTX2_RXON_OVR … #define AR_PHY_65NM_RXTX2_RXON_OVR_S … #define AR_PHY_65NM_RXTX2_RXON … #define AR_PHY_65NM_RXTX2_RXON_S … #define AR_PHY_65NM_RXRF_AGC(i) … #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE … #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE_S … #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR … #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR_S … #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR … #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR_S … #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR … #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR_S … #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR … #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR_S … #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR … #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR_S … #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR … #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR_S … #define AR_PHY_65NM_RXRF_AGC_AGC_OUT … #define AR_PHY_65NM_RXRF_AGC_AGC_OUT_S … #define AR9300_DFS_FIRPWR … #endif /* AR9003_PHY_H */
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