/* * Copyright (c) 2010-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include <linux/export.h> #include "hw.h" #include "ar9003_phy.h" #include "ar9003_eeprom.h" #define AR9300_OFDM_RATES … #define AR9300_HT_SS_RATES … #define AR9300_HT_DS_RATES … #define AR9300_HT_TS_RATES … #define AR9300_11NA_OFDM_SHIFT … #define AR9300_11NA_HT_SS_SHIFT … #define AR9300_11NA_HT_DS_SHIFT … #define AR9300_11NA_HT_TS_SHIFT … #define AR9300_11NG_OFDM_SHIFT … #define AR9300_11NG_HT_SS_SHIFT … #define AR9300_11NG_HT_DS_SHIFT … #define AR9300_11NG_HT_TS_SHIFT … static const int firstep_table[] = …/* level: 0 1 2 3 4 5 6 7 8 */ { … }; /* lvl 0-8, default 2 */ static const int cycpwrThr1_table[] = …/* level: 0 1 2 3 4 5 6 7 8 */ { … }; /* lvl 0-7, default 3 */ /* * register values to turn OFDM weak signal detection OFF */ static const int m1ThreshLow_off = …; static const int m2ThreshLow_off = …; static const int m1Thresh_off = …; static const int m2Thresh_off = …; static const int m2CountThr_off = …; static const int m2CountThrLow_off = …; static const int m1ThreshLowExt_off = …; static const int m2ThreshLowExt_off = …; static const int m1ThreshExt_off = …; static const int m2ThreshExt_off = …; static const u8 ofdm2pwr[] = …; static const u8 mcs2pwr_ht20[] = …; static const u8 mcs2pwr_ht40[] = …; /** * ar9003_hw_set_channel - set channel on single-chip device * @ah: atheros hardware structure * @chan: * * This is the function to change channel on single-chip devices, that is * for AR9300 family of chipsets. * * This function takes the channel value in MHz and sets * hardware channel value. Assumes writes have been enabled to analog bus. * * Actual Expression, * * For 2GHz channel, * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) * * For 5GHz channel, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) * (freq_ref = 40MHz/(24>>amodeRefSel)) * * For 5GHz channels which are 5MHz spaced, * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) * (freq_ref = 40MHz) */ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { … } /** * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency * @ah: atheros hardware structure * @chan: * * For single-chip solutions. Converts to baseband spur frequency given the * input channel frequency and compute register settings below. * * Spur mitigation for MRC CCK */ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, struct ath9k_channel *chan) { … } /* Clean all spur register fields */ static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) { … } static void ar9003_hw_spur_ofdm(struct ath_hw *ah, int freq_offset, int spur_freq_sd, int spur_delta_phase, int spur_subchannel_sd, int range, int synth_freq) { … } static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, int freq_offset) { … } static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, struct ath9k_channel *chan, int freq_offset, int range, int synth_freq) { … } /* Spur mitigation for OFDM */ static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, struct ath9k_channel *chan) { … } static void ar9003_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) { … } static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, struct ath9k_channel *chan) { … } static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, struct ath9k_channel *chan) { … } static void ar9003_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan) { … } static void ar9003_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan) { … } void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) { … } /* * Override INI values with chip specific configuration. */ static void ar9003_hw_override_ini(struct ath_hw *ah) { … } static void ar9003_hw_prog_ini(struct ath_hw *ah, struct ar5416IniArray *iniArr, int column) { … } static u32 ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, struct ath9k_channel *chan) { … } static u32 ar9561_hw_get_modes_txgain_index(struct ath_hw *ah, struct ath9k_channel *chan) { … } static void ar9003_doubler_fix(struct ath_hw *ah) { … } static int ar9003_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan) { … } static void ar9003_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) { … } static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) { … } static void ar9003_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan) { … } static bool ar9003_hw_rfbus_req(struct ath_hw *ah) { … } /* * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). * Read the phy active delay register. Value is in 100ns increments. */ static void ar9003_hw_rfbus_done(struct ath_hw *ah) { … } static bool ar9003_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param) { … } static void ar9003_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]) { … } static void ar9003_hw_set_nf_limits(struct ath_hw *ah) { … } /* * Initialize the ANI register values with default (ini) values. * This routine is called during a (full) hardware reset after * all the registers are initialised from the INI. */ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) { … } static void ar9003_hw_set_radar_params(struct ath_hw *ah, struct ath_hw_radar_conf *conf) { … } static void ar9003_hw_set_radar_conf(struct ath_hw *ah) { … } static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf) { … } static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf) { … } #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) { … } #endif static int ar9003_hw_fast_chan_change(struct ath_hw *ah, struct ath9k_channel *chan, u8 *ini_reloaded) { … } static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, struct ath_spec_scan *param) { … } static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) { … } static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) { … } static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) { … } static void ar9003_hw_tx99_stop(struct ath_hw *ah) { … } static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) { … } static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) { … } static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, int offset) { … } static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, int ss_offset, int ds_offset, int ts_offset, bool is_40) { … } static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, int ds_offset, int ts_offset) { … } void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, struct ath9k_channel *chan) { … } void ar9003_hw_attach_phy_ops(struct ath_hw *ah) { … } /* * Baseband Watchdog signatures: * * 0x04000539: BB hang when operating in HT40 DFS Channel. * Full chip reset is not required, but a recovery * mechanism is needed. * * 0x1300000a: Related to CAC deafness. * Chip reset is not required. * * 0x0400000a: Related to CAC deafness. * Full chip reset is required. * * 0x04000b09: RX state machine gets into an illegal state * when a packet with unsupported rate is received. * Full chip reset is required and PHY_RESTART has * to be disabled. * * 0x04000409: Packet stuck on receive. * Full chip reset is required for all chips except * AR9340, AR9531 and AR9561. */ /* * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required. */ bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) { … } EXPORT_SYMBOL(…); void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) { … } void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) { … } void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) { … } EXPORT_SYMBOL(…); void ar9003_hw_disable_phy_restart(struct ath_hw *ah) { … } EXPORT_SYMBOL(…);
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