linux/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef INITVALS_9462_2P0_H
#define INITVALS_9462_2P0_H

/* AR9462 2.0 */

#define ar9462_2p0_mac_postamble

#define ar9462_2p0_common_wo_xlna_rx_gain

#define ar9462_2p0_common_5g_xlna_only_rxgain

#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484

static const u32 ar9462_2p0_modes_fast_clock[][3] =;

static const u32 ar9462_2p0_baseband_postamble[][5] =;

static const u32 ar9462_2p0_common_rx_gain[][2] =;

static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] =;

static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] =;

static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] =;

static const u32 ar9462_2p0_soc_postamble[][5] =;

static const u32 ar9462_2p0_baseband_core[][2] =;

static const u32 ar9462_2p0_radio_postamble[][5] =;

static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] =;

static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] =;

static const u32 ar9462_2p0_radio_core[][2] =;

static const u32 ar9462_2p0_soc_preamble[][2] =;

static const u32 ar9462_2p0_mac_core[][2] =;

static const u32 ar9462_2p0_common_mixed_rx_gain[][2] =;

static const u32 ar9462_2p0_baseband_postamble_5g_xlna[][5] =;

static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] =;

static const u32 ar9462_2p0_baseband_postamble_mix_rxgain[][5] =;

#endif /* INITVALS_9462_2P0_H */