#ifndef INITVALS_9462_2P0_H
#define INITVALS_9462_2P0_H
#define ar9462_2p0_mac_postamble …
#define ar9462_2p0_common_wo_xlna_rx_gain …
#define ar9462_2p0_common_5g_xlna_only_rxgain …
#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 …
static const u32 ar9462_2p0_modes_fast_clock[][3] = …;
static const u32 ar9462_2p0_baseband_postamble[][5] = …;
static const u32 ar9462_2p0_common_rx_gain[][2] = …;
static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = …;
static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = …;
static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = …;
static const u32 ar9462_2p0_soc_postamble[][5] = …;
static const u32 ar9462_2p0_baseband_core[][2] = …;
static const u32 ar9462_2p0_radio_postamble[][5] = …;
static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = …;
static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = …;
static const u32 ar9462_2p0_radio_core[][2] = …;
static const u32 ar9462_2p0_soc_preamble[][2] = …;
static const u32 ar9462_2p0_mac_core[][2] = …;
static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = …;
static const u32 ar9462_2p0_baseband_postamble_5g_xlna[][5] = …;
static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = …;
static const u32 ar9462_2p0_baseband_postamble_mix_rxgain[][5] = …;
#endif