/* * Copyright (c) 2010-2011 Atheros Communications Inc. * Copyright (c) 2011-2012 Qualcomm Atheros Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef INITVALS_9565_1P0_H #define INITVALS_9565_1P0_H /* AR9565 1.0 */ #define ar9565_1p0_mac_postamble … #define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table … #define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 … static const u32 ar9565_1p0_mac_core[][2] = …; static const u32 ar9565_1p0_baseband_core[][2] = …; static const u32 ar9565_1p0_baseband_postamble[][5] = …; static const u32 ar9565_1p0_radio_core[][2] = …; static const u32 ar9565_1p0_radio_postamble[][5] = …; static const u32 ar9565_1p0_soc_preamble[][2] = …; static const u32 ar9565_1p0_soc_postamble[][5] = …; static const u32 ar9565_1p0_Common_rx_gain_table[][2] = …; static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = …; static const u32 ar9565_1p0_modes_fast_clock[][3] = …; static const u32 ar9565_1p0_common_wo_xlna_rx_gain_table[][2] = …; static const u32 ar9565_1p0_modes_low_ob_db_tx_gain_table[][5] = …; static const u32 ar9565_1p0_modes_high_ob_db_tx_gain_table[][5] = …; static const u32 ar9565_1p0_modes_high_power_tx_gain_table[][5] = …; #endif /* INITVALS_9565_1P0_H */
Codebase Browser
linux