/* * Copyright (c) 2008-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include "hw.h" #include "ar9003_mac.h" #include "ar9003_2p2_initvals.h" #include "ar9003_buffalo_initvals.h" #include "ar9485_initvals.h" #include "ar9340_initvals.h" #include "ar9330_1p1_initvals.h" #include "ar9330_1p2_initvals.h" #include "ar955x_1p0_initvals.h" #include "ar9580_1p0_initvals.h" #include "ar9462_2p0_initvals.h" #include "ar9462_2p1_initvals.h" #include "ar9565_1p0_initvals.h" #include "ar9565_1p1_initvals.h" #include "ar953x_initvals.h" #include "ar956x_initvals.h" /* General hardware code for the AR9003 hadware family */ /* * The AR9003 family uses a new INI format (pre, core, post * arrays per subsystem). This provides support for the * AR9003 2.2 chipsets. */ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode6(struct ath_hw *ah) { … } static void ar9003_tx_gain_table_mode7(struct ath_hw *ah) { … } ath_txgain_tab; static void ar9003_tx_gain_table_apply(struct ath_hw *ah) { … } static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) { … } static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) { … } static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) { … } static void ar9003_rx_gain_table_mode3(struct ath_hw *ah) { … } static void ar9003_rx_gain_table_apply(struct ath_hw *ah) { … } /* set gain table pointers according to values read from the eeprom */ static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) { … } /* * Helper for ASPM support. * * Disable PLL when in L0s as well as receiver clock when in L1. * This power saving option must be enabled through the SerDes. * * Programming the SerDes must go through the same 288 bit serial shift * register as the other analog registers. Hence the 9 writes. */ static void ar9003_hw_configpcipowersave(struct ath_hw *ah, bool power_off) { … } static void ar9003_hw_init_hang_checks(struct ath_hw *ah) { … } /* * MAC HW hang check * ================= * * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1. * * The state of each DCU chain (mapped to TX queues) is available from these * DMA debug registers: * * Chain 0 state : Bits 4:0 of AR_DMADBG_4 * Chain 1 state : Bits 9:5 of AR_DMADBG_4 * Chain 2 state : Bits 14:10 of AR_DMADBG_4 * Chain 3 state : Bits 19:15 of AR_DMADBG_4 * Chain 4 state : Bits 24:20 of AR_DMADBG_4 * Chain 5 state : Bits 29:25 of AR_DMADBG_4 * Chain 6 state : Bits 4:0 of AR_DMADBG_5 * Chain 7 state : Bits 9:5 of AR_DMADBG_5 * Chain 8 state : Bits 14:10 of AR_DMADBG_5 * Chain 9 state : Bits 19:15 of AR_DMADBG_5 * * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done. */ #define NUM_STATUS_READS … static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue) { … } static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) { … } /* Sets up the AR9003 hardware familiy callbacks */ void ar9003_hw_attach_ops(struct ath_hw *ah) { … }
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