/* * Copyright (c) 2015 Qualcomm Atheros Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef REG_AIC_H #define REG_AIC_H #define AR_PHY_AIC_CTRL_0_B0 … #define AR_PHY_AIC_CTRL_1_B0 … #define AR_PHY_AIC_CTRL_2_B0 … #define AR_PHY_AIC_CTRL_3_B0 … #define AR_PHY_AIC_CTRL_4_B0 … #define AR_PHY_AIC_STAT_0_B0 … #define AR_PHY_AIC_STAT_1_B0 … #define AR_PHY_AIC_STAT_2_B0 … #define AR_PHY_AIC_CTRL_0_B1 … #define AR_PHY_AIC_CTRL_1_B1 … #define AR_PHY_AIC_CTRL_4_B1 … #define AR_PHY_AIC_STAT_0_B1 … #define AR_PHY_AIC_STAT_1_B1 … #define AR_PHY_AIC_STAT_2_B1 … #define AR_PHY_AIC_SRAM_ADDR_B0 … #define AR_PHY_AIC_SRAM_DATA_B0 … #define AR_PHY_AIC_SRAM_ADDR_B1 … #define AR_PHY_AIC_SRAM_DATA_B1 … #define AR_PHY_BT_COEX_4 … #define AR_PHY_BT_COEX_5 … /* AIC fields */ #define AR_PHY_AIC_MON_ENABLE … #define AR_PHY_AIC_MON_ENABLE_S … #define AR_PHY_AIC_CAL_MAX_HOP_COUNT … #define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S … #define AR_PHY_AIC_CAL_MIN_VALID_COUNT … #define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S … #define AR_PHY_AIC_F_WLAN … #define AR_PHY_AIC_F_WLAN_S … #define AR_PHY_AIC_CAL_CH_VALID_RESET … #define AR_PHY_AIC_CAL_CH_VALID_RESET_S … #define AR_PHY_AIC_CAL_ENABLE … #define AR_PHY_AIC_CAL_ENABLE_S … #define AR_PHY_AIC_BTTX_PWR_THR … #define AR_PHY_AIC_BTTX_PWR_THR_S … #define AR_PHY_AIC_ENABLE … #define AR_PHY_AIC_ENABLE_S … #define AR_PHY_AIC_CAL_BT_REF_DELAY … #define AR_PHY_AIC_CAL_BT_REF_DELAY_S … #define AR_PHY_AIC_BT_IDLE_CFG … #define AR_PHY_AIC_BT_IDLE_CFG_S … #define AR_PHY_AIC_STDBY_COND … #define AR_PHY_AIC_STDBY_COND_S … #define AR_PHY_AIC_STDBY_ROT_ATT_DB … #define AR_PHY_AIC_STDBY_ROT_ATT_DB_S … #define AR_PHY_AIC_STDBY_COM_ATT_DB … #define AR_PHY_AIC_STDBY_COM_ATT_DB_S … #define AR_PHY_AIC_RSSI_MAX … #define AR_PHY_AIC_RSSI_MAX_S … #define AR_PHY_AIC_RSSI_MIN … #define AR_PHY_AIC_RSSI_MIN_S … #define AR_PHY_AIC_RADIO_DELAY … #define AR_PHY_AIC_RADIO_DELAY_S … #define AR_PHY_AIC_CAL_STEP_SIZE_CORR … #define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S … #define AR_PHY_AIC_CAL_ROT_IDX_CORR … #define AR_PHY_AIC_CAL_ROT_IDX_CORR_S … #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR … #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S … #define AR_PHY_AIC_ROT_IDX_COUNT_MAX … #define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S … #define AR_PHY_AIC_CAL_SYNTH_TOGGLE … #define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S … #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX … #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S … #define AR_PHY_AIC_CAL_SYNTH_SETTLING … #define AR_PHY_AIC_CAL_SYNTH_SETTLING_S … #define AR_PHY_AIC_MON_MAX_HOP_COUNT … #define AR_PHY_AIC_MON_MAX_HOP_COUNT_S … #define AR_PHY_AIC_MON_MIN_STALE_COUNT … #define AR_PHY_AIC_MON_MIN_STALE_COUNT_S … #define AR_PHY_AIC_MON_PWR_EST_LONG … #define AR_PHY_AIC_MON_PWR_EST_LONG_S … #define AR_PHY_AIC_MON_PD_TALLY_SCALING … #define AR_PHY_AIC_MON_PD_TALLY_SCALING_S … #define AR_PHY_AIC_MON_PERF_THR … #define AR_PHY_AIC_MON_PERF_THR_S … #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING … #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S … #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR … #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S … #define AR_PHY_AIC_CAL_PWR_EST_LONG … #define AR_PHY_AIC_CAL_PWR_EST_LONG_S … #define AR_PHY_AIC_MON_DONE … #define AR_PHY_AIC_MON_DONE_S … #define AR_PHY_AIC_MON_ACTIVE … #define AR_PHY_AIC_MON_ACTIVE_S … #define AR_PHY_AIC_MEAS_COUNT … #define AR_PHY_AIC_MEAS_COUNT_S … #define AR_PHY_AIC_CAL_ANT_ISO_EST … #define AR_PHY_AIC_CAL_ANT_ISO_EST_S … #define AR_PHY_AIC_CAL_HOP_COUNT … #define AR_PHY_AIC_CAL_HOP_COUNT_S … #define AR_PHY_AIC_CAL_VALID_COUNT … #define AR_PHY_AIC_CAL_VALID_COUNT_S … #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR … #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S … #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR … #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S … #define AR_PHY_AIC_CAL_DONE … #define AR_PHY_AIC_CAL_DONE_S … #define AR_PHY_AIC_CAL_ACTIVE … #define AR_PHY_AIC_CAL_ACTIVE_S … #define AR_PHY_AIC_MEAS_MAG_MIN … #define AR_PHY_AIC_MEAS_MAG_MIN_S … #define AR_PHY_AIC_MON_STALE_COUNT … #define AR_PHY_AIC_MON_STALE_COUNT_S … #define AR_PHY_AIC_MON_HOP_COUNT … #define AR_PHY_AIC_MON_HOP_COUNT_S … #define AR_PHY_AIC_CAL_AIC_SM … #define AR_PHY_AIC_CAL_AIC_SM_S … #define AR_PHY_AIC_SM … #define AR_PHY_AIC_SM_S … #define AR_PHY_AIC_SRAM_VALID … #define AR_PHY_AIC_SRAM_VALID_S … #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB … #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S … #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN … #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S … #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB … #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S … #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN … #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S … #define AR_PHY_AIC_SRAM_COM_ATT_6DB … #define AR_PHY_AIC_SRAM_COM_ATT_6DB_S … #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO … #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S … #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO … #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S … #define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING … #define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING_S … #define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF … #define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF_S … #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED … #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S … #endif /* REG_AIC_H */
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