/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __ASM_ARCH_OMAP_IO_H #define __ASM_ARCH_OMAP_IO_H #ifndef __ASSEMBLER__ #include <linux/types.h> #ifdef CONFIG_ARCH_OMAP1 /* * NOTE: Please use ioremap + __raw_read/write where possible instead of these */ extern u8 omap_readb(u32 pa); extern u16 omap_readw(u32 pa); extern u32 omap_readl(u32 pa); extern void omap_writeb(u8 v, u32 pa); extern void omap_writew(u16 v, u32 pa); extern void omap_writel(u32 v, u32 pa); #elif defined(CONFIG_COMPILE_TEST) static inline u8 omap_readb(u32 pa) { … } static inline u16 omap_readw(u32 pa) { … } static inline u32 omap_readl(u32 pa) { … } static inline void omap_writeb(u8 v, u32 pa) { … } static inline void omap_writew(u16 v, u32 pa) { … } static inline void omap_writel(u32 v, u32 pa) { … } #endif #endif /* * ---------------------------------------------------------------------------- * System control registers * ---------------------------------------------------------------------------- */ #define MOD_CONF_CTRL_0 … #define MOD_CONF_CTRL_1 … /* * --------------------------------------------------------------------------- * UPLD * --------------------------------------------------------------------------- */ #define ULPD_REG_BASE … #define ULPD_IT_STATUS … #define ULPD_SETUP_ANALOG_CELL_3 … #define ULPD_CLOCK_CTRL … #define DIS_USB_PVCI_CLK … #define USB_MCLK_EN … #define ULPD_SOFT_REQ … #define SOFT_UDC_REQ … #define SOFT_USB_CLK_REQ … #define SOFT_DPLL_REQ … #define ULPD_DPLL_CTRL … #define ULPD_STATUS_REQ … #define ULPD_APLL_CTRL … #define ULPD_POWER_CTRL … #define ULPD_SOFT_DISABLE_REQ_REG … #define DIS_MMC2_DPLL_REQ … #define DIS_MMC1_DPLL_REQ … #define DIS_UART3_DPLL_REQ … #define DIS_UART2_DPLL_REQ … #define DIS_UART1_DPLL_REQ … #define DIS_USB_HOST_DPLL_REQ … #define ULPD_SDW_CLK_DIV_CTRL_SEL … #define ULPD_CAM_CLK_CTRL … /* * ---------------------------------------------------------------------------- * Clocks * ---------------------------------------------------------------------------- */ #define CLKGEN_REG_BASE … #define ARM_CKCTL … #define ARM_IDLECT1 … #define ARM_IDLECT2 … #define ARM_EWUPCT … #define ARM_RSTCT1 … #define ARM_RSTCT2 … #define ARM_SYSST … #define ARM_IDLECT3 … #define CK_RATEF … #define CK_IDLEF … #define CK_ENABLEF … #define CK_SELECTF … #define SETARM_IDLE_SHIFT /* DPLL control registers */ #define DPLL_CTL … /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ #define DSP_CONFIG_REG_BASE … #define DSP_CKCTL … #define DSP_IDLECT1 … #define DSP_IDLECT2 … #define DSP_RSTCT2 … /* * ---------------------------------------------------------------------------- * Pulse-Width Light * ---------------------------------------------------------------------------- */ #define OMAP_PWL_BASE … #define OMAP_PWL_ENABLE … #define OMAP_PWL_CLK_ENABLE … /* * ---------------------------------------------------------------------------- * Pin multiplexing registers * ---------------------------------------------------------------------------- */ #define FUNC_MUX_CTRL_0 … #define FUNC_MUX_CTRL_1 … #define FUNC_MUX_CTRL_2 … #define COMP_MODE_CTRL_0 … #define FUNC_MUX_CTRL_3 … #define FUNC_MUX_CTRL_4 … #define FUNC_MUX_CTRL_5 … #define FUNC_MUX_CTRL_6 … #define FUNC_MUX_CTRL_7 … #define FUNC_MUX_CTRL_8 … #define FUNC_MUX_CTRL_9 … #define FUNC_MUX_CTRL_A … #define FUNC_MUX_CTRL_B … #define FUNC_MUX_CTRL_C … #define FUNC_MUX_CTRL_D … #define PULL_DWN_CTRL_0 … #define PULL_DWN_CTRL_1 … #define PULL_DWN_CTRL_2 … #define PULL_DWN_CTRL_3 … #define PULL_DWN_CTRL_4 … /* OMAP-1610 specific multiplexing registers */ #define FUNC_MUX_CTRL_E … #define FUNC_MUX_CTRL_F … #define FUNC_MUX_CTRL_10 … #define FUNC_MUX_CTRL_11 … #define FUNC_MUX_CTRL_12 … #define PU_PD_SEL_0 … #define PU_PD_SEL_1 … #define PU_PD_SEL_2 … #define PU_PD_SEL_3 … #define PU_PD_SEL_4 … #endif
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