/* * Shared Atheros AR9170 Header * * Register map, hardware-specific definitions * * Copyright 2008, Johannes Berg <[email protected]> * Copyright 2009-2011 Christian Lamparter <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. If not, see * http://www.gnu.org/licenses/. * * This file incorporates work covered by the following copyright and * permission notice: * Copyright (c) 2007-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef __CARL9170_SHARED_HW_H #define __CARL9170_SHARED_HW_H /* High Speed UART */ #define AR9170_UART_REG_BASE … /* Definitions of interrupt registers */ #define AR9170_UART_REG_RX_BUFFER … #define AR9170_UART_REG_TX_HOLDING … #define AR9170_UART_REG_FIFO_CONTROL … #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO … #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO … #define AR9170_UART_REG_LINE_CONTROL … #define AR9170_UART_REG_MODEM_CONTROL … #define AR9170_UART_MODEM_CTRL_DTR_BIT … #define AR9170_UART_MODEM_CTRL_RTS_BIT … #define AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK … #define AR9170_UART_MODEM_CTRL_AUTO_RTS … #define AR9170_UART_MODEM_CTRL_AUTO_CTR … #define AR9170_UART_REG_LINE_STATUS … #define AR9170_UART_LINE_STS_RX_DATA_READY … #define AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN … #define AR9170_UART_LINE_STS_RX_BREAK_IND … #define AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY … #define AR9170_UART_LINE_STS_TRANSMITTER_EMPTY … #define AR9170_UART_REG_MODEM_STATUS … #define AR9170_UART_MODEM_STS_CTS_CHANGE … #define AR9170_UART_MODEM_STS_DSR_CHANGE … #define AR9170_UART_MODEM_STS_DCD_CHANGE … #define AR9170_UART_MODEM_STS_CTS_COMPL … #define AR9170_UART_MODEM_STS_DSR_COMPL … #define AR9170_UART_MODEM_STS_DCD_COMPL … #define AR9170_UART_REG_SCRATCH … #define AR9170_UART_REG_DIVISOR_LSB … #define AR9170_UART_REG_DIVISOR_MSB … #define AR9170_UART_REG_WORD_RX_BUFFER … #define AR9170_UART_REG_WORD_TX_HOLDING … #define AR9170_UART_REG_FIFO_COUNT … #define AR9170_UART_REG_REMAINDER … /* Timer */ #define AR9170_TIMER_REG_BASE … #define AR9170_TIMER_REG_WATCH_DOG … #define AR9170_TIMER_REG_TIMER0 … #define AR9170_TIMER_REG_TIMER1 … #define AR9170_TIMER_REG_TIMER2 … #define AR9170_TIMER_REG_TIMER3 … #define AR9170_TIMER_REG_TIMER4 … #define AR9170_TIMER_REG_CONTROL … #define AR9170_TIMER_CTRL_DISABLE_CLOCK … #define AR9170_TIMER_REG_INTERRUPT … #define AR9170_TIMER_INT_TIMER0 … #define AR9170_TIMER_INT_TIMER1 … #define AR9170_TIMER_INT_TIMER2 … #define AR9170_TIMER_INT_TIMER3 … #define AR9170_TIMER_INT_TIMER4 … #define AR9170_TIMER_INT_TICK_TIMER … #define AR9170_TIMER_REG_TICK_TIMER … #define AR9170_TIMER_REG_CLOCK_LOW … #define AR9170_TIMER_REG_CLOCK_HIGH … #define AR9170_MAC_REG_BASE … #define AR9170_MAC_REG_POWER_STATE_CTRL … #define AR9170_MAC_POWER_STATE_CTRL_RESET … #define AR9170_MAC_REG_MAC_POWER_STATE_CTRL … #define AR9170_MAC_REG_INT_CTRL … #define AR9170_MAC_INT_TXC … #define AR9170_MAC_INT_RXC … #define AR9170_MAC_INT_RETRY_FAIL … #define AR9170_MAC_INT_WAKEUP … #define AR9170_MAC_INT_ATIM … #define AR9170_MAC_INT_DTIM … #define AR9170_MAC_INT_CFG_BCN … #define AR9170_MAC_INT_ABORT … #define AR9170_MAC_INT_QOS … #define AR9170_MAC_INT_MIMO_PS … #define AR9170_MAC_INT_KEY_GEN … #define AR9170_MAC_INT_DECRY_NOUSER … #define AR9170_MAC_INT_RADAR … #define AR9170_MAC_INT_QUIET_FRAME … #define AR9170_MAC_INT_PRETBTT … #define AR9170_MAC_REG_TSF_L … #define AR9170_MAC_REG_TSF_H … #define AR9170_MAC_REG_ATIM_WINDOW … #define AR9170_MAC_ATIM_PERIOD_S … #define AR9170_MAC_ATIM_PERIOD … #define AR9170_MAC_REG_BCN_PERIOD … #define AR9170_MAC_BCN_PERIOD_S … #define AR9170_MAC_BCN_PERIOD … #define AR9170_MAC_BCN_DTIM_S … #define AR9170_MAC_BCN_DTIM … #define AR9170_MAC_BCN_AP_MODE … #define AR9170_MAC_BCN_IBSS_MODE … #define AR9170_MAC_BCN_PWR_MGT … #define AR9170_MAC_BCN_STA_PS … #define AR9170_MAC_REG_PRETBTT … #define AR9170_MAC_PRETBTT_S … #define AR9170_MAC_PRETBTT … #define AR9170_MAC_PRETBTT2_S … #define AR9170_MAC_PRETBTT2 … #define AR9170_MAC_REG_MAC_ADDR_L … #define AR9170_MAC_REG_MAC_ADDR_H … #define AR9170_MAC_REG_BSSID_L … #define AR9170_MAC_REG_BSSID_H … #define AR9170_MAC_REG_GROUP_HASH_TBL_L … #define AR9170_MAC_REG_GROUP_HASH_TBL_H … #define AR9170_MAC_REG_RX_TIMEOUT … #define AR9170_MAC_REG_BASIC_RATE … #define AR9170_MAC_REG_MANDATORY_RATE … #define AR9170_MAC_REG_RTS_CTS_RATE … #define AR9170_MAC_REG_BACKOFF_PROTECT … #define AR9170_MAC_REG_RX_THRESHOLD … #define AR9170_MAC_REG_AFTER_PNP … #define AR9170_MAC_REG_RX_PE_DELAY … #define AR9170_MAC_REG_DYNAMIC_SIFS_ACK … #define AR9170_MAC_REG_SNIFFER … #define AR9170_MAC_SNIFFER_ENABLE_PROMISC … #define AR9170_MAC_SNIFFER_DEFAULTS … #define AR9170_MAC_REG_ENCRYPTION … #define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE … #define AR9170_MAC_ENCRYPTION_RX_SOFTWARE … #define AR9170_MAC_ENCRYPTION_DEFAULTS … #define AR9170_MAC_REG_MISC_680 … #define AR9170_MAC_REG_MISC_684 … #define AR9170_MAC_REG_TX_UNDERRUN … #define AR9170_MAC_REG_FRAMETYPE_FILTER … #define AR9170_MAC_FTF_ASSOC_REQ … #define AR9170_MAC_FTF_ASSOC_RESP … #define AR9170_MAC_FTF_REASSOC_REQ … #define AR9170_MAC_FTF_REASSOC_RESP … #define AR9170_MAC_FTF_PRB_REQ … #define AR9170_MAC_FTF_PRB_RESP … #define AR9170_MAC_FTF_BIT6 … #define AR9170_MAC_FTF_BIT7 … #define AR9170_MAC_FTF_BEACON … #define AR9170_MAC_FTF_ATIM … #define AR9170_MAC_FTF_DEASSOC … #define AR9170_MAC_FTF_AUTH … #define AR9170_MAC_FTF_DEAUTH … #define AR9170_MAC_FTF_BIT13 … #define AR9170_MAC_FTF_BIT14 … #define AR9170_MAC_FTF_BIT15 … #define AR9170_MAC_FTF_BAR … #define AR9170_MAC_FTF_BA … #define AR9170_MAC_FTF_PSPOLL … #define AR9170_MAC_FTF_RTS … #define AR9170_MAC_FTF_CTS … #define AR9170_MAC_FTF_ACK … #define AR9170_MAC_FTF_CFE … #define AR9170_MAC_FTF_CFE_ACK … #define AR9170_MAC_FTF_DEFAULTS … #define AR9170_MAC_FTF_MONITOR … #define AR9170_MAC_REG_ACK_EXTENSION … #define AR9170_MAC_REG_ACK_TPC … #define AR9170_MAC_REG_EIFS_AND_SIFS … #define AR9170_MAC_REG_RX_TIMEOUT_COUNT … #define AR9170_MAC_REG_RX_TOTAL … #define AR9170_MAC_REG_RX_CRC32 … #define AR9170_MAC_REG_RX_CRC16 … #define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI … #define AR9170_MAC_REG_RX_OVERRUN … #define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL … #define AR9170_MAC_REG_TX_BLOCKACKS … #define AR9170_MAC_REG_NAV_COUNT … #define AR9170_MAC_REG_BACKOFF_STATUS … #define AR9170_MAC_BACKOFF_CCA … #define AR9170_MAC_BACKOFF_TX_PEX … #define AR9170_MAC_BACKOFF_RX_PE … #define AR9170_MAC_BACKOFF_MD_READY … #define AR9170_MAC_BACKOFF_TX_PE … #define AR9170_MAC_REG_TX_RETRY … #define AR9170_MAC_REG_TX_COMPLETE … #define AR9170_MAC_REG_CHANNEL_BUSY … #define AR9170_MAC_REG_EXT_BUSY … #define AR9170_MAC_REG_SLOT_TIME … #define AR9170_MAC_REG_TX_TOTAL … #define AR9170_MAC_REG_ACK_FC … #define AR9170_MAC_REG_CAM_MODE … #define AR9170_MAC_CAM_IBSS … #define AR9170_MAC_CAM_AP … #define AR9170_MAC_CAM_STA … #define AR9170_MAC_CAM_AP_WDS … #define AR9170_MAC_CAM_DEFAULTS … #define AR9170_MAC_CAM_HOST_PENDING … #define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L … #define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H … #define AR9170_MAC_REG_CAM_ADDR … #define AR9170_MAC_CAM_ADDR_WRITE … #define AR9170_MAC_REG_CAM_DATA0 … #define AR9170_MAC_REG_CAM_DATA1 … #define AR9170_MAC_REG_CAM_DATA2 … #define AR9170_MAC_REG_CAM_DATA3 … #define AR9170_MAC_REG_CAM_DBG0 … #define AR9170_MAC_REG_CAM_DBG1 … #define AR9170_MAC_REG_CAM_DBG2 … #define AR9170_MAC_REG_CAM_STATE … #define AR9170_MAC_CAM_STATE_READ_PENDING … #define AR9170_MAC_CAM_STATE_WRITE_PENDING … #define AR9170_MAC_REG_CAM_TXKEY … #define AR9170_MAC_REG_CAM_RXKEY … #define AR9170_MAC_REG_CAM_TX_ENC_TYPE … #define AR9170_MAC_REG_CAM_RX_ENC_TYPE … #define AR9170_MAC_REG_CAM_TX_SERACH_HIT … #define AR9170_MAC_REG_CAM_RX_SERACH_HIT … #define AR9170_MAC_REG_AC0_CW … #define AR9170_MAC_REG_AC1_CW … #define AR9170_MAC_REG_AC2_CW … #define AR9170_MAC_REG_AC3_CW … #define AR9170_MAC_REG_AC4_CW … #define AR9170_MAC_REG_AC2_AC1_AC0_AIFS … #define AR9170_MAC_REG_AC4_AC3_AC2_AIFS … #define AR9170_MAC_REG_TXOP_ACK_EXTENSION … #define AR9170_MAC_REG_TXOP_ACK_INTERVAL … #define AR9170_MAC_REG_CONTENTION_POINT … #define AR9170_MAC_REG_RETRY_MAX … #define AR9170_MAC_REG_TID_CFACK_CFEND_RATE … #define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND … #define AR9170_MAC_REG_TKIP_TSC … #define AR9170_MAC_REG_TXOP_DURATION … #define AR9170_MAC_REG_TX_QOS_THRESHOLD … #define AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA … #define AR9170_MAC_VIRTUAL_CCA_Q0 … #define AR9170_MAC_VIRTUAL_CCA_Q1 … #define AR9170_MAC_VIRTUAL_CCA_Q2 … #define AR9170_MAC_VIRTUAL_CCA_Q3 … #define AR9170_MAC_VIRTUAL_CCA_Q4 … #define AR9170_MAC_VIRTUAL_CCA_ALL … #define AR9170_MAC_REG_AC1_AC0_TXOP … #define AR9170_MAC_REG_AC3_AC2_TXOP … #define AR9170_MAC_REG_AMPDU_COUNT … #define AR9170_MAC_REG_MPDU_COUNT … #define AR9170_MAC_REG_AMPDU_FACTOR … #define AR9170_MAC_AMPDU_FACTOR … #define AR9170_MAC_AMPDU_FACTOR_S … #define AR9170_MAC_REG_AMPDU_DENSITY … #define AR9170_MAC_AMPDU_DENSITY … #define AR9170_MAC_AMPDU_DENSITY_S … #define AR9170_MAC_REG_FCS_SELECT … #define AR9170_MAC_FCS_SWFCS … #define AR9170_MAC_FCS_FIFO_PROT … #define AR9170_MAC_REG_RTS_CTS_TPC … #define AR9170_MAC_REG_CFEND_QOSNULL_TPC … #define AR9170_MAC_REG_ACK_TABLE … #define AR9170_MAC_REG_RX_CONTROL … #define AR9170_MAC_RX_CTRL_DEAGG … #define AR9170_MAC_RX_CTRL_SHORT_FILTER … #define AR9170_MAC_RX_CTRL_SA_DA_SEARCH … #define AR9170_MAC_RX_CTRL_PASS_TO_HOST … #define AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER … #define AR9170_MAC_REG_RX_CONTROL_1 … #define AR9170_MAC_REG_AMPDU_RX_THRESH … #define AR9170_MAC_REG_RX_MPDU … #define AR9170_MAC_REG_RX_DROPPED_MPDU … #define AR9170_MAC_REG_RX_DEL_MPDU … #define AR9170_MAC_REG_RX_PHY_MISC_ERROR … #define AR9170_MAC_REG_RX_PHY_XR_ERROR … #define AR9170_MAC_REG_RX_PHY_OFDM_ERROR … #define AR9170_MAC_REG_RX_PHY_CCK_ERROR … #define AR9170_MAC_REG_RX_PHY_HT_ERROR … #define AR9170_MAC_REG_RX_PHY_TOTAL … #define AR9170_MAC_REG_DMA_TXQ_ADDR … #define AR9170_MAC_REG_DMA_TXQ_CURR_ADDR … #define AR9170_MAC_REG_DMA_TXQ0_ADDR … #define AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR … #define AR9170_MAC_REG_DMA_TXQ1_ADDR … #define AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR … #define AR9170_MAC_REG_DMA_TXQ2_ADDR … #define AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR … #define AR9170_MAC_REG_DMA_TXQ3_ADDR … #define AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR … #define AR9170_MAC_REG_DMA_TXQ4_ADDR … #define AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR … #define AR9170_MAC_REG_DMA_RXQ_ADDR … #define AR9170_MAC_REG_DMA_RXQ_CURR_ADDR … #define AR9170_MAC_REG_DMA_TRIGGER … #define AR9170_DMA_TRIGGER_TXQ0 … #define AR9170_DMA_TRIGGER_TXQ1 … #define AR9170_DMA_TRIGGER_TXQ2 … #define AR9170_DMA_TRIGGER_TXQ3 … #define AR9170_DMA_TRIGGER_TXQ4 … #define AR9170_DMA_TRIGGER_RXQ … #define AR9170_MAC_REG_DMA_WLAN_STATUS … #define AR9170_MAC_REG_DMA_STATUS … #define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQ0Q1_LEN … #define AR9170_MAC_REG_DMA_TXQ2Q3_LEN … #define AR9170_MAC_REG_DMA_TXQ4_LEN … #define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR … #define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR … #define AR9170_MAC_REG_TXRX_MPI … #define AR9170_MAC_TXRX_MPI_TX_MPI_MASK … #define AR9170_MAC_TXRX_MPI_TX_TO_MASK … #define AR9170_MAC_TXRX_MPI_RX_MPI_MASK … #define AR9170_MAC_TXRX_MPI_RX_TO_MASK … #define AR9170_MAC_REG_BCN_ADDR … #define AR9170_MAC_REG_BCN_LENGTH … #define AR9170_MAC_BCN_LENGTH_MAX … #define AR9170_MAC_REG_BCN_STATUS … #define AR9170_MAC_REG_BCN_PLCP … #define AR9170_MAC_REG_BCN_CTRL … #define AR9170_BCN_CTRL_READY … #define AR9170_BCN_CTRL_LOCK … #define AR9170_MAC_REG_BCN_CURR_ADDR … #define AR9170_MAC_REG_BCN_COUNT … #define AR9170_MAC_REG_BCN_HT1 … #define AR9170_MAC_BCN_HT1_HT_EN … #define AR9170_MAC_BCN_HT1_GF_PMB … #define AR9170_MAC_BCN_HT1_SP_EXP … #define AR9170_MAC_BCN_HT1_TX_BF … #define AR9170_MAC_BCN_HT1_PWR_CTRL_S … #define AR9170_MAC_BCN_HT1_PWR_CTRL … #define AR9170_MAC_BCN_HT1_TX_ANT1 … #define AR9170_MAC_BCN_HT1_TX_ANT0 … #define AR9170_MAC_BCN_HT1_NUM_LFT_S … #define AR9170_MAC_BCN_HT1_NUM_LFT … #define AR9170_MAC_BCN_HT1_BWC_20M_EXT … #define AR9170_MAC_BCN_HT1_BWC_40M_SHARED … #define AR9170_MAC_BCN_HT1_BWC_40M_DUP … #define AR9170_MAC_BCN_HT1_BF_MCS_S … #define AR9170_MAC_BCN_HT1_BF_MCS … #define AR9170_MAC_BCN_HT1_TPC_S … #define AR9170_MAC_BCN_HT1_TPC … #define AR9170_MAC_BCN_HT1_CHAIN_MASK_S … #define AR9170_MAC_BCN_HT1_CHAIN_MASK … #define AR9170_MAC_REG_BCN_HT2 … #define AR9170_MAC_BCN_HT2_MCS_S … #define AR9170_MAC_BCN_HT2_MCS … #define AR9170_MAC_BCN_HT2_BW40 … #define AR9170_MAC_BCN_HT2_SMOOTHING … #define AR9170_MAC_BCN_HT2_SS … #define AR9170_MAC_BCN_HT2_NSS … #define AR9170_MAC_BCN_HT2_STBC_S … #define AR9170_MAC_BCN_HT2_STBC … #define AR9170_MAC_BCN_HT2_ADV_COD … #define AR9170_MAC_BCN_HT2_SGI … #define AR9170_MAC_BCN_HT2_LEN_S … #define AR9170_MAC_BCN_HT2_LEN … #define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR … /* Random number generator */ #define AR9170_RAND_REG_BASE … #define AR9170_RAND_REG_NUM … #define AR9170_RAND_REG_MODE … #define AR9170_RAND_MODE_MANUAL … #define AR9170_RAND_MODE_FREE … /* GPIO */ #define AR9170_GPIO_REG_BASE … #define AR9170_GPIO_REG_PORT_TYPE … #define AR9170_GPIO_REG_PORT_DATA … #define AR9170_GPIO_PORT_LED_0 … #define AR9170_GPIO_PORT_LED_1 … /* WPS Button GPIO for TP-Link TL-WN821N */ #define AR9170_GPIO_PORT_WPS_BUTTON_PRESSED … /* Memory Controller */ #define AR9170_MC_REG_BASE … #define AR9170_MC_REG_FLASH_WAIT_STATE … #define AR9170_SPI_REG_BASE … #define AR9170_SPI_REG_CONTROL0 … #define AR9170_SPI_CONTROL0_BUSY … #define AR9170_SPI_CONTROL0_CMD_GO … #define AR9170_SPI_CONTROL0_PAGE_WR … #define AR9170_SPI_CONTROL0_SEQ_RD … #define AR9170_SPI_CONTROL0_CMD_ABORT … #define AR9170_SPI_CONTROL0_CMD_LEN_S … #define AR9170_SPI_CONTROL0_CMD_LEN … #define AR9170_SPI_CONTROL0_RD_LEN_S … #define AR9170_SPI_CONTROL0_RD_LEN … #define AR9170_SPI_REG_CONTROL1 … #define AR9170_SPI_CONTROL1_SCK_RATE … #define AR9170_SPI_CONTROL1_DRIVE_SDO … #define AR9170_SPI_CONTROL1_MODE_SEL_S … #define AR9170_SPI_CONTROL1_MODE_SEL … #define AR9170_SPI_CONTROL1_WRITE_PROTECT … #define AR9170_SPI_REG_COMMAND_PORT0 … #define AR9170_SPI_COMMAND_PORT0_CMD0_S … #define AR9170_SPI_COMMAND_PORT0_CMD0 … #define AR9170_SPI_COMMAND_PORT0_CMD1_S … #define AR9170_SPI_COMMAND_PORT0_CMD1 … #define AR9170_SPI_COMMAND_PORT0_CMD2_S … #define AR9170_SPI_COMMAND_PORT0_CMD2 … #define AR9170_SPI_COMMAND_PORT0_CMD3_S … #define AR9170_SPI_COMMAND_PORT0_CMD3 … #define AR9170_SPI_REG_COMMAND_PORT1 … #define AR9170_SPI_COMMAND_PORT1_CMD4_S … #define AR9170_SPI_COMMAND_PORT1_CMD4 … #define AR9170_SPI_COMMAND_PORT1_CMD5_S … #define AR9170_SPI_COMMAND_PORT1_CMD5 … #define AR9170_SPI_COMMAND_PORT1_CMD6_S … #define AR9170_SPI_COMMAND_PORT1_CMD6 … #define AR9170_SPI_COMMAND_PORT1_CMD7_S … #define AR9170_SPI_COMMAND_PORT1_CMD7 … #define AR9170_SPI_REG_DATA_PORT … #define AR9170_SPI_REG_PAGE_WRITE_LEN … #define AR9170_EEPROM_REG_BASE … #define AR9170_EEPROM_REG_WP_MAGIC1 … #define AR9170_EEPROM_WP_MAGIC1 … #define AR9170_EEPROM_REG_WP_MAGIC2 … #define AR9170_EEPROM_WP_MAGIC2 … #define AR9170_EEPROM_REG_WP_MAGIC3 … #define AR9170_EEPROM_WP_MAGIC3 … #define AR9170_EEPROM_REG_CLOCK_DIV … #define AR9170_EEPROM_CLOCK_DIV_FAC_S … #define AR9170_EEPROM_CLOCK_DIV_FAC … #define AR9170_EEPROM_CLOCK_DIV_FAC_39KHZ … #define AR9170_EEPROM_CLOCK_DIV_FAC_78KHZ … #define AR9170_EEPROM_CLOCK_DIV_FAC_312KHZ … #define AR9170_EEPROM_CLOCK_DIV_FAC_10MHZ … #define AR9170_EEPROM_CLOCK_DIV_SOFT_RST … #define AR9170_EEPROM_REG_MODE … #define AR9170_EEPROM_MODE_EEPROM_SIZE_16K_PLUS … #define AR9170_EEPROM_REG_WRITE_PROTECT … #define AR9170_EEPROM_WRITE_PROTECT_WP_STATUS … #define AR9170_EEPROM_WRITE_PROTECT_WP_SET … /* Interrupt Controller */ #define AR9170_MAX_INT_SRC … #define AR9170_INT_REG_BASE … #define AR9170_INT_REG_FLAG … #define AR9170_INT_REG_FIQ_MASK … #define AR9170_INT_REG_IRQ_MASK … /* INT_REG_FLAG, INT_REG_FIQ_MASK and INT_REG_IRQ_MASK */ #define AR9170_INT_FLAG_WLAN … #define AR9170_INT_FLAG_PTAB_BIT … #define AR9170_INT_FLAG_SE_BIT … #define AR9170_INT_FLAG_UART_BIT … #define AR9170_INT_FLAG_TIMER_BIT … #define AR9170_INT_FLAG_EXT_BIT … #define AR9170_INT_FLAG_SW_BIT … #define AR9170_INT_FLAG_USB_BIT … #define AR9170_INT_FLAG_ETHERNET_BIT … #define AR9170_INT_REG_PRIORITY1 … #define AR9170_INT_REG_PRIORITY2 … #define AR9170_INT_REG_PRIORITY3 … #define AR9170_INT_REG_EXT_INT_CONTROL … #define AR9170_INT_REG_SW_INT_CONTROL … #define AR9170_INT_SW_INT_ENABLE … #define AR9170_INT_REG_FIQ_ENCODE … #define AR9170_INT_INT_IRQ_ENCODE … /* Power Management */ #define AR9170_PWR_REG_BASE … #define AR9170_PWR_REG_POWER_STATE … #define AR9170_PWR_REG_RESET … #define AR9170_PWR_RESET_COMMIT_RESET_MASK … #define AR9170_PWR_RESET_WLAN_MASK … #define AR9170_PWR_RESET_DMA_MASK … #define AR9170_PWR_RESET_BRIDGE_MASK … #define AR9170_PWR_RESET_AHB_MASK … #define AR9170_PWR_RESET_BB_WARM_RESET … #define AR9170_PWR_RESET_BB_COLD_RESET … #define AR9170_PWR_RESET_ADDA_CLK_COLD_RESET … #define AR9170_PWR_RESET_PLL … #define AR9170_PWR_RESET_USB_PLL … #define AR9170_PWR_REG_CLOCK_SEL … #define AR9170_PWR_CLK_AHB_40MHZ … #define AR9170_PWR_CLK_AHB_20_22MHZ … #define AR9170_PWR_CLK_AHB_40_44MHZ … #define AR9170_PWR_CLK_AHB_80_88MHZ … #define AR9170_PWR_CLK_DAC_160_INV_DLY … #define AR9170_PWR_REG_CHIP_REVISION … #define AR9170_PWR_REG_PLL_ADDAC … #define AR9170_PWR_PLL_ADDAC_DIV_S … #define AR9170_PWR_PLL_ADDAC_DIV … #define AR9170_PWR_REG_WATCH_DOG_MAGIC … /* Faraday USB Controller */ #define AR9170_USB_REG_BASE … #define AR9170_USB_REG_MAIN_CTRL … #define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP … #define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT … #define AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND … #define AR9170_USB_MAIN_CTRL_RESET … #define AR9170_USB_MAIN_CTRL_CHIP_ENABLE … #define AR9170_USB_MAIN_CTRL_HIGHSPEED … #define AR9170_USB_REG_DEVICE_ADDRESS … #define AR9170_USB_DEVICE_ADDRESS_CONFIGURE … #define AR9170_USB_REG_TEST … #define AR9170_USB_REG_PHY_TEST_SELECT … #define AR9170_USB_REG_CX_CONFIG_STATUS … #define AR9170_USB_REG_EP0_DATA … #define AR9170_USB_REG_EP0_DATA1 … #define AR9170_USB_REG_EP0_DATA2 … #define AR9170_USB_REG_INTR_MASK_BYTE_0 … #define AR9170_USB_REG_INTR_MASK_BYTE_1 … #define AR9170_USB_REG_INTR_MASK_BYTE_2 … #define AR9170_USB_REG_INTR_MASK_BYTE_3 … #define AR9170_USB_REG_INTR_MASK_BYTE_4 … #define AR9170_USB_INTR_DISABLE_OUT_INT … #define AR9170_USB_REG_INTR_MASK_BYTE_5 … #define AR9170_USB_REG_INTR_MASK_BYTE_6 … #define AR9170_USB_INTR_DISABLE_IN_INT … #define AR9170_USB_REG_INTR_MASK_BYTE_7 … #define AR9170_USB_REG_INTR_GROUP … #define AR9170_USB_REG_INTR_SOURCE_0 … #define AR9170_USB_INTR_SRC0_SETUP … #define AR9170_USB_INTR_SRC0_IN … #define AR9170_USB_INTR_SRC0_OUT … #define AR9170_USB_INTR_SRC0_FAIL … #define AR9170_USB_INTR_SRC0_END … #define AR9170_USB_INTR_SRC0_ABORT … #define AR9170_USB_REG_INTR_SOURCE_1 … #define AR9170_USB_REG_INTR_SOURCE_2 … #define AR9170_USB_REG_INTR_SOURCE_3 … #define AR9170_USB_REG_INTR_SOURCE_4 … #define AR9170_USB_REG_INTR_SOURCE_5 … #define AR9170_USB_REG_INTR_SOURCE_6 … #define AR9170_USB_REG_INTR_SOURCE_7 … #define AR9170_USB_INTR_SRC7_USB_RESET … #define AR9170_USB_INTR_SRC7_USB_SUSPEND … #define AR9170_USB_INTR_SRC7_USB_RESUME … #define AR9170_USB_INTR_SRC7_ISO_SEQ_ERR … #define AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT … #define AR9170_USB_INTR_SRC7_TX0BYTE … #define AR9170_USB_INTR_SRC7_RX0BYTE … #define AR9170_USB_REG_IDLE_COUNT … #define AR9170_USB_REG_EP_MAP … #define AR9170_USB_REG_EP1_MAP … #define AR9170_USB_REG_EP2_MAP … #define AR9170_USB_REG_EP3_MAP … #define AR9170_USB_REG_EP4_MAP … #define AR9170_USB_REG_EP5_MAP … #define AR9170_USB_REG_EP6_MAP … #define AR9170_USB_REG_EP7_MAP … #define AR9170_USB_REG_EP8_MAP … #define AR9170_USB_REG_EP9_MAP … #define AR9170_USB_REG_EP10_MAP … #define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH … #define AR9170_USB_EP_IN_STALL … #define AR9170_USB_EP_IN_TOGGLE … #define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW … #define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH … #define AR9170_USB_EP_OUT_STALL … #define AR9170_USB_EP_OUT_TOGGLE … #define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW … #define AR9170_USB_REG_EP3_BYTE_COUNT_HIGH … #define AR9170_USB_REG_EP3_BYTE_COUNT_LOW … #define AR9170_USB_REG_EP4_BYTE_COUNT_HIGH … #define AR9170_USB_REG_EP4_BYTE_COUNT_LOW … #define AR9170_USB_REG_FIFO_MAP … #define AR9170_USB_REG_FIFO0_MAP … #define AR9170_USB_REG_FIFO1_MAP … #define AR9170_USB_REG_FIFO2_MAP … #define AR9170_USB_REG_FIFO3_MAP … #define AR9170_USB_REG_FIFO4_MAP … #define AR9170_USB_REG_FIFO5_MAP … #define AR9170_USB_REG_FIFO6_MAP … #define AR9170_USB_REG_FIFO7_MAP … #define AR9170_USB_REG_FIFO8_MAP … #define AR9170_USB_REG_FIFO9_MAP … #define AR9170_USB_REG_FIFO_CONFIG … #define AR9170_USB_REG_FIFO0_CONFIG … #define AR9170_USB_REG_FIFO1_CONFIG … #define AR9170_USB_REG_FIFO2_CONFIG … #define AR9170_USB_REG_FIFO3_CONFIG … #define AR9170_USB_REG_FIFO4_CONFIG … #define AR9170_USB_REG_FIFO5_CONFIG … #define AR9170_USB_REG_FIFO6_CONFIG … #define AR9170_USB_REG_FIFO7_CONFIG … #define AR9170_USB_REG_FIFO8_CONFIG … #define AR9170_USB_REG_FIFO9_CONFIG … #define AR9170_USB_REG_EP3_DATA … #define AR9170_USB_REG_EP4_DATA … #define AR9170_USB_REG_FIFO_SIZE … #define AR9170_USB_REG_DMA_CTL … #define AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE … #define AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE … #define AR9170_USB_DMA_CTL_HIGH_SPEED … #define AR9170_USB_DMA_CTL_UP_PACKET_MODE … #define AR9170_USB_DMA_CTL_UP_STREAM_S … #define AR9170_USB_DMA_CTL_UP_STREAM … #define AR9170_USB_DMA_CTL_UP_STREAM_4K … #define AR9170_USB_DMA_CTL_UP_STREAM_8K … #define AR9170_USB_DMA_CTL_UP_STREAM_16K … #define AR9170_USB_DMA_CTL_UP_STREAM_32K … #define AR9170_USB_DMA_CTL_DOWN_STREAM … #define AR9170_USB_REG_DMA_STATUS … #define AR9170_USB_DMA_STATUS_UP_IDLE … #define AR9170_USB_DMA_STATUS_DN_IDLE … #define AR9170_USB_REG_MAX_AGG_UPLOAD … #define AR9170_USB_REG_UPLOAD_TIME_CTL … #define AR9170_USB_REG_WAKE_UP … #define AR9170_USB_WAKE_UP_WAKE … #define AR9170_USB_REG_CBUS_CTRL … #define AR9170_USB_CBUS_CTRL_BUFFER_END … /* PCI/USB to AHB Bridge */ #define AR9170_PTA_REG_BASE … #define AR9170_PTA_REG_CMD … #define AR9170_PTA_REG_PARAM1 … #define AR9170_PTA_REG_PARAM2 … #define AR9170_PTA_REG_PARAM3 … #define AR9170_PTA_REG_RSP … #define AR9170_PTA_REG_STATUS1 … #define AR9170_PTA_REG_STATUS2 … #define AR9170_PTA_REG_STATUS3 … #define AR9170_PTA_REG_AHB_INT_FLAG … #define AR9170_PTA_REG_AHB_INT_MASK … #define AR9170_PTA_REG_AHB_INT_ACK … #define AR9170_PTA_REG_AHB_SCRATCH1 … #define AR9170_PTA_REG_AHB_SCRATCH2 … #define AR9170_PTA_REG_AHB_SCRATCH3 … #define AR9170_PTA_REG_AHB_SCRATCH4 … #define AR9170_PTA_REG_SHARE_MEM_CTRL … /* * PCI to AHB Bridge */ #define AR9170_PTA_REG_INT_FLAG … #define AR9170_PTA_INT_FLAG_DN … #define AR9170_PTA_INT_FLAG_UP … #define AR9170_PTA_INT_FLAG_CMD … #define AR9170_PTA_REG_INT_MASK … #define AR9170_PTA_REG_DN_DMA_ADDRL … #define AR9170_PTA_REG_DN_DMA_ADDRH … #define AR9170_PTA_REG_UP_DMA_ADDRL … #define AR9170_PTA_REG_UP_DMA_ADDRH … #define AR9170_PTA_REG_DN_PEND_TIME … #define AR9170_PTA_REG_UP_PEND_TIME … #define AR9170_PTA_REG_CONTROL … #define AR9170_PTA_CTRL_4_BEAT_BURST … #define AR9170_PTA_CTRL_8_BEAT_BURST … #define AR9170_PTA_CTRL_16_BEAT_BURST … #define AR9170_PTA_CTRL_LOOPBACK_MODE … #define AR9170_PTA_REG_MEM_CTRL … #define AR9170_PTA_REG_MEM_ADDR … #define AR9170_PTA_REG_DN_DMA_TRIGGER … #define AR9170_PTA_REG_UP_DMA_TRIGGER … #define AR9170_PTA_REG_DMA_STATUS … #define AR9170_PTA_REG_DN_CURR_ADDRL … #define AR9170_PTA_REG_DN_CURR_ADDRH … #define AR9170_PTA_REG_UP_CURR_ADDRL … #define AR9170_PTA_REG_UP_CURR_ADDRH … #define AR9170_PTA_REG_DMA_MODE_CTRL … #define AR9170_PTA_DMA_MODE_CTRL_RESET … #define AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB … /* Protocol Controller Module */ #define AR9170_MAC_REG_PC_REG_BASE … #define AR9170_NUM_LEDS … /* CAM */ #define AR9170_CAM_MAX_USER … #define AR9170_CAM_MAX_KEY_LENGTH … #define AR9170_SRAM_OFFSET … #define AR9170_SRAM_SIZE … #define AR9170_PRAM_OFFSET … #define AR9170_PRAM_SIZE … enum cpu_clock { … }; /* USB endpoints */ enum ar9170_usb_ep { … }; enum ar9170_usb_fifo { … }; enum ar9170_tx_queues { … }; #define AR9170_TX_STREAM_TAG … #define AR9170_RX_STREAM_TAG … #define AR9170_RX_STREAM_MAX_SIZE … struct ar9170_stream { … } __packed __aligned(…); #define AR9170_STREAM_LEN … #define AR9170_MAX_ACKTABLE_ENTRIES … #define AR9170_MAX_VIRTUAL_MAC … #define AR9170_USB_EP_CTRL_MAX … #define AR9170_USB_EP_TX_MAX … #define AR9170_USB_EP_RX_MAX … #define AR9170_USB_EP_IRQ_MAX … #define AR9170_USB_EP_CMD_MAX … /* Trigger PRETBTT interrupt 6 Kus earlier */ #define CARL9170_PRETBTT_KUS … #define AR5416_MAX_RATE_POWER … #define SET_VAL(reg, value, newvalue) … #define SET_CONSTVAL(reg, newvalue) … #define MOD_VAL(reg, value, newvalue) … #define GET_VAL(reg, value) … #endif /* __CARL9170_SHARED_HW_H */
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