/* * Shared Atheros AR9170 Header * * RX/TX meta descriptor format * * Copyright 2008, Johannes Berg <[email protected]> * Copyright 2009-2011 Christian Lamparter <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. If not, see * http://www.gnu.org/licenses/. * * This file incorporates work covered by the following copyright and * permission notice: * Copyright (c) 2007-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef __CARL9170_SHARED_WLAN_H #define __CARL9170_SHARED_WLAN_H #include "fwcmd.h" #define AR9170_RX_PHY_RATE_CCK_1M … #define AR9170_RX_PHY_RATE_CCK_2M … #define AR9170_RX_PHY_RATE_CCK_5M … #define AR9170_RX_PHY_RATE_CCK_11M … #define AR9170_ENC_ALG_NONE … #define AR9170_ENC_ALG_WEP64 … #define AR9170_ENC_ALG_TKIP … #define AR9170_ENC_ALG_AESCCMP … #define AR9170_ENC_ALG_WEP128 … #define AR9170_ENC_ALG_WEP256 … #define AR9170_ENC_ALG_CENC … #define AR9170_RX_ENC_SOFTWARE … #define AR9170_RX_STATUS_MODULATION … #define AR9170_RX_STATUS_MODULATION_S … #define AR9170_RX_STATUS_MODULATION_CCK … #define AR9170_RX_STATUS_MODULATION_OFDM … #define AR9170_RX_STATUS_MODULATION_HT … #define AR9170_RX_STATUS_MODULATION_DUPOFDM … /* depends on modulation */ #define AR9170_RX_STATUS_SHORT_PREAMBLE … #define AR9170_RX_STATUS_GREENFIELD … #define AR9170_RX_STATUS_MPDU … #define AR9170_RX_STATUS_MPDU_S … #define AR9170_RX_STATUS_MPDU_SINGLE … #define AR9170_RX_STATUS_MPDU_FIRST … #define AR9170_RX_STATUS_MPDU_MIDDLE … #define AR9170_RX_STATUS_MPDU_LAST … #define AR9170_RX_STATUS_CONT_AGGR … #define AR9170_RX_STATUS_TOTAL_ERROR … #define AR9170_RX_ERROR_RXTO … #define AR9170_RX_ERROR_OVERRUN … #define AR9170_RX_ERROR_DECRYPT … #define AR9170_RX_ERROR_FCS … #define AR9170_RX_ERROR_WRONG_RA … #define AR9170_RX_ERROR_PLCP … #define AR9170_RX_ERROR_MMIC … /* these are either-or */ #define AR9170_TX_MAC_PROT_RTS … #define AR9170_TX_MAC_PROT_CTS … #define AR9170_TX_MAC_PROT … #define AR9170_TX_MAC_NO_ACK … /* if unset, MAC will only do SIFS space before frame */ #define AR9170_TX_MAC_BACKOFF … #define AR9170_TX_MAC_BURST … #define AR9170_TX_MAC_AGGR … /* encryption is a two-bit field */ #define AR9170_TX_MAC_ENCR_NONE … #define AR9170_TX_MAC_ENCR_RC4 … #define AR9170_TX_MAC_ENCR_CENC … #define AR9170_TX_MAC_ENCR_AES … #define AR9170_TX_MAC_MMIC … #define AR9170_TX_MAC_HW_DURATION … #define AR9170_TX_MAC_QOS_S … #define AR9170_TX_MAC_QOS … #define AR9170_TX_MAC_DISABLE_TXOP … #define AR9170_TX_MAC_TXOP_RIFS … #define AR9170_TX_MAC_IMM_BA … /* either-or */ #define AR9170_TX_PHY_MOD_CCK … #define AR9170_TX_PHY_MOD_OFDM … #define AR9170_TX_PHY_MOD_HT … /* depends on modulation */ #define AR9170_TX_PHY_SHORT_PREAMBLE … #define AR9170_TX_PHY_GREENFIELD … #define AR9170_TX_PHY_BW_S … #define AR9170_TX_PHY_BW … #define AR9170_TX_PHY_BW_20MHZ … #define AR9170_TX_PHY_BW_40MHZ … #define AR9170_TX_PHY_BW_40MHZ_DUP … #define AR9170_TX_PHY_TX_HEAVY_CLIP_S … #define AR9170_TX_PHY_TX_HEAVY_CLIP … #define AR9170_TX_PHY_TX_PWR_S … #define AR9170_TX_PHY_TX_PWR … #define AR9170_TX_PHY_TXCHAIN_S … #define AR9170_TX_PHY_TXCHAIN … #define AR9170_TX_PHY_TXCHAIN_1 … /* use for cck, ofdm 6/9/12/18/24 and HT if capable */ #define AR9170_TX_PHY_TXCHAIN_2 … #define AR9170_TX_PHY_MCS_S … #define AR9170_TX_PHY_MCS … #define AR9170_TX_PHY_RATE_CCK_1M … #define AR9170_TX_PHY_RATE_CCK_2M … #define AR9170_TX_PHY_RATE_CCK_5M … #define AR9170_TX_PHY_RATE_CCK_11M … /* same as AR9170_RX_PHY_RATE */ #define AR9170_TXRX_PHY_RATE_OFDM_6M … #define AR9170_TXRX_PHY_RATE_OFDM_9M … #define AR9170_TXRX_PHY_RATE_OFDM_12M … #define AR9170_TXRX_PHY_RATE_OFDM_18M … #define AR9170_TXRX_PHY_RATE_OFDM_24M … #define AR9170_TXRX_PHY_RATE_OFDM_36M … #define AR9170_TXRX_PHY_RATE_OFDM_48M … #define AR9170_TXRX_PHY_RATE_OFDM_54M … #define AR9170_TXRX_PHY_RATE_HT_MCS0 … #define AR9170_TXRX_PHY_RATE_HT_MCS1 … #define AR9170_TXRX_PHY_RATE_HT_MCS2 … #define AR9170_TXRX_PHY_RATE_HT_MCS3 … #define AR9170_TXRX_PHY_RATE_HT_MCS4 … #define AR9170_TXRX_PHY_RATE_HT_MCS5 … #define AR9170_TXRX_PHY_RATE_HT_MCS6 … #define AR9170_TXRX_PHY_RATE_HT_MCS7 … #define AR9170_TXRX_PHY_RATE_HT_MCS8 … #define AR9170_TXRX_PHY_RATE_HT_MCS9 … #define AR9170_TXRX_PHY_RATE_HT_MCS10 … #define AR9170_TXRX_PHY_RATE_HT_MCS11 … #define AR9170_TXRX_PHY_RATE_HT_MCS12 … #define AR9170_TXRX_PHY_RATE_HT_MCS13 … #define AR9170_TXRX_PHY_RATE_HT_MCS14 … #define AR9170_TXRX_PHY_RATE_HT_MCS15 … #define AR9170_TX_PHY_SHORT_GI … #ifdef __CARL9170FW__ struct ar9170_tx_hw_mac_control { union { struct { /* * Beware of compiler bugs in all gcc pre 4.4! */ u8 erp_prot:2; u8 no_ack:1; u8 backoff:1; u8 burst:1; u8 ampdu:1; u8 enc_mode:2; u8 hw_mmic:1; u8 hw_duration:1; u8 qos_queue:2; u8 disable_txop:1; u8 txop_rifs:1; u8 ba_end:1; u8 probe:1; } __packed; __le16 set; } __packed; } __packed; struct ar9170_tx_hw_phy_control { union { struct { /* * Beware of compiler bugs in all gcc pre 4.4! */ u8 modulation:2; u8 preamble:1; u8 bandwidth:2; u8:1; u8 heavy_clip:3; u8 tx_power:6; u8 chains:3; u8 mcs:7; u8:6; u8 short_gi:1; } __packed; __le32 set; } __packed; } __packed; struct ar9170_tx_rate_info { u8 tries:3; u8 erp_prot:2; u8 ampdu:1; u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */ } __packed; struct carl9170_tx_superdesc { __le16 len; u8 rix; u8 cnt; u8 cookie; u8 ampdu_density:3; u8 ampdu_factor:2; u8 ampdu_commit_density:1; u8 ampdu_commit_factor:1; u8 ampdu_unused_bit:1; u8 queue:2; u8 assign_seq:1; u8 vif_id:3; u8 fill_in_tsf:1; u8 cab:1; u8 padding2; struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES]; struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES]; } __packed; struct ar9170_tx_hwdesc { __le16 length; struct ar9170_tx_hw_mac_control mac; struct ar9170_tx_hw_phy_control phy; } __packed; struct ar9170_tx_frame { struct ar9170_tx_hwdesc hdr; union { struct ieee80211_hdr i3e; DECLARE_FLEX_ARRAY(u8, payload); } data; } __packed; struct carl9170_tx_superframe { struct carl9170_tx_superdesc s; struct ar9170_tx_frame f; } __packed __aligned(4); #endif /* __CARL9170FW__ */ struct _ar9170_tx_hwdesc { … } __packed; #define CARL9170_TX_SUPER_AMPDU_DENSITY_S … #define CARL9170_TX_SUPER_AMPDU_DENSITY … #define CARL9170_TX_SUPER_AMPDU_FACTOR … #define CARL9170_TX_SUPER_AMPDU_FACTOR_S … #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY … #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S … #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR … #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S … #define CARL9170_TX_SUPER_MISC_QUEUE … #define CARL9170_TX_SUPER_MISC_QUEUE_S … #define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ … #define CARL9170_TX_SUPER_MISC_VIF_ID … #define CARL9170_TX_SUPER_MISC_VIF_ID_S … #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF … #define CARL9170_TX_SUPER_MISC_CAB … #define CARL9170_TX_SUPER_RI_TRIES … #define CARL9170_TX_SUPER_RI_TRIES_S … #define CARL9170_TX_SUPER_RI_ERP_PROT … #define CARL9170_TX_SUPER_RI_ERP_PROT_S … #define CARL9170_TX_SUPER_RI_AMPDU … #define CARL9170_TX_SUPER_RI_AMPDU_S … struct _carl9170_tx_superdesc { … } __packed; struct _carl9170_tx_superframe { … } __packed __aligned(…); #define CARL9170_TX_SUPERDESC_LEN … #define AR9170_TX_HWDESC_LEN … #define CARL9170_TX_SUPERFRAME_LEN … struct ar9170_rx_head { … } __packed; #define AR9170_RX_HEAD_LEN … struct ar9170_rx_phystatus { … } __packed; #define AR9170_RX_PHYSTATUS_LEN … struct ar9170_rx_macstatus { … } __packed; #define AR9170_RX_MACSTATUS_LEN … struct ar9170_rx_frame_single { … }; struct ar9170_rx_frame_head { … }; struct ar9170_rx_frame_middle { … }; struct ar9170_rx_frame_tail { … }; struct ar9170_rx_frame { … }; static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t) { … } /* * This is an workaround for several undocumented bugs. * Don't mess with the QoS/AC <-> HW Queue map, if you don't * know what you are doing. * * Known problems [hardware]: * * The MAC does not aggregate frames on anything other * than the first HW queue. * * when an AMPDU is placed [in the first hw queue] and * additional frames are already queued on a different * hw queue, the MAC will ALWAYS freeze. * * In a nutshell: The hardware can either do QoS or * Aggregation but not both at the same time. As a * result, this makes the device pretty much useless * for any serious 802.11n setup. */ enum ar9170_txq { … }; #define AR9170_TXQ_DEPTH … #endif /* __CARL9170_SHARED_WLAN_H */
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