/* * Shared Atheros AR9170 Header * * PHY register map * * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef __CARL9170_SHARED_PHY_H #define __CARL9170_SHARED_PHY_H #define AR9170_PHY_REG_BASE … #define AR9170_PHY_REG(_n) … #define AR9170_PHY_REG_TEST … #define AR9170_PHY_TEST_AGC_CLR … #define AR9170_PHY_TEST_RFSILENT_BB … #define AR9170_PHY_REG_TURBO … #define AR9170_PHY_TURBO_FC_TURBO_MODE … #define AR9170_PHY_TURBO_FC_TURBO_SHORT … #define AR9170_PHY_TURBO_FC_DYN2040_EN … #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY … #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH … /* For 25 MHz channel spacing -- not used but supported by hw */ #define AR9170_PHY_TURBO_FC_DYN2040_EXT_CH … #define AR9170_PHY_TURBO_FC_HT_EN … #define AR9170_PHY_TURBO_FC_SHORT_GI_40 … #define AR9170_PHY_TURBO_FC_WALSH … #define AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 … #define AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO … #define AR9170_PHY_REG_TEST2 … #define AR9170_PHY_REG_TIMING2 … #define AR9170_PHY_TIMING2_USE_FORCE … #define AR9170_PHY_TIMING2_FORCE … #define AR9170_PHY_TIMING2_FORCE_S … #define AR9170_PHY_REG_TIMING3 … #define AR9170_PHY_TIMING3_DSC_EXP … #define AR9170_PHY_TIMING3_DSC_EXP_S … #define AR9170_PHY_TIMING3_DSC_MAN … #define AR9170_PHY_TIMING3_DSC_MAN_S … #define AR9170_PHY_REG_CHIP_ID … #define AR9170_PHY_CHIP_ID_REV_0 … #define AR9170_PHY_CHIP_ID_REV_1 … #define AR9170_PHY_CHIP_ID_9160_REV_0 … #define AR9170_PHY_REG_ACTIVE … #define AR9170_PHY_ACTIVE_EN … #define AR9170_PHY_ACTIVE_DIS … #define AR9170_PHY_REG_RF_CTL2 … #define AR9170_PHY_RF_CTL2_TX_END_DATA_START … #define AR9170_PHY_RF_CTL2_TX_END_DATA_START_S … #define AR9170_PHY_RF_CTL2_TX_END_PA_ON … #define AR9170_PHY_RF_CTL2_TX_END_PA_ON_S … #define AR9170_PHY_REG_RF_CTL3 … #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON … #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S … #define AR9170_PHY_REG_ADC_CTL … #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN … #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S … #define AR9170_PHY_ADC_CTL_OFF_PWDDAC … #define AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP … #define AR9170_PHY_ADC_CTL_OFF_PWDADC … #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN … #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S … #define AR9170_PHY_REG_ADC_SERIAL_CTL … #define AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC … #define AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO … #define AR9170_PHY_REG_RF_CTL4 … #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF … #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S … #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF … #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S … #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON … #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S … #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON … #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S … #define AR9170_PHY_REG_TSTDAC_CONST … #define AR9170_PHY_REG_SETTLING … #define AR9170_PHY_SETTLING_SWITCH … #define AR9170_PHY_SETTLING_SWITCH_S … #define AR9170_PHY_REG_RXGAIN … #define AR9170_PHY_REG_RXGAIN_CHAIN_2 … #define AR9170_PHY_RXGAIN_TXRX_ATTEN … #define AR9170_PHY_RXGAIN_TXRX_ATTEN_S … #define AR9170_PHY_RXGAIN_TXRX_RF_MAX … #define AR9170_PHY_RXGAIN_TXRX_RF_MAX_S … #define AR9170_PHY_REG_DESIRED_SZ … #define AR9170_PHY_DESIRED_SZ_ADC … #define AR9170_PHY_DESIRED_SZ_ADC_S … #define AR9170_PHY_DESIRED_SZ_PGA … #define AR9170_PHY_DESIRED_SZ_PGA_S … #define AR9170_PHY_DESIRED_SZ_TOT_DES … #define AR9170_PHY_DESIRED_SZ_TOT_DES_S … #define AR9170_PHY_REG_FIND_SIG … #define AR9170_PHY_FIND_SIG_FIRSTEP … #define AR9170_PHY_FIND_SIG_FIRSTEP_S … #define AR9170_PHY_FIND_SIG_FIRPWR … #define AR9170_PHY_FIND_SIG_FIRPWR_S … #define AR9170_PHY_REG_AGC_CTL1 … #define AR9170_PHY_AGC_CTL1_COARSE_LOW … #define AR9170_PHY_AGC_CTL1_COARSE_LOW_S … #define AR9170_PHY_AGC_CTL1_COARSE_HIGH … #define AR9170_PHY_AGC_CTL1_COARSE_HIGH_S … #define AR9170_PHY_REG_AGC_CONTROL … #define AR9170_PHY_AGC_CONTROL_CAL … #define AR9170_PHY_AGC_CONTROL_NF … #define AR9170_PHY_AGC_CONTROL_ENABLE_NF … #define AR9170_PHY_AGC_CONTROL_FLTR_CAL … #define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF … #define AR9170_PHY_REG_CCA … #define AR9170_PHY_CCA_MIN_PWR … #define AR9170_PHY_CCA_MIN_PWR_S … #define AR9170_PHY_CCA_THRESH62 … #define AR9170_PHY_CCA_THRESH62_S … #define AR9170_PHY_REG_SFCORR … #define AR9170_PHY_SFCORR_M2COUNT_THR … #define AR9170_PHY_SFCORR_M2COUNT_THR_S … #define AR9170_PHY_SFCORR_M1_THRESH … #define AR9170_PHY_SFCORR_M1_THRESH_S … #define AR9170_PHY_SFCORR_M2_THRESH … #define AR9170_PHY_SFCORR_M2_THRESH_S … #define AR9170_PHY_REG_SFCORR_LOW … #define AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW … #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW … #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S … #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW … #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S … #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW … #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S … #define AR9170_PHY_REG_SLEEP_CTR_CONTROL … #define AR9170_PHY_REG_SLEEP_CTR_LIMIT … #define AR9170_PHY_REG_SLEEP_SCAL … #define AR9170_PHY_REG_PLL_CTL … #define AR9170_PHY_PLL_CTL_40 … #define AR9170_PHY_PLL_CTL_40_5413 … #define AR9170_PHY_PLL_CTL_44 … #define AR9170_PHY_PLL_CTL_44_2133 … #define AR9170_PHY_PLL_CTL_40_2133 … #define AR9170_PHY_REG_BIN_MASK_1 … #define AR9170_PHY_REG_BIN_MASK_2 … #define AR9170_PHY_REG_BIN_MASK_3 … #define AR9170_PHY_REG_MASK_CTL … /* analogue power on time (100ns) */ #define AR9170_PHY_REG_RX_DELAY … #define AR9170_PHY_REG_SEARCH_START_DELAY … #define AR9170_PHY_RX_DELAY_DELAY … #define AR9170_PHY_REG_TIMING_CTRL4(_i) … #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF … #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S … #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF … #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S … #define AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE … #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX … #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S … #define AR9170_PHY_TIMING_CTRL4_DO_IQCAL … #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI … #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER … #define AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK … #define AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK … #define AR9170_PHY_REG_TIMING5 … #define AR9170_PHY_TIMING5_CYCPWR_THR1 … #define AR9170_PHY_TIMING5_CYCPWR_THR1_S … #define AR9170_PHY_REG_POWER_TX_RATE1 … #define AR9170_PHY_REG_POWER_TX_RATE2 … #define AR9170_PHY_REG_POWER_TX_RATE_MAX … #define AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE … #define AR9170_PHY_REG_FRAME_CTL … #define AR9170_PHY_FRAME_CTL_TX_CLIP … #define AR9170_PHY_FRAME_CTL_TX_CLIP_S … #define AR9170_PHY_REG_SPUR_REG … #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL … #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S … #define AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM … #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT … #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S … #define AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI … #define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH … #define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S … #define AR9170_PHY_REG_RADAR_EXT … #define AR9170_PHY_RADAR_EXT_ENA … #define AR9170_PHY_REG_RADAR_0 … #define AR9170_PHY_RADAR_0_ENA … #define AR9170_PHY_RADAR_0_FFT_ENA … /* inband pulse threshold */ #define AR9170_PHY_RADAR_0_INBAND … #define AR9170_PHY_RADAR_0_INBAND_S … /* pulse RSSI threshold */ #define AR9170_PHY_RADAR_0_PRSSI … #define AR9170_PHY_RADAR_0_PRSSI_S … /* pulse height threshold */ #define AR9170_PHY_RADAR_0_HEIGHT … #define AR9170_PHY_RADAR_0_HEIGHT_S … /* radar RSSI threshold */ #define AR9170_PHY_RADAR_0_RRSSI … #define AR9170_PHY_RADAR_0_RRSSI_S … /* radar firepower threshold */ #define AR9170_PHY_RADAR_0_FIRPWR … #define AR9170_PHY_RADAR_0_FIRPWR_S … #define AR9170_PHY_REG_RADAR_1 … #define AR9170_PHY_RADAR_1_RELPWR_ENA … #define AR9170_PHY_RADAR_1_USE_FIR128 … #define AR9170_PHY_RADAR_1_RELPWR_THRESH … #define AR9170_PHY_RADAR_1_RELPWR_THRESH_S … #define AR9170_PHY_RADAR_1_BLOCK_CHECK … #define AR9170_PHY_RADAR_1_MAX_RRSSI … #define AR9170_PHY_RADAR_1_RELSTEP_CHECK … #define AR9170_PHY_RADAR_1_RELSTEP_THRESH … #define AR9170_PHY_RADAR_1_RELSTEP_THRESH_S … #define AR9170_PHY_RADAR_1_MAXLEN … #define AR9170_PHY_RADAR_1_MAXLEN_S … #define AR9170_PHY_REG_SWITCH_CHAIN_0 … #define AR9170_PHY_REG_SWITCH_CHAIN_2 … #define AR9170_PHY_REG_SWITCH_COM … #define AR9170_PHY_REG_CCA_THRESHOLD … #define AR9170_PHY_REG_SIGMA_DELTA … #define AR9170_PHY_SIGMA_DELTA_ADC_SEL … #define AR9170_PHY_SIGMA_DELTA_ADC_SEL_S … #define AR9170_PHY_SIGMA_DELTA_FILT2 … #define AR9170_PHY_SIGMA_DELTA_FILT2_S … #define AR9170_PHY_SIGMA_DELTA_FILT1 … #define AR9170_PHY_SIGMA_DELTA_FILT1_S … #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP … #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S … #define AR9170_PHY_REG_RESTART … #define AR9170_PHY_RESTART_DIV_GC … #define AR9170_PHY_RESTART_DIV_GC_S … #define AR9170_PHY_REG_RFBUS_REQ … #define AR9170_PHY_RFBUS_REQ_EN … #define AR9170_PHY_REG_TIMING7 … #define AR9170_PHY_REG_TIMING8 … #define AR9170_PHY_TIMING8_PILOT_MASK_2 … #define AR9170_PHY_TIMING8_PILOT_MASK_2_S … #define AR9170_PHY_REG_BIN_MASK2_1 … #define AR9170_PHY_REG_BIN_MASK2_2 … #define AR9170_PHY_REG_BIN_MASK2_3 … #define AR9170_PHY_REG_BIN_MASK2_4 … #define AR9170_PHY_BIN_MASK2_4_MASK_4 … #define AR9170_PHY_BIN_MASK2_4_MASK_4_S … #define AR9170_PHY_REG_TIMING9 … #define AR9170_PHY_REG_TIMING10 … #define AR9170_PHY_TIMING10_PILOT_MASK_2 … #define AR9170_PHY_TIMING10_PILOT_MASK_2_S … #define AR9170_PHY_REG_TIMING11 … #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE … #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S … #define AR9170_PHY_TIMING11_SPUR_FREQ_SD … #define AR9170_PHY_TIMING11_SPUR_FREQ_SD_S … #define AR9170_PHY_TIMING11_USE_SPUR_IN_AGC … #define AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR … #define AR9170_PHY_REG_RX_CHAINMASK … #define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) … #define AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE … #define AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE … #define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL … #define AR9170_PHY_9285_ANT_DIV_CTL_ALL … #define AR9170_PHY_9285_ANT_DIV_CTL … #define AR9170_PHY_9285_ANT_DIV_CTL_S … #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF … #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S … #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF … #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S … #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB … #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S … #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB … #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S … #define AR9170_PHY_9285_ANT_DIV_LNA1 … #define AR9170_PHY_9285_ANT_DIV_LNA2 … #define AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 … #define AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 … #define AR9170_PHY_9285_ANT_DIV_GAINTB_0 … #define AR9170_PHY_9285_ANT_DIV_GAINTB_1 … #define AR9170_PHY_REG_EXT_CCA0 … #define AR9170_PHY_REG_EXT_CCA0_THRESH62 … #define AR9170_PHY_REG_EXT_CCA0_THRESH62_S … #define AR9170_PHY_REG_EXT_CCA … #define AR9170_PHY_EXT_CCA_CYCPWR_THR1 … #define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S … #define AR9170_PHY_EXT_CCA_THRESH62 … #define AR9170_PHY_EXT_CCA_THRESH62_S … #define AR9170_PHY_EXT_CCA_MIN_PWR … #define AR9170_PHY_EXT_CCA_MIN_PWR_S … #define AR9170_PHY_REG_SFCORR_EXT … #define AR9170_PHY_SFCORR_EXT_M1_THRESH … #define AR9170_PHY_SFCORR_EXT_M1_THRESH_S … #define AR9170_PHY_SFCORR_EXT_M2_THRESH … #define AR9170_PHY_SFCORR_EXT_M2_THRESH_S … #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW … #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S … #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW … #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S … #define AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S … #define AR9170_PHY_REG_HALFGI … #define AR9170_PHY_HALFGI_DSC_MAN … #define AR9170_PHY_HALFGI_DSC_MAN_S … #define AR9170_PHY_HALFGI_DSC_EXP … #define AR9170_PHY_HALFGI_DSC_EXP_S … #define AR9170_PHY_REG_CHANNEL_MASK_01_30 … #define AR9170_PHY_REG_CHANNEL_MASK_31_60 … #define AR9170_PHY_REG_CHAN_INFO_MEMORY … #define AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK … #define AR9170_PHY_REG_HEAVY_CLIP_ENABLE … #define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS … #define AR9170_PHY_RIFS_INIT_DELAY … #define AR9170_PHY_REG_CALMODE … #define AR9170_PHY_CALMODE_IQ … #define AR9170_PHY_CALMODE_ADC_GAIN … #define AR9170_PHY_CALMODE_ADC_DC_PER … #define AR9170_PHY_CALMODE_ADC_DC_INIT … #define AR9170_PHY_REG_REFCLKDLY … #define AR9170_PHY_REG_REFCLKPD … #define AR9170_PHY_REG_CAL_MEAS_0(_i) … #define AR9170_PHY_REG_CAL_MEAS_1(_i) … #define AR9170_PHY_REG_CAL_MEAS_2(_i) … #define AR9170_PHY_REG_CAL_MEAS_3(_i) … #define AR9170_PHY_REG_CURRENT_RSSI … #define AR9170_PHY_REG_RFBUS_GRANT … #define AR9170_PHY_RFBUS_GRANT_EN … #define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF … #define AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT … #define AR9170_PHY_REG_CHAN_INFO_GAIN … #define AR9170_PHY_REG_MODE … #define AR9170_PHY_MODE_ASYNCFIFO … #define AR9170_PHY_MODE_AR2133 … #define AR9170_PHY_MODE_AR5111 … #define AR9170_PHY_MODE_AR5112 … #define AR9170_PHY_MODE_DYNAMIC … #define AR9170_PHY_MODE_RF2GHZ … #define AR9170_PHY_MODE_RF5GHZ … #define AR9170_PHY_MODE_CCK … #define AR9170_PHY_MODE_OFDM … #define AR9170_PHY_MODE_DYN_CCK_DISABLE … #define AR9170_PHY_REG_CCK_TX_CTRL … #define AR9170_PHY_CCK_TX_CTRL_JAPAN … #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK … #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S … #define AR9170_PHY_REG_CCK_DETECT … #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK … #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S … /* [12:6] settling time for antenna switch */ #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME … #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S … #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV … #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S … #define AR9170_PHY_REG_GAIN_2GHZ … #define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 … #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN … #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S … #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN … #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S … #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN … #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S … #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN … #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S … #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN … #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S … #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB … #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S … #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB … #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S … #define AR9170_PHY_REG_CCK_RXCTRL4 … #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT … #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S … #define AR9170_PHY_REG_DAG_CTRLCCK … #define AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR … #define AR9170_REG_DAG_CTRLCCK_RSSI_THR … #define AR9170_REG_DAG_CTRLCCK_RSSI_THR_S … #define AR9170_PHY_REG_FORCE_CLKEN_CCK … #define AR9170_FORCE_CLKEN_CCK_MRC_MUX … #define AR9170_PHY_REG_POWER_TX_RATE3 … #define AR9170_PHY_REG_POWER_TX_RATE4 … #define AR9170_PHY_REG_SCRM_SEQ_XR … #define AR9170_PHY_REG_HEADER_DETECT_XR … #define AR9170_PHY_REG_CHIRP_DETECTED_XR … #define AR9170_PHY_REG_BLUETOOTH … #define AR9170_PHY_REG_TPCRG1 … #define AR9170_PHY_TPCRG1_NUM_PD_GAIN … #define AR9170_PHY_TPCRG1_NUM_PD_GAIN_S … #define AR9170_PHY_TPCRG1_PD_GAIN_1 … #define AR9170_PHY_TPCRG1_PD_GAIN_1_S … #define AR9170_PHY_TPCRG1_PD_GAIN_2 … #define AR9170_PHY_TPCRG1_PD_GAIN_2_S … #define AR9170_PHY_TPCRG1_PD_GAIN_3 … #define AR9170_PHY_TPCRG1_PD_GAIN_3_S … #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE … #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S … #define AR9170_PHY_REG_TX_PWRCTRL4 … #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID … #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S … #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT … #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S … #define AR9170_PHY_REG_ANALOG_SWAP … #define AR9170_PHY_ANALOG_SWAP_AB … #define AR9170_PHY_ANALOG_SWAP_ALT_CHAIN … #define AR9170_PHY_REG_TPCRG5 … #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP … #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 … #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S … #define AR9170_PHY_REG_TX_PWRCTRL6_0 … #define AR9170_PHY_REG_TX_PWRCTRL6_1 … #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE … #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S … #define AR9170_PHY_REG_TX_PWRCTRL7 … #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN … #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S … #define AR9170_PHY_REG_TX_PWRCTRL9 … #define AR9170_PHY_TX_DESIRED_SCALE_CCK … #define AR9170_PHY_TX_DESIRED_SCALE_CCK_S … #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL … #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S … #define AR9170_PHY_REG_TX_GAIN_TBL1 … #define AR9170_PHY_TX_GAIN … #define AR9170_PHY_TX_GAIN_S … /* Carrier leak calibration control, do it after AGC calibration */ #define AR9170_PHY_REG_CL_CAL_CTL … #define AR9170_PHY_CL_CAL_ENABLE … #define AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE … #define AR9170_PHY_REG_POWER_TX_RATE5 … #define AR9170_PHY_REG_POWER_TX_RATE6 … #define AR9170_PHY_REG_CH0_TX_PWRCTRL11 … #define AR9170_PHY_REG_CH1_TX_PWRCTRL11 … #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP … #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S … #define AR9170_PHY_REG_CAL_CHAINMASK … #define AR9170_PHY_REG_VIT_MASK2_M_46_61 … #define AR9170_PHY_REG_MASK2_M_31_45 … #define AR9170_PHY_REG_MASK2_M_16_30 … #define AR9170_PHY_REG_MASK2_M_00_15 … #define AR9170_PHY_REG_PILOT_MASK_01_30 … #define AR9170_PHY_REG_PILOT_MASK_31_60 … #define AR9170_PHY_REG_MASK2_P_15_01 … #define AR9170_PHY_REG_MASK2_P_30_16 … #define AR9170_PHY_REG_MASK2_P_45_31 … #define AR9170_PHY_REG_MASK2_P_61_45 … #define AR9170_PHY_REG_POWER_TX_SUB … #define AR9170_PHY_REG_POWER_TX_RATE7 … #define AR9170_PHY_REG_POWER_TX_RATE8 … #define AR9170_PHY_REG_POWER_TX_RATE9 … #define AR9170_PHY_REG_XPA_CFG … #define AR9170_PHY_FORCE_XPA_CFG … #define AR9170_PHY_FORCE_XPA_CFG_S … #define AR9170_PHY_REG_CH1_CCA … #define AR9170_PHY_CH1_CCA_MIN_PWR … #define AR9170_PHY_CH1_CCA_MIN_PWR_S … #define AR9170_PHY_REG_CH2_CCA … #define AR9170_PHY_CH2_CCA_MIN_PWR … #define AR9170_PHY_CH2_CCA_MIN_PWR_S … #define AR9170_PHY_REG_CH1_EXT_CCA … #define AR9170_PHY_CH1_EXT_CCA_MIN_PWR … #define AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S … #define AR9170_PHY_REG_CH2_EXT_CCA … #define AR9170_PHY_CH2_EXT_CCA_MIN_PWR … #define AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S … #endif /* __CARL9170_SHARED_PHY_H */
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