/* * Copyright (c) 2004-2010 Atheros Communications Inc. * Copyright (c) 2011 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef TARGET_H #define TARGET_H #define AR6003_BOARD_DATA_SZ … #define AR6003_BOARD_EXT_DATA_SZ … #define AR6003_BOARD_EXT_DATA_SZ_V2 … #define AR6004_BOARD_DATA_SZ … #define AR6004_BOARD_EXT_DATA_SZ … #define RESET_CONTROL_ADDRESS … #define RESET_CONTROL_COLD_RST … #define RESET_CONTROL_MBOX_RST … #define CPU_CLOCK_STANDARD_S … #define CPU_CLOCK_STANDARD … #define CPU_CLOCK_ADDRESS … #define CLOCK_CONTROL_ADDRESS … #define CLOCK_CONTROL_LF_CLK32_S … #define CLOCK_CONTROL_LF_CLK32 … #define SYSTEM_SLEEP_ADDRESS … #define SYSTEM_SLEEP_DISABLE_S … #define SYSTEM_SLEEP_DISABLE … #define LPO_CAL_ADDRESS … #define LPO_CAL_ENABLE_S … #define LPO_CAL_ENABLE … #define GPIO_PIN9_ADDRESS … #define GPIO_PIN10_ADDRESS … #define GPIO_PIN11_ADDRESS … #define GPIO_PIN12_ADDRESS … #define GPIO_PIN13_ADDRESS … #define HOST_INT_STATUS_ADDRESS … #define HOST_INT_STATUS_ERROR_S … #define HOST_INT_STATUS_ERROR … #define HOST_INT_STATUS_CPU_S … #define HOST_INT_STATUS_CPU … #define HOST_INT_STATUS_COUNTER_S … #define HOST_INT_STATUS_COUNTER … #define CPU_INT_STATUS_ADDRESS … #define ERROR_INT_STATUS_ADDRESS … #define ERROR_INT_STATUS_WAKEUP_S … #define ERROR_INT_STATUS_WAKEUP … #define ERROR_INT_STATUS_RX_UNDERFLOW_S … #define ERROR_INT_STATUS_RX_UNDERFLOW … #define ERROR_INT_STATUS_TX_OVERFLOW_S … #define ERROR_INT_STATUS_TX_OVERFLOW … #define COUNTER_INT_STATUS_ADDRESS … #define COUNTER_INT_STATUS_COUNTER_S … #define COUNTER_INT_STATUS_COUNTER … #define RX_LOOKAHEAD_VALID_ADDRESS … #define INT_STATUS_ENABLE_ADDRESS … #define INT_STATUS_ENABLE_ERROR_S … #define INT_STATUS_ENABLE_ERROR … #define INT_STATUS_ENABLE_CPU_S … #define INT_STATUS_ENABLE_CPU … #define INT_STATUS_ENABLE_INT_S … #define INT_STATUS_ENABLE_INT … #define INT_STATUS_ENABLE_COUNTER_S … #define INT_STATUS_ENABLE_COUNTER … #define INT_STATUS_ENABLE_MBOX_DATA_S … #define INT_STATUS_ENABLE_MBOX_DATA … #define CPU_INT_STATUS_ENABLE_ADDRESS … #define CPU_INT_STATUS_ENABLE_BIT_S … #define CPU_INT_STATUS_ENABLE_BIT … #define ERROR_STATUS_ENABLE_ADDRESS … #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S … #define ERROR_STATUS_ENABLE_RX_UNDERFLOW … #define ERROR_STATUS_ENABLE_TX_OVERFLOW_S … #define ERROR_STATUS_ENABLE_TX_OVERFLOW … #define COUNTER_INT_STATUS_ENABLE_ADDRESS … #define COUNTER_INT_STATUS_ENABLE_BIT_S … #define COUNTER_INT_STATUS_ENABLE_BIT … #define COUNT_ADDRESS … #define COUNT_DEC_ADDRESS … #define WINDOW_DATA_ADDRESS … #define WINDOW_WRITE_ADDR_ADDRESS … #define WINDOW_READ_ADDR_ADDRESS … #define CPU_DBG_SEL_ADDRESS … #define CPU_DBG_ADDRESS … #define LOCAL_SCRATCH_ADDRESS … #define ATH6KL_OPTION_SLEEP_DISABLE … #define RTC_BASE_ADDRESS … #define GPIO_BASE_ADDRESS … #define MBOX_BASE_ADDRESS … #define ANALOG_INTF_BASE_ADDRESS … /* real name of the register is unknown */ #define ATH6KL_ANALOG_PLL_REGISTER … #define SM(f, v) … #define MS(f, v) … /* * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the * host_interest structure. * * Host Interest is shared between Host and Target in order to coordinate * between the two, and is intended to remain constant (with additions only * at the end). */ #define ATH6KL_AR6003_HI_START_ADDR … #define ATH6KL_AR6004_HI_START_ADDR … /* * These are items that the Host may need to access * via BMI or via the Diagnostic Window. The position * of items in this structure must remain constant. * across firmware revisions! * * Types for each item must be fixed size across target and host platforms. * The structure is used only to calculate offset for each register with * HI_ITEM() macro, no values are stored to it. * * More items may be added at the end. */ struct host_interest { … } __packed; #define HI_ITEM(item) … #define HI_OPTION_MAC_ADDR_METHOD_SHIFT … #define HI_OPTION_FW_MODE_IBSS … #define HI_OPTION_FW_MODE_BSS_STA … #define HI_OPTION_FW_MODE_AP … #define HI_OPTION_FW_SUBMODE_NONE … #define HI_OPTION_FW_SUBMODE_P2PDEV … #define HI_OPTION_FW_SUBMODE_P2PCLIENT … #define HI_OPTION_FW_SUBMODE_P2PGO … #define HI_OPTION_NUM_DEV_SHIFT … #define HI_OPTION_FW_BRIDGE_SHIFT … /* Fw Mode/SubMode Mask |------------------------------------------------------------------------------| | SUB | SUB | SUB | SUB | | | | | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |------------------------------------------------------------------------------| */ #define HI_OPTION_FW_MODE_BITS … #define HI_OPTION_FW_MODE_SHIFT … #define HI_OPTION_FW_SUBMODE_BITS … #define HI_OPTION_FW_SUBMODE_SHIFT … /* Convert a Target virtual address into a Target physical address */ #define AR6003_VTOP(vaddr) … #define AR6004_VTOP(vaddr) … #define TARG_VTOP(target_type, vaddr) … #define ATH6KL_FWLOG_PAYLOAD_SIZE … struct ath6kl_dbglog_buf { … } __packed; struct ath6kl_dbglog_hdr { … } __packed; #endif
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