/* * Header for MultiMediaCard (MMC) * * Copyright 2002 Hewlett-Packard Company * * Use consistent with the GNU GPL is permitted, * provided that this copyright notice is * preserved in its entirety in all copies and derived works. * * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS * FITNESS FOR ANY PARTICULAR PURPOSE. * * Many thanks to Alessandro Rubini and Jonathan Corbet! * * Based strongly on code by: * * Author: Yong-iL Joh <[email protected]> * * Author: Andrew Christian * 15 May 2002 */ #ifndef LINUX_MMC_MMC_H #define LINUX_MMC_MMC_H #include <linux/types.h> /* Standard MMC commands (4.1) type argument response */ /* class 1 */ #define MMC_GO_IDLE_STATE … #define MMC_SEND_OP_COND … #define MMC_ALL_SEND_CID … #define MMC_SET_RELATIVE_ADDR … #define MMC_SET_DSR … #define MMC_SLEEP_AWAKE … #define MMC_SWITCH … #define MMC_SELECT_CARD … #define MMC_SEND_EXT_CSD … #define MMC_SEND_CSD … #define MMC_SEND_CID … #define MMC_READ_DAT_UNTIL_STOP … #define MMC_STOP_TRANSMISSION … #define MMC_SEND_STATUS … #define MMC_BUS_TEST_R … #define MMC_GO_INACTIVE_STATE … #define MMC_BUS_TEST_W … #define MMC_SPI_READ_OCR … #define MMC_SPI_CRC_ON_OFF … /* class 2 */ #define MMC_SET_BLOCKLEN … #define MMC_READ_SINGLE_BLOCK … #define MMC_READ_MULTIPLE_BLOCK … #define MMC_SEND_TUNING_BLOCK … #define MMC_SEND_TUNING_BLOCK_HS200 … /* class 3 */ #define MMC_WRITE_DAT_UNTIL_STOP … /* class 4 */ #define MMC_SET_BLOCK_COUNT … #define MMC_WRITE_BLOCK … #define MMC_WRITE_MULTIPLE_BLOCK … #define MMC_PROGRAM_CID … #define MMC_PROGRAM_CSD … /* class 6 */ #define MMC_SET_WRITE_PROT … #define MMC_CLR_WRITE_PROT … #define MMC_SEND_WRITE_PROT … /* class 5 */ #define MMC_ERASE_GROUP_START … #define MMC_ERASE_GROUP_END … #define MMC_ERASE … /* class 9 */ #define MMC_FAST_IO … #define MMC_GO_IRQ_STATE … /* class 7 */ #define MMC_LOCK_UNLOCK … /* class 8 */ #define MMC_APP_CMD … #define MMC_GEN_CMD … /* class 11 */ #define MMC_QUE_TASK_PARAMS … #define MMC_QUE_TASK_ADDR … #define MMC_EXECUTE_READ_TASK … #define MMC_EXECUTE_WRITE_TASK … #define MMC_CMDQ_TASK_MGMT … static inline bool mmc_op_multi(u32 opcode) { … } static inline bool mmc_op_tuning(u32 opcode) { … } /* * MMC_SWITCH argument format: * * [31:26] Always 0 * [25:24] Access Mode * [23:16] Location of target Byte in EXT_CSD * [15:08] Value Byte * [07:03] Always 0 * [02:00] Command Set */ /* MMC status in R1, for native mode (SPI bits are different) Type e : error bit s : status bit r : detected and set for the actual command response x : detected and set during command execution. the host must poll the card by sending status command in order to read these bits. Clear condition a : according to the card state b : always related to the previous command. Reception of a valid command will clear it (with a delay of one command) c : clear by read */ #define R1_OUT_OF_RANGE … #define R1_ADDRESS_ERROR … #define R1_BLOCK_LEN_ERROR … #define R1_ERASE_SEQ_ERROR … #define R1_ERASE_PARAM … #define R1_WP_VIOLATION … #define R1_CARD_IS_LOCKED … #define R1_LOCK_UNLOCK_FAILED … #define R1_COM_CRC_ERROR … #define R1_ILLEGAL_COMMAND … #define R1_CARD_ECC_FAILED … #define R1_CC_ERROR … #define R1_ERROR … #define R1_UNDERRUN … #define R1_OVERRUN … #define R1_CID_CSD_OVERWRITE … #define R1_WP_ERASE_SKIP … #define R1_CARD_ECC_DISABLED … #define R1_ERASE_RESET … #define R1_STATUS(x) … #define R1_CURRENT_STATE(x) … #define R1_READY_FOR_DATA … #define R1_SWITCH_ERROR … #define R1_EXCEPTION_EVENT … #define R1_APP_CMD … #define R1_STATE_IDLE … #define R1_STATE_READY … #define R1_STATE_IDENT … #define R1_STATE_STBY … #define R1_STATE_TRAN … #define R1_STATE_DATA … #define R1_STATE_RCV … #define R1_STATE_PRG … #define R1_STATE_DIS … static inline bool mmc_ready_for_data(u32 status) { … } /* * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS * R1 is the low order byte; R2 is the next highest byte, when present. */ #define R1_SPI_IDLE … #define R1_SPI_ERASE_RESET … #define R1_SPI_ILLEGAL_COMMAND … #define R1_SPI_COM_CRC … #define R1_SPI_ERASE_SEQ … #define R1_SPI_ADDRESS … #define R1_SPI_PARAMETER … /* R1 bit 7 is always zero */ #define R2_SPI_CARD_LOCKED … #define R2_SPI_WP_ERASE_SKIP … #define R2_SPI_LOCK_UNLOCK_FAIL … #define R2_SPI_ERROR … #define R2_SPI_CC_ERROR … #define R2_SPI_CARD_ECC_ERROR … #define R2_SPI_WP_VIOLATION … #define R2_SPI_ERASE_PARAM … #define R2_SPI_OUT_OF_RANGE … #define R2_SPI_CSD_OVERWRITE … /* * OCR bits are mostly in host.h */ #define MMC_CARD_BUSY … /* * Card Command Classes (CCC) */ #define CCC_BASIC … /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ /* (and for SPI, CMD58,59) */ #define CCC_STREAM_READ … /* (CMD11) */ #define CCC_BLOCK_READ … /* (CMD16,17,18) */ #define CCC_STREAM_WRITE … /* (CMD20) */ #define CCC_BLOCK_WRITE … /* (CMD16,24,25,26,27) */ #define CCC_ERASE … /* (CMD32,33,34,35,36,37,38,39) */ #define CCC_WRITE_PROT … /* (CMD28,29,30) */ #define CCC_LOCK_CARD … /* (CMD16,CMD42) */ #define CCC_APP_SPEC … /* (CMD55,56,57,ACMD*) */ #define CCC_IO_MODE … /* (CMD5,39,40,52,53) */ #define CCC_SWITCH … /* (CMD6,34,35,36,37,50) */ /* (11) Reserved */ /* (CMD?) */ /* * CSD field definitions */ #define CSD_STRUCT_VER_1_0 … #define CSD_STRUCT_VER_1_1 … #define CSD_STRUCT_VER_1_2 … #define CSD_STRUCT_EXT_CSD … #define CSD_SPEC_VER_0 … #define CSD_SPEC_VER_1 … #define CSD_SPEC_VER_2 … #define CSD_SPEC_VER_3 … #define CSD_SPEC_VER_4 … /* * EXT_CSD fields */ #define EXT_CSD_CMDQ_MODE_EN … #define EXT_CSD_FLUSH_CACHE … #define EXT_CSD_CACHE_CTRL … #define EXT_CSD_POWER_OFF_NOTIFICATION … #define EXT_CSD_EXP_EVENTS_STATUS … #define EXT_CSD_EXP_EVENTS_CTRL … #define EXT_CSD_DATA_SECTOR_SIZE … #define EXT_CSD_GP_SIZE_MULT … #define EXT_CSD_PARTITION_SETTING_COMPLETED … #define EXT_CSD_PARTITION_ATTRIBUTE … #define EXT_CSD_PARTITION_SUPPORT … #define EXT_CSD_HPI_MGMT … #define EXT_CSD_RST_N_FUNCTION … #define EXT_CSD_BKOPS_EN … #define EXT_CSD_BKOPS_START … #define EXT_CSD_SANITIZE_START … #define EXT_CSD_WR_REL_PARAM … #define EXT_CSD_RPMB_MULT … #define EXT_CSD_FW_CONFIG … #define EXT_CSD_BOOT_WP … #define EXT_CSD_ERASE_GROUP_DEF … #define EXT_CSD_PART_CONFIG … #define EXT_CSD_ERASED_MEM_CONT … #define EXT_CSD_BUS_WIDTH … #define EXT_CSD_STROBE_SUPPORT … #define EXT_CSD_HS_TIMING … #define EXT_CSD_POWER_CLASS … #define EXT_CSD_REV … #define EXT_CSD_STRUCTURE … #define EXT_CSD_CARD_TYPE … #define EXT_CSD_DRIVER_STRENGTH … #define EXT_CSD_OUT_OF_INTERRUPT_TIME … #define EXT_CSD_PART_SWITCH_TIME … #define EXT_CSD_PWR_CL_52_195 … #define EXT_CSD_PWR_CL_26_195 … #define EXT_CSD_PWR_CL_52_360 … #define EXT_CSD_PWR_CL_26_360 … #define EXT_CSD_SEC_CNT … #define EXT_CSD_S_A_TIMEOUT … #define EXT_CSD_REL_WR_SEC_C … #define EXT_CSD_HC_WP_GRP_SIZE … #define EXT_CSD_ERASE_TIMEOUT_MULT … #define EXT_CSD_HC_ERASE_GRP_SIZE … #define EXT_CSD_BOOT_MULT … #define EXT_CSD_SEC_TRIM_MULT … #define EXT_CSD_SEC_ERASE_MULT … #define EXT_CSD_SEC_FEATURE_SUPPORT … #define EXT_CSD_TRIM_MULT … #define EXT_CSD_PWR_CL_200_195 … #define EXT_CSD_PWR_CL_200_360 … #define EXT_CSD_PWR_CL_DDR_52_195 … #define EXT_CSD_PWR_CL_DDR_52_360 … #define EXT_CSD_BKOPS_STATUS … #define EXT_CSD_POWER_OFF_LONG_TIME … #define EXT_CSD_GENERIC_CMD6_TIME … #define EXT_CSD_CACHE_SIZE … #define EXT_CSD_PWR_CL_DDR_200_360 … #define EXT_CSD_FIRMWARE_VERSION … #define EXT_CSD_PRE_EOL_INFO … #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A … #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B … #define EXT_CSD_CMDQ_DEPTH … #define EXT_CSD_CMDQ_SUPPORT … #define EXT_CSD_SUPPORTED_MODE … #define EXT_CSD_TAG_UNIT_SIZE … #define EXT_CSD_DATA_TAG_SUPPORT … #define EXT_CSD_BKOPS_SUPPORT … #define EXT_CSD_HPI_FEATURES … /* * EXT_CSD field definitions */ #define EXT_CSD_WR_REL_PARAM_EN … #define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR … #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS … #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS … #define EXT_CSD_BOOT_WP_B_PERM_WP_EN … #define EXT_CSD_BOOT_WP_B_PWR_WP_EN … #define EXT_CSD_PART_CONFIG_ACC_MASK … #define EXT_CSD_PART_CONFIG_ACC_BOOT0 … #define EXT_CSD_PART_CONFIG_ACC_RPMB … #define EXT_CSD_PART_CONFIG_ACC_GP0 … #define EXT_CSD_PART_SETTING_COMPLETED … #define EXT_CSD_PART_SUPPORT_PART_EN … #define EXT_CSD_CMD_SET_NORMAL … #define EXT_CSD_CMD_SET_SECURE … #define EXT_CSD_CMD_SET_CPSECURE … #define EXT_CSD_CARD_TYPE_HS_26 … #define EXT_CSD_CARD_TYPE_HS_52 … #define EXT_CSD_CARD_TYPE_HS … #define EXT_CSD_CARD_TYPE_DDR_1_8V … /* DDR mode @1.8V or 3V I/O */ #define EXT_CSD_CARD_TYPE_DDR_1_2V … /* DDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_DDR_52 … #define EXT_CSD_CARD_TYPE_HS200_1_8V … #define EXT_CSD_CARD_TYPE_HS200_1_2V … /* SDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_HS200 … #define EXT_CSD_CARD_TYPE_HS400_1_8V … #define EXT_CSD_CARD_TYPE_HS400_1_2V … #define EXT_CSD_CARD_TYPE_HS400 … #define EXT_CSD_CARD_TYPE_HS400ES … #define EXT_CSD_BUS_WIDTH_1 … #define EXT_CSD_BUS_WIDTH_4 … #define EXT_CSD_BUS_WIDTH_8 … #define EXT_CSD_DDR_BUS_WIDTH_4 … #define EXT_CSD_DDR_BUS_WIDTH_8 … #define EXT_CSD_BUS_WIDTH_STROBE … #define EXT_CSD_TIMING_BC … #define EXT_CSD_TIMING_HS … #define EXT_CSD_TIMING_HS200 … #define EXT_CSD_TIMING_HS400 … #define EXT_CSD_DRV_STR_SHIFT … #define EXT_CSD_SEC_ER_EN … #define EXT_CSD_SEC_BD_BLK_EN … #define EXT_CSD_SEC_GB_CL_EN … #define EXT_CSD_SEC_SANITIZE … #define EXT_CSD_RST_N_EN_MASK … #define EXT_CSD_RST_N_ENABLED … #define EXT_CSD_NO_POWER_NOTIFICATION … #define EXT_CSD_POWER_ON … #define EXT_CSD_POWER_OFF_SHORT … #define EXT_CSD_POWER_OFF_LONG … #define EXT_CSD_PWR_CL_8BIT_MASK … #define EXT_CSD_PWR_CL_4BIT_MASK … #define EXT_CSD_PWR_CL_8BIT_SHIFT … #define EXT_CSD_PWR_CL_4BIT_SHIFT … /* * EXCEPTION_EVENT_STATUS field */ #define EXT_CSD_URGENT_BKOPS … #define EXT_CSD_DYNCAP_NEEDED … #define EXT_CSD_SYSPOOL_EXHAUSTED … /* * BKOPS status level */ #define EXT_CSD_BKOPS_LEVEL_2 … /* * BKOPS modes */ #define EXT_CSD_MANUAL_BKOPS_MASK … #define EXT_CSD_AUTO_BKOPS_MASK … /* * Command Queue */ #define EXT_CSD_CMDQ_MODE_ENABLED … #define EXT_CSD_CMDQ_DEPTH_MASK … #define EXT_CSD_CMDQ_SUPPORTED … /* * MMC_SWITCH access modes */ #define MMC_SWITCH_MODE_CMD_SET … #define MMC_SWITCH_MODE_SET_BITS … #define MMC_SWITCH_MODE_CLEAR_BITS … #define MMC_SWITCH_MODE_WRITE_BYTE … /* * Erase/trim/discard */ #define MMC_ERASE_ARG … #define MMC_SECURE_ERASE_ARG … #define MMC_TRIM_ARG … #define MMC_DISCARD_ARG … #define MMC_SECURE_TRIM1_ARG … #define MMC_SECURE_TRIM2_ARG … #define MMC_SECURE_ARGS … #define MMC_TRIM_OR_DISCARD_ARGS … #define mmc_driver_type_mask(n) … #endif /* LINUX_MMC_MMC_H */
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