/* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2016 Qualcomm Atheros, Inc. */ #ifndef __TARGADDRS_H__ #define __TARGADDRS_H__ #include "hw.h" /* * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the * host_interest structure. It must match the address of the _host_interest * symbol (see linker script). * * Host Interest is shared between Host and Target in order to coordinate * between the two, and is intended to remain constant (with additions only * at the end) across software releases. * * All addresses are available here so that it's possible to * write a single binary that works with all Target Types. * May be used in assembler code as well as C. */ #define QCA988X_HOST_INTEREST_ADDRESS … #define HOST_INTEREST_MAX_SIZE … /* * These are items that the Host may need to access via BMI or via the * Diagnostic Window. The position of items in this structure must remain * constant across firmware revisions! Types for each item must be fixed * size across target and host platforms. More items may be added at the end. */ struct host_interest { … } __packed; #define HI_ITEM(item) … /* Bits defined in hi_option_flag */ /* Enable timer workaround */ #define HI_OPTION_TIMER_WAR … /* Limit BMI command credits */ #define HI_OPTION_BMI_CRED_LIMIT … /* Relay Dot11 hdr to/from host */ #define HI_OPTION_RELAY_DOT11_HDR … /* MAC addr method 0-locally administred 1-globally unique addrs */ #define HI_OPTION_MAC_ADDR_METHOD … /* Firmware Bridging */ #define HI_OPTION_FW_BRIDGE … /* Enable CPU profiling */ #define HI_OPTION_ENABLE_PROFILE … /* Disable debug logging */ #define HI_OPTION_DISABLE_DBGLOG … /* Skip Era Tracking */ #define HI_OPTION_SKIP_ERA_TRACKING … /* Disable PAPRD (debug) */ #define HI_OPTION_PAPRD_DISABLE … #define HI_OPTION_NUM_DEV_LSB … #define HI_OPTION_NUM_DEV_MSB … #define HI_OPTION_DEV_MODE_LSB … #define HI_OPTION_DEV_MODE_MSB … /* Disable LowFreq Timer Stabilization */ #define HI_OPTION_NO_LFT_STBL … /* Skip regulatory scan */ #define HI_OPTION_SKIP_REG_SCAN … /* * Do regulatory scan during init before * sending WMI ready event to host */ #define HI_OPTION_INIT_REG_SCAN … /* REV6: Do not adjust memory map */ #define HI_OPTION_SKIP_MEMMAP … #define HI_OPTION_MAC_ADDR_METHOD_SHIFT … /* 2 bits of hi_option_flag are used to represent 3 modes */ #define HI_OPTION_FW_MODE_IBSS … #define HI_OPTION_FW_MODE_BSS_STA … #define HI_OPTION_FW_MODE_AP … #define HI_OPTION_FW_MODE_BT30AMP … /* 2 bits of hi_option flag are usedto represent 4 submodes */ #define HI_OPTION_FW_SUBMODE_NONE … #define HI_OPTION_FW_SUBMODE_P2PDEV … #define HI_OPTION_FW_SUBMODE_P2PCLIENT … #define HI_OPTION_FW_SUBMODE_P2PGO … /* Num dev Mask */ #define HI_OPTION_NUM_DEV_MASK … #define HI_OPTION_NUM_DEV_SHIFT … /* firmware bridging */ #define HI_OPTION_FW_BRIDGE_SHIFT … /* * Fw Mode/SubMode Mask *----------------------------------------------------------------------------- * SUB | SUB | SUB | SUB | | | | *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] * (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) *----------------------------------------------------------------------------- */ #define HI_OPTION_FW_MODE_BITS … #define HI_OPTION_FW_MODE_MASK … #define HI_OPTION_FW_MODE_SHIFT … #define HI_OPTION_ALL_FW_MODE_MASK … #define HI_OPTION_FW_SUBMODE_BITS … #define HI_OPTION_FW_SUBMODE_MASK … #define HI_OPTION_FW_SUBMODE_SHIFT … #define HI_OPTION_ALL_FW_SUBMODE_MASK … #define HI_OPTION_ALL_FW_SUBMODE_SHIFT … /* hi_option_flag2 options */ #define HI_OPTION_OFFLOAD_AMSDU … #define HI_OPTION_DFS_SUPPORT … #define HI_OPTION_ENABLE_RFKILL … #define HI_OPTION_RADIO_RETENTION_DISABLE … #define HI_OPTION_EARLY_CFG_DONE … #define HI_OPTION_RF_KILL_SHIFT … #define HI_OPTION_RF_KILL_MASK … /* hi_reset_flag */ /* preserve App Start address */ #define HI_RESET_FLAG_PRESERVE_APP_START … /* preserve host interest */ #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST … /* preserve ROM data */ #define HI_RESET_FLAG_PRESERVE_ROMDATA … #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE … #define HI_RESET_FLAG_PRESERVE_BOOT_INFO … #define HI_RESET_FLAG_WARM_RESET … /* define hi_fw_swap bits */ #define HI_DESC_IN_FW_BIT … /* indicate the reset flag is valid */ #define HI_RESET_FLAG_IS_VALID … /* ACS is enabled */ #define HI_ACS_FLAGS_ENABLED … /* Use physical WWAN device */ #define HI_ACS_FLAGS_USE_WWAN … /* Use test VAP */ #define HI_ACS_FLAGS_TEST_VAP … /* SDIO/mailbox ACS flag definitions */ #define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET … #define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET … #define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE … #define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK … #define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK … /* * If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW * flags are set, then crashdump upload will be done using the BMI host/target * communication channel. */ /* HOST to support using BMI dump FW memory when hit assert */ #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST … /* FW to support using BMI dump FW memory when hit assert */ #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW … /* * CONSOLE FLAGS * * Bit Range Meaning * --------- -------------------------------- * 2..0 UART ID (0 = Default) * 3 Baud Select (0 = 9600, 1 = 115200) * 30..4 Reserved * 31 Enable Console * */ #define HI_CONSOLE_FLAGS_ENABLE … #define HI_CONSOLE_FLAGS_UART_MASK … #define HI_CONSOLE_FLAGS_UART_SHIFT … #define HI_CONSOLE_FLAGS_BAUD_SELECT … /* SM power save options */ #define HI_SMPS_ALLOW_MASK … #define HI_SMPS_MODE_MASK … #define HI_SMPS_MODE_STATIC … #define HI_SMPS_MODE_DYNAMIC … #define HI_SMPS_DISABLE_AUTO_MODE … #define HI_SMPS_DATA_THRESH_MASK … #define HI_SMPS_DATA_THRESH_SHIFT … #define HI_SMPS_RSSI_THRESH_MASK … #define HI_SMPS_RSSI_THRESH_SHIFT … #define HI_SMPS_LOWPWR_CM_MASK … #define HI_SMPS_LOWPWR_CM_SHIFT … #define HI_SMPS_HIPWR_CM_MASK … #define HI_SMPS_HIPWR_CM_SHIFT … /* * WOW Extension configuration * * Bit Range Meaning * --------- -------------------------------- * 8..0 Size of each WOW pattern (max 511) * 15..9 Number of patterns per list (max 127) * 17..16 Number of lists (max 4) * 30..18 Reserved * 31 Enabled * * set values (except enable) to zeros for default settings */ #define HI_WOW_EXT_ENABLED_MASK … #define HI_WOW_EXT_NUM_LIST_SHIFT … #define HI_WOW_EXT_NUM_LIST_MASK … #define HI_WOW_EXT_NUM_PATTERNS_SHIFT … #define HI_WOW_EXT_NUM_PATTERNS_MASK … #define HI_WOW_EXT_PATTERN_SIZE_SHIFT … #define HI_WOW_EXT_PATTERN_SIZE_MASK … #define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) … #define HI_WOW_EXT_GET_NUM_LISTS(config) … #define HI_WOW_EXT_GET_NUM_PATTERNS(config) … #define HI_WOW_EXT_GET_PATTERN_SIZE(config) … /* * Early allocation configuration * Support RAM bank configuration before BMI done and this eases the memory * allocation at very early stage * Bit Range Meaning * --------- ---------------------------------- * [0:3] number of bank assigned to be IRAM * [4:15] reserved * [16:31] magic number * * Note: * 1. target firmware would check magic number and if it's a match, firmware * would consider the bits[0:15] are valid and base on that to calculate * the end of DRAM. Early allocation would be located at that area and * may be reclaimed when necessary * 2. if no magic number is found, early allocation would happen at "_end" * symbol of ROM which is located before the app-data and might NOT be * re-claimable. If this is adopted, link script should keep this in * mind to avoid data corruption. */ #define HI_EARLY_ALLOC_MAGIC … #define HI_EARLY_ALLOC_MAGIC_MASK … #define HI_EARLY_ALLOC_MAGIC_SHIFT … #define HI_EARLY_ALLOC_IRAM_BANKS_MASK … #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT … #define HI_EARLY_ALLOC_VALID() … #define HI_EARLY_ALLOC_GET_IRAM_BANKS() … /*power save flag bit definitions*/ #define HI_PWR_SAVE_LPL_ENABLED … /*b1-b3 reserved*/ /*b4-b5 : dev0 LPL type : 0 - none * 1- Reduce Pwr Search * 2- Reduce Pwr Listen */ /*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ #define HI_PWR_SAVE_LPL_DEV0_LSB … #define HI_PWR_SAVE_LPL_DEV_MASK … /*power save related utility macros*/ #define HI_LPL_ENABLED() … #define HI_DEV_LPL_TYPE_GET(_devix) … #define HOST_INTEREST_SMPS_IS_ALLOWED() … /* Reserve 1024 bytes for extended board data */ #define QCA988X_BOARD_DATA_SZ … #define QCA988X_BOARD_EXT_DATA_SZ … #define QCA9887_BOARD_DATA_SZ … #define QCA9887_BOARD_EXT_DATA_SZ … #define QCA6174_BOARD_DATA_SZ … #define QCA6174_BOARD_EXT_DATA_SZ … #define QCA9377_BOARD_DATA_SZ … #define QCA9377_BOARD_EXT_DATA_SZ … #define QCA99X0_BOARD_DATA_SZ … #define QCA99X0_BOARD_EXT_DATA_SZ … /* Dual band extended board data */ #define QCA99X0_EXT_BOARD_DATA_SZ … #define EXT_BOARD_ADDRESS_OFFSET … #define QCA4019_BOARD_DATA_SZ … #define QCA4019_BOARD_EXT_DATA_SZ … #define WCN3990_BOARD_DATA_SZ … #define WCN3990_BOARD_EXT_DATA_SZ … #endif /* __TARGADDRS_H__ */
Codebase Browser
linux