/* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. * Copyright (c) 2018 The Linux Foundation. All rights reserved. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _HW_H_ #define _HW_H_ #include "targaddrs.h" enum ath10k_bus { … }; #define ATH10K_FW_DIR … #define QCA988X_2_0_DEVICE_ID_UBNT … #define QCA988X_2_0_DEVICE_ID … #define QCA6164_2_1_DEVICE_ID … #define QCA6174_2_1_DEVICE_ID … #define QCA6174_3_2_DEVICE_ID … #define QCA99X0_2_0_DEVICE_ID … #define QCA9888_2_0_DEVICE_ID … #define QCA9984_1_0_DEVICE_ID … #define QCA9377_1_0_DEVICE_ID … #define QCA9887_1_0_DEVICE_ID … /* QCA988X 1.0 definitions (unsupported) */ #define QCA988X_HW_1_0_CHIP_ID_REV … /* QCA988X 2.0 definitions */ #define QCA988X_HW_2_0_VERSION … #define QCA988X_HW_2_0_CHIP_ID_REV … #define QCA988X_HW_2_0_FW_DIR … #define QCA988X_HW_2_0_PATCH_LOAD_ADDR … /* QCA9887 1.0 definitions */ #define QCA9887_HW_1_0_VERSION … #define QCA9887_HW_1_0_CHIP_ID_REV … #define QCA9887_HW_1_0_FW_DIR … #define QCA9887_HW_1_0_PATCH_LOAD_ADDR … /* QCA6174 target BMI version signatures */ #define QCA6174_HW_1_0_VERSION … #define QCA6174_HW_1_1_VERSION … #define QCA6174_HW_1_3_VERSION … #define QCA6174_HW_2_1_VERSION … #define QCA6174_HW_3_0_VERSION … #define QCA6174_HW_3_2_VERSION … /* QCA9377 target BMI version signatures */ #define QCA9377_HW_1_0_DEV_VERSION … #define QCA9377_HW_1_1_DEV_VERSION … enum qca6174_pci_rev { … }; enum qca6174_chip_id_rev { … }; enum qca9377_chip_id_rev { … }; #define QCA6174_HW_2_1_FW_DIR … #define QCA6174_HW_2_1_PATCH_LOAD_ADDR … #define QCA6174_HW_3_0_FW_DIR … #define QCA6174_HW_3_0_PATCH_LOAD_ADDR … /* QCA99X0 1.0 definitions (unsupported) */ #define QCA99X0_HW_1_0_CHIP_ID_REV … /* QCA99X0 2.0 definitions */ #define QCA99X0_HW_2_0_DEV_VERSION … #define QCA99X0_HW_2_0_CHIP_ID_REV … #define QCA99X0_HW_2_0_FW_DIR … #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR … /* QCA9984 1.0 defines */ #define QCA9984_HW_1_0_DEV_VERSION … #define QCA9984_HW_DEV_TYPE … #define QCA9984_HW_1_0_CHIP_ID_REV … #define QCA9984_HW_1_0_FW_DIR … #define QCA9984_HW_1_0_PATCH_LOAD_ADDR … /* QCA9888 2.0 defines */ #define QCA9888_HW_2_0_DEV_VERSION … #define QCA9888_HW_DEV_TYPE … #define QCA9888_HW_2_0_CHIP_ID_REV … #define QCA9888_HW_2_0_FW_DIR … #define QCA9888_HW_2_0_PATCH_LOAD_ADDR … /* QCA9377 1.0 definitions */ #define QCA9377_HW_1_0_FW_DIR … #define QCA9377_HW_1_0_PATCH_LOAD_ADDR … /* QCA4019 1.0 definitions */ #define QCA4019_HW_1_0_DEV_VERSION … #define QCA4019_HW_1_0_FW_DIR … #define QCA4019_HW_1_0_PATCH_LOAD_ADDR … /* WCN3990 1.0 definitions */ #define WCN3990_HW_1_0_DEV_VERSION … #define WCN3990_HW_1_0_FW_DIR … #define ATH10K_FW_FILE_BASE … #define ATH10K_FW_API_MAX … #define ATH10K_FW_API_MIN … #define ATH10K_FW_API2_FILE … #define ATH10K_FW_API3_FILE … /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ #define ATH10K_FW_API4_FILE … /* HTT id conflict fix for management frames over HTT */ #define ATH10K_FW_API5_FILE … /* the firmware-6.bin blob */ #define ATH10K_FW_API6_FILE … #define ATH10K_FW_UTF_FILE … #define ATH10K_FW_UTF_API2_FILE … #define ATH10K_FW_UTF_FILE_BASE … /* includes also the null byte */ #define ATH10K_FIRMWARE_MAGIC … #define ATH10K_BOARD_MAGIC … #define ATH10K_BOARD_DATA_FILE … #define ATH10K_BOARD_API2_FILE … #define ATH10K_EBOARD_DATA_FILE … #define REG_DUMP_COUNT_QCA988X … struct ath10k_fw_ie { … }; enum ath10k_fw_ie_type { … }; enum ath10k_fw_wmi_op_version { … }; enum ath10k_fw_htt_op_version { … }; enum ath10k_bd_ie_type { … }; enum ath10k_bd_ie_board_type { … }; enum ath10k_hw_rev { … }; struct ath10k_hw_regs { … }; extern const struct ath10k_hw_regs qca988x_regs; extern const struct ath10k_hw_regs qca6174_regs; extern const struct ath10k_hw_regs qca99x0_regs; extern const struct ath10k_hw_regs qca4019_regs; extern const struct ath10k_hw_regs wcn3990_regs; struct ath10k_hw_ce_regs_addr_map { … }; struct ath10k_hw_ce_ctrl1 { … }; struct ath10k_hw_ce_cmd_halt { … }; struct ath10k_hw_ce_host_ie { … }; struct ath10k_hw_ce_host_wm_regs { … }; struct ath10k_hw_ce_misc_regs { … }; struct ath10k_hw_ce_dst_src_wm_regs { … }; struct ath10k_hw_ce_ctrl1_upd { … }; struct ath10k_hw_ce_regs { … }; struct ath10k_hw_values { … }; extern const struct ath10k_hw_values qca988x_values; extern const struct ath10k_hw_values qca6174_values; extern const struct ath10k_hw_values qca99x0_values; extern const struct ath10k_hw_values qca9888_values; extern const struct ath10k_hw_values qca4019_values; extern const struct ath10k_hw_values wcn3990_values; extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; extern const struct ath10k_hw_ce_regs qcax_ce_regs; void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); int ath10k_hw_diag_fast_download(struct ath10k *ar, u32 address, const void *buffer, u32 length); #define QCA_REV_988X(ar) … #define QCA_REV_9887(ar) … #define QCA_REV_6174(ar) … #define QCA_REV_99X0(ar) … #define QCA_REV_9888(ar) … #define QCA_REV_9984(ar) … #define QCA_REV_9377(ar) … #define QCA_REV_40XX(ar) … #define QCA_REV_WCN3990(ar) … /* Known peculiarities: * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap * - raw have FCS, nwifi doesn't * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher * param, llc/snap) are aligned to 4byte boundaries each */ enum ath10k_hw_txrx_mode { … }; enum ath10k_mcast2ucast_mode { … }; enum ath10k_hw_rate_ofdm { … }; enum ath10k_hw_rate_cck { … }; enum ath10k_hw_rate_rev2_cck { … }; enum ath10k_hw_cc_wraparound_type { … }; enum ath10k_hw_refclk_speed { … }; struct ath10k_hw_clk_params { … }; struct htt_rx_desc_ops; struct ath10k_hw_params { … }; struct htt_resp; struct htt_data_tx_completion_ext; struct htt_rx_ring_rx_desc_offsets; /* Defines needed for Rx descriptor abstraction */ struct ath10k_hw_ops { … }; extern const struct ath10k_hw_ops qca988x_ops; extern const struct ath10k_hw_ops qca99x0_ops; extern const struct ath10k_hw_ops qca6174_ops; extern const struct ath10k_hw_ops qca6174_sdio_ops; extern const struct ath10k_hw_ops wcn3990_ops; extern const struct ath10k_hw_clk_params qca6174_clk[]; static inline int ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw, struct htt_resp *htt) { … } static inline int ath10k_is_rssi_enable(struct ath10k_hw_params *hw, struct htt_resp *resp) { … } /* Target specific defines for MAIN firmware */ #define TARGET_NUM_VDEVS … #define TARGET_NUM_PEER_AST … #define TARGET_NUM_WDS_ENTRIES … #define TARGET_DMA_BURST_SIZE … #define TARGET_MAC_AGGR_DELIM … #define TARGET_AST_SKID_LIMIT … #define TARGET_NUM_STATIONS … #define TARGET_NUM_PEERS … #define TARGET_NUM_OFFLOAD_PEERS … #define TARGET_NUM_OFFLOAD_REORDER_BUFS … #define TARGET_NUM_PEER_KEYS … #define TARGET_NUM_TIDS … #define TARGET_TX_CHAIN_MASK … #define TARGET_RX_CHAIN_MASK … #define TARGET_RX_TIMEOUT_LO_PRI … #define TARGET_RX_TIMEOUT_HI_PRI … #define TARGET_SCAN_MAX_PENDING_REQS … #define TARGET_BMISS_OFFLOAD_MAX_VDEV … #define TARGET_ROAM_OFFLOAD_MAX_VDEV … #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES … #define TARGET_GTK_OFFLOAD_MAX_VDEV … #define TARGET_NUM_MCAST_GROUPS … #define TARGET_NUM_MCAST_TABLE_ELEMS … #define TARGET_MCAST2UCAST_MODE … #define TARGET_TX_DBG_LOG_SIZE … #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK … #define TARGET_VOW_CONFIG … #define TARGET_NUM_MSDU_DESC … #define TARGET_MAX_FRAG_ENTRIES … /* Target specific defines for 10.X firmware */ #define TARGET_10X_NUM_VDEVS … #define TARGET_10X_NUM_PEER_AST … #define TARGET_10X_NUM_WDS_ENTRIES … #define TARGET_10X_DMA_BURST_SIZE … #define TARGET_10X_MAC_AGGR_DELIM … #define TARGET_10X_AST_SKID_LIMIT … #define TARGET_10X_NUM_STATIONS … #define TARGET_10X_TX_STATS_NUM_STATIONS … #define TARGET_10X_NUM_PEERS … #define TARGET_10X_TX_STATS_NUM_PEERS … #define TARGET_10X_NUM_OFFLOAD_PEERS … #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS … #define TARGET_10X_NUM_PEER_KEYS … #define TARGET_10X_NUM_TIDS_MAX … #define TARGET_10X_NUM_TIDS … #define TARGET_10X_TX_STATS_NUM_TIDS … #define TARGET_10X_TX_CHAIN_MASK … #define TARGET_10X_RX_CHAIN_MASK … #define TARGET_10X_RX_TIMEOUT_LO_PRI … #define TARGET_10X_RX_TIMEOUT_HI_PRI … #define TARGET_10X_SCAN_MAX_PENDING_REQS … #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV … #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV … #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES … #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV … #define TARGET_10X_NUM_MCAST_GROUPS … #define TARGET_10X_NUM_MCAST_TABLE_ELEMS … #define TARGET_10X_MCAST2UCAST_MODE … #define TARGET_10X_TX_DBG_LOG_SIZE … #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK … #define TARGET_10X_VOW_CONFIG … #define TARGET_10X_NUM_MSDU_DESC … #define TARGET_10X_MAX_FRAG_ENTRIES … /* 10.2 parameters */ #define TARGET_10_2_DMA_BURST_SIZE … /* Target specific defines for WMI-TLV firmware */ #define TARGET_TLV_NUM_VDEVS … #define TARGET_TLV_NUM_STATIONS … #define TARGET_TLV_NUM_PEERS … #define TARGET_TLV_NUM_TDLS_VDEVS … #define TARGET_TLV_NUM_TIDS … #define TARGET_TLV_NUM_MSDU_DESC … #define TARGET_TLV_NUM_MSDU_DESC_HL … #define TARGET_TLV_NUM_WOW_PATTERNS … #define TARGET_TLV_MGMT_NUM_MSDU_DESC … /* Target specific defines for WMI-HL-1.0 firmware */ #define TARGET_HL_TLV_NUM_PEERS … #define TARGET_HL_TLV_AST_SKID_LIMIT … #define TARGET_HL_TLV_NUM_WDS_ENTRIES … /* Target specific defines for QCA9377 high latency firmware */ #define TARGET_QCA9377_HL_NUM_PEERS … /* Diagnostic Window */ #define CE_DIAG_PIPE … #define NUM_TARGET_CE_CONFIG_WLAN … /* Target specific defines for 10.4 firmware */ #define TARGET_10_4_NUM_VDEVS … #define TARGET_10_4_NUM_STATIONS … #define TARGET_10_4_NUM_PEERS … #define TARGET_10_4_ACTIVE_PEERS … #define TARGET_10_4_NUM_QCACHE_PEERS_MAX … #define TARGET_10_4_QCACHE_ACTIVE_PEERS … #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC … #define TARGET_10_4_NUM_OFFLOAD_PEERS … #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS … #define TARGET_10_4_NUM_PEER_KEYS … #define TARGET_10_4_TGT_NUM_TIDS … #define TARGET_10_4_NUM_MSDU_DESC … #define TARGET_10_4_NUM_MSDU_DESC_PFC … #define TARGET_10_4_AST_SKID_LIMIT … /* 100 ms for video, best-effort, and background */ #define TARGET_10_4_RX_TIMEOUT_LO_PRI … /* 40 ms for voice */ #define TARGET_10_4_RX_TIMEOUT_HI_PRI … #define TARGET_10_4_RX_DECAP_MODE … #define TARGET_10_4_SCAN_MAX_REQS … #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV … #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV … #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES … /* Note: mcast to ucast is disabled by default */ #define TARGET_10_4_NUM_MCAST_GROUPS … #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS … #define TARGET_10_4_MCAST2UCAST_MODE … #define TARGET_10_4_TX_DBG_LOG_SIZE … #define TARGET_10_4_NUM_WDS_ENTRIES … #define TARGET_10_4_DMA_BURST_SIZE … #define TARGET_10_4_MAC_AGGR_DELIM … #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK … #define TARGET_10_4_VOW_CONFIG … #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV … #define TARGET_10_4_11AC_TX_MAX_FRAGS … #define TARGET_10_4_MAX_PEER_EXT_STATS … #define TARGET_10_4_SMART_ANT_CAP … #define TARGET_10_4_BK_MIN_FREE … #define TARGET_10_4_BE_MIN_FREE … #define TARGET_10_4_VI_MIN_FREE … #define TARGET_10_4_VO_MIN_FREE … #define TARGET_10_4_RX_BATCH_MODE … #define TARGET_10_4_THERMAL_THROTTLING_CONFIG … #define TARGET_10_4_ATF_CONFIG … #define TARGET_10_4_IPHDR_PAD_CONFIG … #define TARGET_10_4_QWRAP_CONFIG … /* TDLS config */ #define TARGET_10_4_NUM_TDLS_VDEVS … #define TARGET_10_4_NUM_TDLS_BUFFER_STA … #define TARGET_10_4_NUM_TDLS_SLEEP_STA … /* Maximum number of Copy Engine's supported */ #define CE_COUNT_MAX … /* Number of Copy Engines supported */ #define CE_COUNT … /* * Granted MSIs are assigned as follows: * Firmware uses the first * Remaining MSIs, if any, are used by Copy Engines * This mapping is known to both Target firmware and Host software. * It may be changed as long as Host and Target are kept in sync. */ /* MSI for firmware (errors, etc.) */ #define MSI_ASSIGN_FW … /* MSIs for Copy Engines */ #define MSI_ASSIGN_CE_INITIAL … #define MSI_ASSIGN_CE_MAX … /* as of IP3.7.1 */ #define RTC_STATE_V_ON … #define RTC_STATE_V_LSB … #define RTC_STATE_V_MASK … #define RTC_STATE_ADDRESS … #define PCIE_SOC_WAKE_V_MASK … #define PCIE_SOC_WAKE_ADDRESS … #define PCIE_SOC_WAKE_RESET … #define SOC_GLOBAL_RESET_ADDRESS … #define RTC_SOC_BASE_ADDRESS … #define RTC_WMAC_BASE_ADDRESS … #define MAC_COEX_BASE_ADDRESS … #define BT_COEX_BASE_ADDRESS … #define SOC_PCIE_BASE_ADDRESS … #define SOC_CORE_BASE_ADDRESS … #define WLAN_UART_BASE_ADDRESS … #define WLAN_SI_BASE_ADDRESS … #define WLAN_GPIO_BASE_ADDRESS … #define WLAN_ANALOG_INTF_BASE_ADDRESS … #define WLAN_MAC_BASE_ADDRESS … #define EFUSE_BASE_ADDRESS … #define FPGA_REG_BASE_ADDRESS … #define WLAN_UART2_BASE_ADDRESS … #define CE_WRAPPER_BASE_ADDRESS … #define CE0_BASE_ADDRESS … #define CE1_BASE_ADDRESS … #define CE2_BASE_ADDRESS … #define CE3_BASE_ADDRESS … #define CE4_BASE_ADDRESS … #define CE5_BASE_ADDRESS … #define CE6_BASE_ADDRESS … #define CE7_BASE_ADDRESS … #define DBI_BASE_ADDRESS … #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS … #define PCIE_LOCAL_BASE_ADDRESS … #define SOC_RESET_CONTROL_ADDRESS … #define SOC_RESET_CONTROL_OFFSET … #define SOC_RESET_CONTROL_SI0_RST_MASK … #define SOC_RESET_CONTROL_CE_RST_MASK … #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK … #define SOC_CPU_CLOCK_OFFSET … #define SOC_CPU_CLOCK_STANDARD_LSB … #define SOC_CPU_CLOCK_STANDARD_MASK … #define SOC_CLOCK_CONTROL_OFFSET … #define SOC_CLOCK_CONTROL_SI0_CLK_MASK … #define SOC_SYSTEM_SLEEP_OFFSET … #define SOC_LPO_CAL_OFFSET … #define SOC_LPO_CAL_ENABLE_LSB … #define SOC_LPO_CAL_ENABLE_MASK … #define SOC_LF_TIMER_CONTROL0_ADDRESS … #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK … #define SOC_CHIP_ID_ADDRESS … #define SOC_CHIP_ID_REV_LSB … #define SOC_CHIP_ID_REV_MASK … #define WLAN_RESET_CONTROL_COLD_RST_MASK … #define WLAN_RESET_CONTROL_WARM_RST_MASK … #define WLAN_SYSTEM_SLEEP_DISABLE_LSB … #define WLAN_SYSTEM_SLEEP_DISABLE_MASK … #define WLAN_GPIO_PIN0_ADDRESS … #define WLAN_GPIO_PIN0_CONFIG_LSB … #define WLAN_GPIO_PIN0_CONFIG_MASK … #define WLAN_GPIO_PIN0_PAD_PULL_LSB … #define WLAN_GPIO_PIN0_PAD_PULL_MASK … #define WLAN_GPIO_PIN1_ADDRESS … #define WLAN_GPIO_PIN1_CONFIG_MASK … #define WLAN_GPIO_PIN10_ADDRESS … #define WLAN_GPIO_PIN11_ADDRESS … #define WLAN_GPIO_PIN12_ADDRESS … #define WLAN_GPIO_PIN13_ADDRESS … #define CLOCK_GPIO_OFFSET … #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB … #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK … #define SI_CONFIG_OFFSET … #define SI_CONFIG_ERR_INT_LSB … #define SI_CONFIG_ERR_INT_MASK … #define SI_CONFIG_BIDIR_OD_DATA_LSB … #define SI_CONFIG_BIDIR_OD_DATA_MASK … #define SI_CONFIG_I2C_LSB … #define SI_CONFIG_I2C_MASK … #define SI_CONFIG_POS_SAMPLE_LSB … #define SI_CONFIG_POS_SAMPLE_MASK … #define SI_CONFIG_INACTIVE_DATA_LSB … #define SI_CONFIG_INACTIVE_DATA_MASK … #define SI_CONFIG_INACTIVE_CLK_LSB … #define SI_CONFIG_INACTIVE_CLK_MASK … #define SI_CONFIG_DIVIDER_LSB … #define SI_CONFIG_DIVIDER_MASK … #define SI_CS_OFFSET … #define SI_CS_DONE_ERR_LSB … #define SI_CS_DONE_ERR_MASK … #define SI_CS_DONE_INT_LSB … #define SI_CS_DONE_INT_MASK … #define SI_CS_START_LSB … #define SI_CS_START_MASK … #define SI_CS_RX_CNT_LSB … #define SI_CS_RX_CNT_MASK … #define SI_CS_TX_CNT_LSB … #define SI_CS_TX_CNT_MASK … #define SI_TX_DATA0_OFFSET … #define SI_TX_DATA1_OFFSET … #define SI_RX_DATA0_OFFSET … #define SI_RX_DATA1_OFFSET … #define CORE_CTRL_CPU_INTR_MASK … #define CORE_CTRL_PCIE_REG_31_MASK … #define CORE_CTRL_ADDRESS … #define PCIE_INTR_ENABLE_ADDRESS … #define PCIE_INTR_CAUSE_ADDRESS … #define PCIE_INTR_CLR_ADDRESS … #define SCRATCH_3_ADDRESS … #define CPU_INTR_ADDRESS … #define FW_RAM_CONFIG_ADDRESS … #define CCNT_TO_MSEC(ar, x) … /* Firmware indications to the Host via SCRATCH_3 register. */ #define FW_INDICATOR_ADDRESS … #define FW_IND_EVENT_PENDING … #define FW_IND_INITIALIZED … #define FW_IND_HOST_READY … /* HOST_REG interrupt from firmware */ #define PCIE_INTR_FIRMWARE_MASK … #define PCIE_INTR_CE_MASK_ALL … #define DRAM_BASE_ADDRESS … #define PCIE_BAR_REG_ADDRESS … #define MISSING … #define SYSTEM_SLEEP_OFFSET … #define WLAN_SYSTEM_SLEEP_OFFSET … #define WLAN_RESET_CONTROL_OFFSET … #define CLOCK_CONTROL_OFFSET … #define CLOCK_CONTROL_SI0_CLK_MASK … #define RESET_CONTROL_MBOX_RST_MASK … #define RESET_CONTROL_SI0_RST_MASK … #define GPIO_BASE_ADDRESS … #define GPIO_PIN0_OFFSET … #define GPIO_PIN1_OFFSET … #define GPIO_PIN0_CONFIG_LSB … #define GPIO_PIN0_CONFIG_MASK … #define GPIO_PIN0_PAD_PULL_LSB … #define GPIO_PIN0_PAD_PULL_MASK … #define GPIO_PIN1_CONFIG_MASK … #define SI_BASE_ADDRESS … #define SCRATCH_BASE_ADDRESS … #define LOCAL_SCRATCH_OFFSET … #define CPU_CLOCK_OFFSET … #define LPO_CAL_OFFSET … #define GPIO_PIN10_OFFSET … #define GPIO_PIN11_OFFSET … #define GPIO_PIN12_OFFSET … #define GPIO_PIN13_OFFSET … #define CPU_CLOCK_STANDARD_LSB … #define CPU_CLOCK_STANDARD_MASK … #define LPO_CAL_ENABLE_LSB … #define LPO_CAL_ENABLE_MASK … #define ANALOG_INTF_BASE_ADDRESS … #define MBOX_BASE_ADDRESS … #define INT_STATUS_ENABLE_ERROR_LSB … #define INT_STATUS_ENABLE_ERROR_MASK … #define INT_STATUS_ENABLE_CPU_LSB … #define INT_STATUS_ENABLE_CPU_MASK … #define INT_STATUS_ENABLE_COUNTER_LSB … #define INT_STATUS_ENABLE_COUNTER_MASK … #define INT_STATUS_ENABLE_MBOX_DATA_LSB … #define INT_STATUS_ENABLE_MBOX_DATA_MASK … #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB … #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK … #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB … #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK … #define COUNTER_INT_STATUS_ENABLE_BIT_LSB … #define COUNTER_INT_STATUS_ENABLE_BIT_MASK … #define INT_STATUS_ENABLE_ADDRESS … #define CPU_INT_STATUS_ENABLE_BIT_LSB … #define CPU_INT_STATUS_ENABLE_BIT_MASK … #define HOST_INT_STATUS_ADDRESS … #define CPU_INT_STATUS_ADDRESS … #define ERROR_INT_STATUS_ADDRESS … #define ERROR_INT_STATUS_WAKEUP_MASK … #define ERROR_INT_STATUS_WAKEUP_LSB … #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK … #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB … #define ERROR_INT_STATUS_TX_OVERFLOW_MASK … #define ERROR_INT_STATUS_TX_OVERFLOW_LSB … #define COUNT_DEC_ADDRESS … #define HOST_INT_STATUS_CPU_MASK … #define HOST_INT_STATUS_CPU_LSB … #define HOST_INT_STATUS_ERROR_MASK … #define HOST_INT_STATUS_ERROR_LSB … #define HOST_INT_STATUS_COUNTER_MASK … #define HOST_INT_STATUS_COUNTER_LSB … #define RX_LOOKAHEAD_VALID_ADDRESS … #define WINDOW_DATA_ADDRESS … #define WINDOW_READ_ADDR_ADDRESS … #define WINDOW_WRITE_ADDR_ADDRESS … #define QCA9887_1_0_I2C_SDA_GPIO_PIN … #define QCA9887_1_0_I2C_SDA_PIN_CONFIG … #define QCA9887_1_0_SI_CLK_GPIO_PIN … #define QCA9887_1_0_SI_CLK_PIN_CONFIG … #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS … #define QCA9887_EEPROM_SELECT_READ … #define QCA9887_EEPROM_ADDR_HI_MASK … #define QCA9887_EEPROM_ADDR_HI_LSB … #define QCA9887_EEPROM_ADDR_LO_MASK … #define QCA9887_EEPROM_ADDR_LO_LSB … #define MBOX_RESET_CONTROL_ADDRESS … #define MBOX_HOST_INT_STATUS_ADDRESS … #define MBOX_HOST_INT_STATUS_ERROR_LSB … #define MBOX_HOST_INT_STATUS_ERROR_MASK … #define MBOX_HOST_INT_STATUS_CPU_LSB … #define MBOX_HOST_INT_STATUS_CPU_MASK … #define MBOX_HOST_INT_STATUS_COUNTER_LSB … #define MBOX_HOST_INT_STATUS_COUNTER_MASK … #define MBOX_CPU_INT_STATUS_ADDRESS … #define MBOX_ERROR_INT_STATUS_ADDRESS … #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB … #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK … #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB … #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK … #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB … #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK … #define MBOX_COUNTER_INT_STATUS_ADDRESS … #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB … #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK … #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS … #define MBOX_INT_STATUS_ENABLE_ADDRESS … #define MBOX_INT_STATUS_ENABLE_ERROR_LSB … #define MBOX_INT_STATUS_ENABLE_ERROR_MASK … #define MBOX_INT_STATUS_ENABLE_CPU_LSB … #define MBOX_INT_STATUS_ENABLE_CPU_MASK … #define MBOX_INT_STATUS_ENABLE_INT_LSB … #define MBOX_INT_STATUS_ENABLE_INT_MASK … #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB … #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK … #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB … #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK … #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS … #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB … #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK … #define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK … #define MBOX_ERROR_STATUS_ENABLE_ADDRESS … #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB … #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK … #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB … #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK … #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS … #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB … #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK … #define MBOX_COUNT_ADDRESS … #define MBOX_COUNT_DEC_ADDRESS … #define MBOX_WINDOW_DATA_ADDRESS … #define MBOX_WINDOW_WRITE_ADDR_ADDRESS … #define MBOX_WINDOW_READ_ADDR_ADDRESS … #define MBOX_CPU_DBG_SEL_ADDRESS … #define MBOX_CPU_DBG_ADDRESS … #define MBOX_RTC_BASE_ADDRESS … #define MBOX_GPIO_BASE_ADDRESS … #define MBOX_MBOX_BASE_ADDRESS … #define RTC_STATE_V_GET(x) … /* Register definitions for first generation ath10k cards. These cards include * a mac thich has a register allocation similar to ath9k and at least some * registers including the ones relevant for modifying the coverage class are * identical to the ath9k definitions. * These registers are usually managed by the ath10k firmware. However by * overriding them it is possible to support coverage class modifications. */ #define WAVE1_PCU_ACK_CTS_TIMEOUT … #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX … #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK … #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB … #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK … #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB … #define WAVE1_PCU_GBL_IFS_SLOT … #define WAVE1_PCU_GBL_IFS_SLOT_MASK … #define WAVE1_PCU_GBL_IFS_SLOT_MAX … #define WAVE1_PCU_GBL_IFS_SLOT_LSB … #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 … #define WAVE1_PHYCLK … #define WAVE1_PHYCLK_USEC_MASK … #define WAVE1_PHYCLK_USEC_LSB … /* qca6174 PLL offset/mask */ #define SOC_CORE_CLK_CTRL_OFFSET … #define SOC_CORE_CLK_CTRL_DIV_LSB … #define SOC_CORE_CLK_CTRL_DIV_MASK … #define EFUSE_OFFSET … #define EFUSE_XTAL_SEL_LSB … #define EFUSE_XTAL_SEL_MASK … #define BB_PLL_CONFIG_OFFSET … #define BB_PLL_CONFIG_FRAC_LSB … #define BB_PLL_CONFIG_FRAC_MASK … #define BB_PLL_CONFIG_OUTDIV_LSB … #define BB_PLL_CONFIG_OUTDIV_MASK … #define WLAN_PLL_SETTLE_OFFSET … #define WLAN_PLL_SETTLE_TIME_LSB … #define WLAN_PLL_SETTLE_TIME_MASK … #define WLAN_PLL_CONTROL_OFFSET … #define WLAN_PLL_CONTROL_DIV_LSB … #define WLAN_PLL_CONTROL_DIV_MASK … #define WLAN_PLL_CONTROL_REFDIV_LSB … #define WLAN_PLL_CONTROL_REFDIV_MASK … #define WLAN_PLL_CONTROL_BYPASS_LSB … #define WLAN_PLL_CONTROL_BYPASS_MASK … #define WLAN_PLL_CONTROL_NOPWD_LSB … #define WLAN_PLL_CONTROL_NOPWD_MASK … #define RTC_SYNC_STATUS_OFFSET … #define RTC_SYNC_STATUS_PLL_CHANGING_LSB … #define RTC_SYNC_STATUS_PLL_CHANGING_MASK … /* qca6174 PLL offset/mask end */ /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory * region is accessed. The memory region size is 1M. * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0] * is 0xX. * The following MACROs are defined to get the 0xX and the size limit. */ #define CPU_ADDR_MSB_REGION_MASK … #define CPU_ADDR_MSB_REGION_VAL(X) … #define REGION_ACCESS_SIZE_LIMIT … #define REGION_ACCESS_SIZE_MASK … #endif /* _HW_H_ */
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