/* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. * Copyright (c) 2018, The Linux Foundation. All rights reserved. * Copyright (c) 2021, 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _HTT_H_ #define _HTT_H_ #include <linux/bug.h> #include <linux/interrupt.h> #include <linux/dmapool.h> #include <linux/hashtable.h> #include <linux/kfifo.h> #include <net/mac80211.h> #include "htc.h" #include "hw.h" #include "rx_desc.h" enum htt_dbg_stats_type { … }; enum htt_h2t_msg_type { … }; struct htt_cmd_hdr { … } __packed; struct htt_ver_req { … } __packed; /* * HTT tx MSDU descriptor * * The HTT tx MSDU descriptor is created by the host HTT SW for each * tx MSDU. The HTT tx MSDU descriptor contains the information that * the target firmware needs for the FW's tx processing, particularly * for creating the HW msdu descriptor. * The same HTT tx descriptor is used for HL and LL systems, though * a few fields within the tx descriptor are used only by LL or * only by HL. * The HTT tx descriptor is defined in two manners: by a struct with * bitfields, and by a series of [dword offset, bit mask, bit shift] * definitions. * The target should use the struct def, for simplicity and clarity, * but the host shall use the bit-mast + bit-shift defs, to be endian- * neutral. Specifically, the host shall use the get/set macros built * around the mask + shift defs. */ struct htt_data_tx_desc_frag { … } __packed; struct htt_msdu_ext_desc { … }; struct htt_msdu_ext_desc_64 { … }; #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE … #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE … #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE … #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE … #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE … #define HTT_MSDU_CHECKSUM_ENABLE … #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 … #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 … #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 … #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 … #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 … #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 … #define HTT_MSDU_CHECKSUM_ENABLE_64 … enum htt_data_tx_desc_flags0 { … }; enum htt_data_tx_desc_flags1 { … }; #define HTT_TX_CREDIT_DELTA_ABS_M … #define HTT_TX_CREDIT_DELTA_ABS_S … #define HTT_TX_CREDIT_DELTA_ABS_GET(word) … #define HTT_TX_CREDIT_SIGN_BIT_M … #define HTT_TX_CREDIT_SIGN_BIT_S … #define HTT_TX_CREDIT_SIGN_BIT_GET(word) … enum htt_data_tx_ext_tid { … }; #define HTT_INVALID_PEERID … /* * htt_data_tx_desc - used for data tx path * * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ * for special kinds of tids * postponed: only for HL hosts. indicates if this is a resend * (HL hosts manage queues on the host ) * more_in_batch: only for HL hosts. indicates if more packets are * pending. this allows target to wait and aggregate * freq: 0 means home channel of given vdev. intended for offchannel */ struct htt_data_tx_desc { … } __packed; struct htt_data_tx_desc_64 { … } __packed; enum htt_rx_ring_flags { … }; #define HTT_RX_RING_SIZE_MIN … #define HTT_RX_RING_SIZE_MAX … #define HTT_RX_RING_SIZE … #define HTT_RX_RING_FILL_LEVEL … #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC … struct htt_rx_ring_rx_desc_offsets { … } __packed; struct htt_rx_ring_setup_ring32 { … } __packed; struct htt_rx_ring_setup_ring64 { … } __packed; struct htt_rx_ring_setup_hdr { … } __packed; struct htt_rx_ring_setup_32 { … } __packed; struct htt_rx_ring_setup_64 { … } __packed; /* * htt_stats_req - request target to send specified statistics * * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually * so make sure its little-endian. * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually * so make sure its little-endian. * @cfg_val: stat_type specific configuration * @stat_type: see %htt_dbg_stats_type * @cookie_lsb: used for confirmation message from target->host * @cookie_msb: ditto as %cookie */ struct htt_stats_req { … } __packed; #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID … #define HTT_STATS_BIT_MASK … /* * htt_oob_sync_req - request out-of-band sync * * The HTT SYNC tells the target to suspend processing of subsequent * HTT host-to-target messages until some other target agent locally * informs the target HTT FW that the current sync counter is equal to * or greater than (in a modulo sense) the sync counter specified in * the SYNC message. * * This allows other host-target components to synchronize their operation * with HTT, e.g. to ensure that tx frames don't get transmitted until a * security key has been downloaded to and activated by the target. * In the absence of any explicit synchronization counter value * specification, the target HTT FW will use zero as the default current * sync value. * * The HTT target FW will suspend its host->target message processing as long * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. */ struct htt_oob_sync_req { … } __packed; struct htt_aggr_conf { … } __packed; struct htt_aggr_conf_v2 { … } __packed; #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN … struct htt_mgmt_tx_desc_qca99x0 { … } __packed; struct htt_mgmt_tx_desc { … } __packed; enum htt_mgmt_tx_status { … }; /*=== target -> host messages ===============================================*/ enum htt_main_t2h_msg_type { … }; enum htt_10x_t2h_msg_type { … }; enum htt_tlv_t2h_msg_type { … }; enum htt_10_4_t2h_msg_type { … }; enum htt_t2h_msg_type { … }; /* * htt_resp_hdr - header for target-to-host messages * * msg_type: see htt_t2h_msg_type */ struct htt_resp_hdr { … } __packed; #define HTT_RESP_HDR_MSG_TYPE_OFFSET … #define HTT_RESP_HDR_MSG_TYPE_MASK … #define HTT_RESP_HDR_MSG_TYPE_LSB … /* htt_ver_resp - response sent for htt_ver_req */ struct htt_ver_resp { … } __packed; #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI … #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK … struct htt_mgmt_tx_completion { … } __packed; #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK … #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB … #define HTT_RX_INDICATION_INFO0_FLUSH_VALID … #define HTT_RX_INDICATION_INFO0_RELEASE_VALID … #define HTT_RX_INDICATION_INFO0_PPDU_DURATION … #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK … #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB … #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK … #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB … #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK … #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB … #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK … #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB … #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK … #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB … #define HTT_TX_CMPL_FLAG_DATA_RSSI … #define HTT_TX_CMPL_FLAG_PPID_PRESENT … #define HTT_TX_CMPL_FLAG_PA_PRESENT … #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT … #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 … #define HTT_TX_DATA_APPEND_RETRIES … #define HTT_TX_DATA_APPEND_TIMESTAMP … struct htt_rx_indication_hdr { … } __packed; #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID … #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK … #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB … #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK … #define HTT_RX_INDICATION_INFO0_END_VALID … #define HTT_RX_INDICATION_INFO0_START_VALID … #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK … #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB … #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK … #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB … #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK … #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB … #define HTT_RX_INDICATION_INFO2_SERVICE_MASK … #define HTT_RX_INDICATION_INFO2_SERVICE_LSB … enum htt_rx_legacy_rate { … }; enum htt_rx_legacy_rate_type { … }; enum htt_rx_preamble_type { … }; /* * Fields: phy_err_valid, phy_err_code, tsf, * usec_timestamp, sub_usec_timestamp * ..are valid only if end_valid == 1. * * Fields: rssi_chains, legacy_rate_type, * legacy_rate_cck, preamble_type, service, * vht_sig_* * ..are valid only if start_valid == 1; */ struct htt_rx_indication_ppdu { … } __packed; enum htt_rx_mpdu_status { … }; struct htt_rx_indication_mpdu_range { … } __packed; struct htt_rx_indication_prefix { … } __packed; struct htt_rx_indication { … } __packed; /* High latency version of the RX indication */ struct htt_rx_indication_hl { … } __packed; struct htt_hl_rx_desc { … } __packed; static inline struct htt_rx_indication_mpdu_range * htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) { … } static inline struct htt_rx_indication_mpdu_range * htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind) { … } enum htt_rx_flush_mpdu_status { … }; /* * htt_rx_flush - discard or reorder given range of mpdus * * Note: host must check if all sequence numbers between * [seq_num_start, seq_num_end-1] are valid. */ struct htt_rx_flush { … }; struct htt_rx_peer_map { … } __packed; struct htt_rx_peer_unmap { … } __packed; enum htt_txrx_sec_cast_type { … }; enum htt_rx_pn_check_type { … }; enum htt_rx_tkip_demic_type { … }; enum htt_security_types { … }; #define ATH10K_HTT_TXRX_PEER_SECURITY_MAX … #define ATH10K_TXRX_NUM_EXT_TIDS … #define ATH10K_TXRX_NON_QOS_TID … enum htt_security_flags { … }; struct htt_security_indication { … } __packed; #define HTT_RX_BA_INFO0_TID_MASK … #define HTT_RX_BA_INFO0_TID_LSB … #define HTT_RX_BA_INFO0_PEER_ID_MASK … #define HTT_RX_BA_INFO0_PEER_ID_LSB … struct htt_rx_addba { … } __packed; struct htt_rx_delba { … } __packed; enum htt_data_tx_status { … }; enum htt_data_tx_flags { … }; #define HTT_TX_COMPL_INV_MSDU_ID … struct htt_append_retries { … } __packed; struct htt_data_tx_completion_ext { … } __packed; /* * @brief target -> host TX completion indication message definition * * @details * The following diagram shows the format of the TX completion indication sent * from the target to the host * * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| * |-------------------------------------------------------------| * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type | * |-------------------------------------------------------------| * payload: | MSDU1 ID | MSDU0 ID | * |-------------------------------------------------------------| * : MSDU3 ID : MSDU2 ID : * |-------------------------------------------------------------| * | struct htt_tx_compl_ind_append_retries | * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| * | struct htt_tx_compl_ind_append_tx_tstamp | * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | * |-------------------------------------------------------------| * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| * -msg_type * Bits 7:0 * Purpose: identifies this as HTT TX completion indication * -status * Bits 10:8 * Purpose: the TX completion status of payload fragmentations descriptors * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD * -tid * Bits 14:11 * Purpose: the tid associated with those fragmentation descriptors. It is * valid or not, depending on the tid_invalid bit. * Value: 0 to 15 * -tid_invalid * Bits 15:15 * Purpose: this bit indicates whether the tid field is valid or not * Value: 0 indicates valid, 1 indicates invalid * -num * Bits 23:16 * Purpose: the number of payload in this indication * Value: 1 to 255 * -A0 = append * Bits 24:24 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains * the number of tx retries for one MSDU at the end of this message * Value: 0 indicates no appending, 1 indicates appending * -A1 = append1 * Bits 25:25 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which * contains the timestamp info for each TX msdu id in payload. * Value: 0 indicates no appending, 1 indicates appending * -TP = MSDU tx power presence * Bits 26:26 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report * for each MSDU referenced by the TX_COMPL_IND message. * The order of the per-MSDU tx power reports matches the order * of the MSDU IDs. * Value: 0 indicates not appending, 1 indicates appending * -A2 = append2 * Bits 27:27 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report * matches the order of the MSDU IDs. * The ACK RSSI values are valid when status is COMPLETE_OK (and * this append2 bit is set). * Value: 0 indicates not appending, 1 indicates appending */ struct htt_data_tx_completion { … } __packed; #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK … #define HTT_TX_PPDU_DUR_INFO0_TID_MASK … struct htt_data_tx_ppdu_dur { … } __packed; #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK … struct htt_data_tx_compl_ppdu_dur { … } __packed; struct htt_tx_compl_ind_base { … } __packed; struct htt_rc_tx_done_params { … }; struct htt_rc_update { … } __packed; /* see htt_rx_indication for similar fields and descriptions */ struct htt_rx_fragment_indication { … } __packed; #define ATH10K_IEEE80211_EXTIV … #define ATH10K_IEEE80211_TKIP_MICLEN … #define HTT_RX_FRAG_IND_INFO0_HEADER_LEN … #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK … #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB … #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK … #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB … #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK … #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB … #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK … #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB … struct htt_rx_pn_ind { … } __packed; struct htt_rx_offload_msdu { … } __packed; struct htt_rx_offload_ind { … } __packed; struct htt_rx_in_ord_msdu_desc { … } __packed; struct htt_rx_in_ord_msdu_desc_ext { … } __packed; struct htt_rx_in_ord_ind { … } __packed; #define HTT_RX_IN_ORD_IND_INFO_TID_MASK … #define HTT_RX_IN_ORD_IND_INFO_TID_LSB … #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK … #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB … #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK … #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB … /* * target -> host test message definition * * The following field definitions describe the format of the test * message sent from the target to the host. * The message consists of a 4-octet header, followed by a variable * number of 32-bit integer values, followed by a variable number * of 8-bit character values. * * |31 16|15 8|7 0| * |-----------------------------------------------------------| * | num chars | num ints | msg type | * |-----------------------------------------------------------| * | int 0 | * |-----------------------------------------------------------| * | int 1 | * |-----------------------------------------------------------| * | ... | * |-----------------------------------------------------------| * | char 3 | char 2 | char 1 | char 0 | * |-----------------------------------------------------------| * | | | ... | char 4 | * |-----------------------------------------------------------| * - MSG_TYPE * Bits 7:0 * Purpose: identifies this as a test message * Value: HTT_MSG_TYPE_TEST * - NUM_INTS * Bits 15:8 * Purpose: indicate how many 32-bit integers follow the message header * - NUM_CHARS * Bits 31:16 * Purpose: indicate how many 8-bit characters follow the series of integers */ struct htt_rx_test { … } __packed; static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) { … } static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) { … } /* * target -> host packet log message * * The following field definitions describe the format of the packet log * message sent from the target to the host. * The message consists of a 4-octet header,followed by a variable number * of 32-bit character values. * * |31 24|23 16|15 8|7 0| * |-----------------------------------------------------------| * | | | | msg type | * |-----------------------------------------------------------| * | payload | * |-----------------------------------------------------------| * - MSG_TYPE * Bits 7:0 * Purpose: identifies this as a test message * Value: HTT_MSG_TYPE_PACKETLOG */ struct htt_pktlog_msg { … } __packed; struct htt_dbg_stats_rx_reorder_stats { … }; struct htt_dbg_stats_wal_tx_stats { … } __packed; struct htt_dbg_stats_wal_rx_stats { … } __packed; struct htt_dbg_stats_wal_peer_stats { … } __packed; struct htt_dbg_stats_wal_pdev_txrx { … } __packed; struct htt_dbg_stats_rx_rate_info { … }; /* * htt_dbg_stats_status - * present - The requested stats have been delivered in full. * This indicates that either the stats information was contained * in its entirety within this message, or else this message * completes the delivery of the requested stats info that was * partially delivered through earlier STATS_CONF messages. * partial - The requested stats have been delivered in part. * One or more subsequent STATS_CONF messages with the same * cookie value will be sent to deliver the remainder of the * information. * error - The requested stats could not be delivered, for example due * to a shortage of memory to construct a message holding the * requested stats. * invalid - The requested stat type is either not recognized, or the * target is configured to not gather the stats type in question. * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * series_done - This special value indicates that no further stats info * elements are present within a series of stats info elems * (within a stats upload confirmation message). */ enum htt_dbg_stats_status { … }; /* * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank * * The following field definitions describe the format of the HTT host * to target frag_desc/msdu_ext bank configuration message. * The message contains the based address and the min and max id of the * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and * MSDU_EXT/FRAG_DESC. * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 * the hardware does the mapping/translation. * * Total banks that can be configured is configured to 16. * * This should be called before any TX has be initiated by the HTT * * |31 16|15 8|7 5|4 0| * |------------------------------------------------------------| * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | * |------------------------------------------------------------| * | BANK0_BASE_ADDRESS | * |------------------------------------------------------------| * | ... | * |------------------------------------------------------------| * | BANK15_BASE_ADDRESS | * |------------------------------------------------------------| * | BANK0_MAX_ID | BANK0_MIN_ID | * |------------------------------------------------------------| * | ... | * |------------------------------------------------------------| * | BANK15_MAX_ID | BANK15_MIN_ID | * |------------------------------------------------------------| * Header fields: * - MSG_TYPE * Bits 7:0 * Value: 0x6 * - BANKx_BASE_ADDRESS * Bits 31:0 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT * bank physical/bus address. * - BANKx_MIN_ID * Bits 15:0 * Purpose: Provide a mechanism to specify the min index that needs to * mapped. * - BANKx_MAX_ID * Bits 31:16 * Purpose: Provide a mechanism to specify the max index that needs to * */ struct htt_frag_desc_bank_id { … } __packed; /* real is 16 but it wouldn't fit in the max htt message size * so we use a conservatively safe value for now */ #define HTT_FRAG_DESC_BANK_MAX … #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK … #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB … #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP … #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID … #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK … #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB … enum htt_q_depth_type { … }; #define HTT_TX_Q_STATE_NUM_PEERS … #define HTT_TX_Q_STATE_NUM_TIDS … #define HTT_TX_Q_STATE_ENTRY_SIZE … #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER … /** * struct htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config * * Defines host q state format and behavior. See htt_q_state. * * @paddr: Queue physical address * @num_peers: Number of supported peers * @num_tids: Number of supported TIDs * @record_size: Defines the size of each host q entry in bytes. In practice * however firmware (at least 10.4.3-00191) ignores this host * configuration value and uses hardcoded value of 1. * @record_multiplier: This is valid only when q depth type is MSDUs. It * defines the exponent for the power of 2 multiplication. * @pad: struct padding for 32-bit alignment */ struct htt_q_state_conf { … } __packed; struct htt_frag_desc_bank_cfg32 { … } __packed; struct htt_frag_desc_bank_cfg64 { … } __packed; #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT … #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK … #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB … #define HTT_TX_Q_STATE_ENTRY_EXP_MASK … #define HTT_TX_Q_STATE_ENTRY_EXP_LSB … /** * struct htt_q_state - shared between host and firmware via DMA * * This structure is used for the host to expose it's software queue state to * firmware so that its rate control can schedule fetch requests for optimized * performance. This is most notably used for MU-MIMO aggregation when multiple * MU clients are connected. * * @count: Each element defines the host queue depth. When q depth type was * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** * record_multiplier (see htt_q_state_conf). * @map: Used by firmware to quickly check which host queues are not empty. It * is a bitmap simply saying. * @seq: Used by firmware to quickly check if the host queues were updated * since it last checked. * * FIXME: Is the q_state map[] size calculation really correct? */ struct htt_q_state { … } __packed; #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK … #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB … #define HTT_TX_FETCH_RECORD_INFO_TID_MASK … #define HTT_TX_FETCH_RECORD_INFO_TID_LSB … struct htt_tx_fetch_record { … } __packed; struct htt_tx_fetch_ind { … } __packed; static inline void * ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) { … } struct htt_tx_fetch_resp { … } __packed; struct htt_tx_fetch_confirm { … } __packed; enum htt_tx_mode_switch_mode { … }; #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE … #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK … #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB … #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK … #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB … #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK … #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB … #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK … #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB … #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK … #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB … struct htt_tx_mode_switch_record { … } __packed; struct htt_tx_mode_switch_ind { … } __packed; struct htt_channel_change { … } __packed; struct htt_per_peer_tx_stats_ind { … } __packed; struct htt_peer_tx_stats { … } __packed; #define ATH10K_10_2_TX_STATS_OFFSET … #define PEER_STATS_FOR_NO_OF_PPDUS … struct ath10k_10_2_peer_tx_stats { … } __packed; htt_rx_pn_t; struct htt_cmd { … } __packed; struct htt_resp { … } __packed; /*** host side structures follow ***/ struct htt_tx_done { … }; enum htt_tx_compl_state { … }; struct htt_peer_map_event { … }; struct htt_peer_unmap_event { … }; struct ath10k_htt_txbuf_32 { … } __packed __aligned(…); struct ath10k_htt_txbuf_64 { … } __packed __aligned(…); struct ath10k_htt { … }; struct ath10k_htt_tx_ops { … }; static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt) { … } static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) { … } static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt) { … } static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt) { … } static inline int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, struct sk_buff *msdu) { … } static inline void ath10k_htt_flush_tx(struct ath10k_htt *htt) { … } static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt) { … } static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt) { … } static inline int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, u8 max_subfrms_ampdu, u8 max_subfrms_amsdu) { … } struct ath10k_htt_rx_ops { … }; static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt) { … } static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt, void *vaddr) { … } static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt, dma_addr_t paddr, int idx) { … } static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt) { … } static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx) { … } static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt, struct htt_rx_fragment_indication *rx, struct sk_buff *skb) { … } /* the driver strongly assumes that the rx header status be 64 bytes long, * so all possible rx_desc structures must respect this assumption. */ #define RX_HTT_HDR_STATUS_LEN … /* The rx descriptor structure layout is programmed via rx ring setup * so that FW knows how to transfer the rx descriptor to the host. * Unfortunately, though, QCA6174's firmware doesn't currently behave correctly * when modifying the structure layout of the rx descriptor beyond what it expects * (even if it correctly programmed during the rx ring setup). * Therefore we must keep two different memory layouts, abstract the rx descriptor * representation and use ath10k_rx_desc_ops * for correctly accessing rx descriptor data. */ /* base struct used for abstracting the rx descriptor representation */ struct htt_rx_desc { … } __packed; /* rx descriptor for wcn3990 and possibly extensible for newer cards * Buffers like this are placed on the rx ring. */ struct htt_rx_desc_v2 { … }; /* QCA6174, QCA988x, QCA99x0 dedicated rx descriptor to make sure their firmware * works correctly. We keep a single rx descriptor for all these three * families of cards because from tests it seems to be the most stable solution, * e.g. having a rx descriptor only for QCA6174 seldom caused firmware crashes * during some tests. * Buffers like this are placed on the rx ring. */ struct htt_rx_desc_v1 { … }; /* rx_desc abstraction */ struct ath10k_htt_rx_desc_ops { … }; extern const struct ath10k_htt_rx_desc_ops qca988x_rx_desc_ops; extern const struct ath10k_htt_rx_desc_ops qca99x0_rx_desc_ops; extern const struct ath10k_htt_rx_desc_ops wcn3990_rx_desc_ops; static inline int ath10k_htt_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline bool ath10k_htt_rx_desc_msdu_limit_error(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } /* The default implementation of all these getters is using the old rx_desc, * so that it is easier to define the ath10k_htt_rx_desc_ops instances. * But probably, if new wireless cards must be supported, it would be better * to switch the default implementation to the new rx_desc, since this would * make the extension easier . */ static inline struct htt_rx_desc * ath10k_htt_rx_desc_from_raw_buffer(struct ath10k_hw_params *hw, void *buff) { … } static inline void ath10k_htt_rx_desc_get_offsets(struct ath10k_hw_params *hw, struct htt_rx_ring_rx_desc_offsets *off) { … } static inline struct rx_attention * ath10k_htt_rx_desc_get_attention(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_frag_info_common * ath10k_htt_rx_desc_get_frag_info(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_mpdu_start * ath10k_htt_rx_desc_get_mpdu_start(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_mpdu_end * ath10k_htt_rx_desc_get_mpdu_end(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_msdu_start_common * ath10k_htt_rx_desc_get_msdu_start(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_msdu_end_common * ath10k_htt_rx_desc_get_msdu_end(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_ppdu_start * ath10k_htt_rx_desc_get_ppdu_start(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline struct rx_ppdu_end_common * ath10k_htt_rx_desc_get_ppdu_end(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline u8 * ath10k_htt_rx_desc_get_rx_hdr_status(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } static inline u8 * ath10k_htt_rx_desc_get_msdu_payload(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) { … } #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK … #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB … #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK … #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB … #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK … #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB … #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK … #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB … #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK … #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB … struct htt_rx_desc_base_hl { … }; struct htt_rx_chan_info { … } __packed; #define HTT_RX_DESC_ALIGN … #define HTT_MAC_ADDR_LEN … /* * FIX THIS * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, * rounded up to a cache line size. */ #define HTT_RX_BUF_SIZE … /* The HTT_RX_MSDU_SIZE can't be statically computed anymore, * because it depends on the underlying device rx_desc representation */ static inline int ath10k_htt_rx_msdu_size(struct ath10k_hw_params *hw) { … } /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle * aggregated traffic more nicely. */ #define ATH10K_HTT_MAX_NUM_REFILL … /* * DMA_MAP expects the buffer to be an integral number of cache lines. * Rather than checking the actual cache line size, this code makes a * conservative estimate of what the cache line size could be. */ #define HTT_LOG2_MAX_CACHE_LINE_SIZE … #define HTT_MAX_CACHE_LINE_SIZE_MASK … /* These values are default in most firmware revisions and apparently are a * sweet spot performance wise. */ #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT … #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT … int ath10k_htt_connect(struct ath10k_htt *htt); int ath10k_htt_init(struct ath10k *ar); int ath10k_htt_setup(struct ath10k_htt *htt); int ath10k_htt_tx_start(struct ath10k_htt *htt); void ath10k_htt_tx_stop(struct ath10k_htt *htt); void ath10k_htt_tx_destroy(struct ath10k_htt *htt); void ath10k_htt_tx_free(struct ath10k_htt *htt); int ath10k_htt_rx_alloc(struct ath10k_htt *htt); int ath10k_htt_rx_ring_refill(struct ath10k *ar); void ath10k_htt_rx_free(struct ath10k_htt *htt); void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, u64 cookie); void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); int ath10k_htt_tx_fetch_resp(struct ath10k *ar, __le32 token, __le16 fetch_seq_num, struct htt_tx_fetch_record *records, size_t num_records); void ath10k_htt_op_ep_tx_credits(struct ath10k *ar); void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, struct ieee80211_txq *txq); void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, struct ieee80211_txq *txq); void ath10k_htt_tx_txq_sync(struct ath10k *ar); void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, bool is_presp); int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, struct sk_buff *skb); int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); int ath10k_htt_rx_hl_indication(struct ath10k *ar, int budget); void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); #endif
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