hw.c | Explore in Territory

// SPDX-License-Identifier: ISC
/*
 * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.
 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include "core.h"
#include "hw.h"
#include "hif.h"
#include "wmi-ops.h"
#include "bmi.h"
#include "rx_desc.h"

const struct ath10k_hw_regs qca988x_regs = …;

const struct ath10k_hw_regs qca6174_regs = …;

const struct ath10k_hw_regs qca99x0_regs = …;

const struct ath10k_hw_regs qca4019_regs = …;

const struct ath10k_hw_values qca988x_values = …;

const struct ath10k_hw_values qca6174_values = …;

const struct ath10k_hw_values qca99x0_values = …;

const struct ath10k_hw_values qca9888_values = …;

const struct ath10k_hw_values qca4019_values = …;

const struct ath10k_hw_regs wcn3990_regs = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = …;

static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = …;

static struct ath10k_hw_ce_host_ie wcn3990_host_ie = …;

static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = …;

static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = …;

static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = …;

static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = …;

static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = …;

static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = …;

const struct ath10k_hw_ce_regs wcn3990_ce_regs = …;

const struct ath10k_hw_values wcn3990_values = …;

static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = …;

static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = …;

static struct ath10k_hw_ce_regs_addr_map qcax_dmax = …;

static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = …;

static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = …;

static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = …;

static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = …;

static struct ath10k_hw_ce_host_ie qcax_host_ie = …;

static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = …;

static struct ath10k_hw_ce_misc_regs qcax_misc_reg = …;

static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = …;

static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = …;

static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = …;

static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = …;

static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = …;

static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = …;

const struct ath10k_hw_ce_regs qcax_ce_regs = …;

const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = …;

void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
{ … }

/* The firmware does not support setting the coverage class. Instead this
 * function monitors and modifies the corresponding MAC registers.
 */
static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
						 s16 value)
{ … }

/**
 * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
 * @ar: the ath10k blob
 *
 * This function is very hardware specific, the clock initialization
 * steps is very sensitive and could lead to unknown crash, so they
 * should be done in sequence.
 *
 * *** Be aware if you planned to refactor them. ***
 *
 * Return: 0 if successfully enable the pll, otherwise EINVAL
 */
static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar)
{ … }

/* Program CPU_ADDR_MSB to allow different memory
 * region access.
 */
static void ath10k_hw_map_target_mem(struct ath10k *ar, u32 msb)
{ … }

/* 1. Write to memory region of target, such as IRAM and DRAM.
 * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)
 *    can be written directly. See ath10k_pci_targ_cpu_to_ce_addr() too.
 * 3. In order to access the region other than the above,
 *    we need to set the value of register CPU_ADDR_MSB.
 * 4. Target memory access space is limited to 1M size. If the size is larger
 *    than 1M, need to split it and program CPU_ADDR_MSB accordingly.
 */
static int ath10k_hw_diag_segment_msb_download(struct ath10k *ar,
					       const void *buffer,
					       u32 address,
					       u32 length)
{ … }

static int ath10k_hw_diag_segment_download(struct ath10k *ar,
					   const void *buffer,
					   u32 address,
					   u32 length)
{ … }

int ath10k_hw_diag_fast_download(struct ath10k *ar,
				 u32 address,
				 const void *buffer,
				 u32 length)
{ … }

static int ath10k_htt_tx_rssi_enable(struct htt_resp *resp)
{ … }

static int ath10k_htt_tx_rssi_enable_wcn3990(struct htt_resp *resp)
{ … }

static int ath10k_get_htt_tx_data_rssi_pad(struct htt_resp *resp)
{ … }

const struct ath10k_hw_ops qca988x_ops = …;

const struct ath10k_hw_ops qca99x0_ops = …;

const struct ath10k_hw_ops qca6174_ops = …;

const struct ath10k_hw_ops qca6174_sdio_ops = …;

const struct ath10k_hw_ops wcn3990_ops = …;
linux/drivers/net/wireless/ath/ath10k/hw.c
