/* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _PCI_H_ #define _PCI_H_ #include <linux/interrupt.h> #include <linux/mutex.h> #include "hw.h" #include "ce.h" #include "ahb.h" /* * maximum number of bytes that can be * handled atomically by DiagRead/DiagWrite */ #define DIAG_TRANSFER_LIMIT … struct bmi_xfer { … }; /* * PCI-specific Target state * * NOTE: Structure is shared between Host software and Target firmware! * * Much of this may be of interest to the Host so * HOST_INTEREST->hi_interconnect_state points here * (and all members are 32-bit quantities in order to * facilitate Host access). In particular, Host software is * required to initialize pipe_cfg_addr and svc_to_pipe_map. */ struct pcie_state { … }; /* PCIE_CONFIG_FLAG definitions */ #define PCIE_CONFIG_FLAG_ENABLE_L1 … /* Per-pipe state. */ struct ath10k_pci_pipe { … }; struct ath10k_pci_supp_chip { … }; enum ath10k_pci_irq_mode { … }; struct ath10k_pci { … }; static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) { … } #define ATH10K_PCI_RX_POST_RETRY_MS … #define ATH_PCI_RESET_WAIT_MAX … #define PCIE_WAKE_TIMEOUT … #define PCIE_WAKE_LATE_US … #define BAR_NUM … #define CDC_WAR_MAGIC_STR … #define CDC_WAR_DATA_CE … /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */ #define DIAG_ACCESS_CE_TIMEOUT_US … #define DIAG_ACCESS_CE_WAIT_US … void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value); void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val); void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val); u32 ath10k_pci_read32(struct ath10k *ar, u32 offset); u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr); u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr); int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, struct ath10k_hif_sg_item *items, int n_items); int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, size_t buf_len); int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, const void *data, int nbytes); int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len, void *resp, u32 *resp_len); int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, u8 *ul_pipe, u8 *dl_pipe); void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, u8 *dl_pipe); void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, int force); u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe); void ath10k_pci_hif_power_down(struct ath10k *ar); int ath10k_pci_alloc_pipes(struct ath10k *ar); void ath10k_pci_free_pipes(struct ath10k *ar); void ath10k_pci_rx_replenish_retry(struct timer_list *t); void ath10k_pci_ce_deinit(struct ath10k *ar); void ath10k_pci_init_napi(struct ath10k *ar); int ath10k_pci_init_pipes(struct ath10k *ar); int ath10k_pci_init_config(struct ath10k *ar); void ath10k_pci_rx_post(struct ath10k *ar); void ath10k_pci_flush(struct ath10k *ar); void ath10k_pci_enable_intx_irq(struct ath10k *ar); bool ath10k_pci_irq_pending(struct ath10k *ar); void ath10k_pci_disable_and_clear_intx_irq(struct ath10k *ar); void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar); int ath10k_pci_wait_for_target_init(struct ath10k *ar); int ath10k_pci_setup_resource(struct ath10k *ar); void ath10k_pci_release_resource(struct ath10k *ar); /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too * frequently. To avoid this put SoC to sleep after a very conservative grace * period. Adjust with great care. */ #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC … #endif /* _PCI_H_ */
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