// SPDX-License-Identifier: ISC /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/pci.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/spinlock.h> #include <linux/bitops.h> #include "core.h" #include "debug.h" #include "coredump.h" #include "targaddrs.h" #include "bmi.h" #include "hif.h" #include "htc.h" #include "ce.h" #include "pci.h" enum ath10k_pci_reset_mode { … }; static unsigned int ath10k_pci_irq_mode = …; static unsigned int ath10k_pci_reset_mode = …; module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); MODULE_PARM_DESC(…) …; module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); MODULE_PARM_DESC(…) …; /* how long wait to wait for target to initialise, in ms */ #define ATH10K_PCI_TARGET_WAIT … #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS … /* Maximum number of bytes that can be handled atomically by * diag read and write. */ #define ATH10K_DIAG_TRANSFER_LIMIT … #define QCA99X0_PCIE_BAR0_START_REG … #define QCA99X0_CPU_MEM_ADDR_REG … #define QCA99X0_CPU_MEM_DATA_REG … static const struct pci_device_id ath10k_pci_id_table[] = …; static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = …; static void ath10k_pci_buffer_cleanup(struct ath10k *ar); static int ath10k_pci_cold_reset(struct ath10k *ar); static int ath10k_pci_safe_chip_reset(struct ath10k *ar); static int ath10k_pci_init_irq(struct ath10k *ar); static int ath10k_pci_deinit_irq(struct ath10k *ar); static int ath10k_pci_request_irq(struct ath10k *ar); static void ath10k_pci_free_irq(struct ath10k *ar); static int ath10k_pci_bmi_wait(struct ath10k *ar, struct ath10k_ce_pipe *tx_pipe, struct ath10k_ce_pipe *rx_pipe, struct bmi_xfer *xfer); static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); static const struct ce_attr pci_host_ce_config_wlan[] = …; /* Target firmware's Copy Engine configuration. */ static const struct ce_pipe_config pci_target_ce_config_wlan[] = …; /* * Map from service/endpoint to Copy Engine. * This table is derived from the CE_PCI TABLE, above. * It is passed to the Target at startup for use by firmware. */ static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = …; static bool ath10k_pci_is_awake(struct ath10k *ar) { … } static void __ath10k_pci_wake(struct ath10k *ar) { … } static void __ath10k_pci_sleep(struct ath10k *ar) { … } static int ath10k_pci_wake_wait(struct ath10k *ar) { … } static int ath10k_pci_force_wake(struct ath10k *ar) { … } static void ath10k_pci_force_sleep(struct ath10k *ar) { … } static int ath10k_pci_wake(struct ath10k *ar) { … } static void ath10k_pci_sleep(struct ath10k *ar) { … } static void ath10k_pci_ps_timer(struct timer_list *t) { … } static void ath10k_pci_sleep_sync(struct ath10k *ar) { … } static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) { … } static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) { … } inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) { … } inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) { … } u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) { … } void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) { … } u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) { … } void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) { … } bool ath10k_pci_irq_pending(struct ath10k *ar) { … } void ath10k_pci_disable_and_clear_intx_irq(struct ath10k *ar) { … } void ath10k_pci_enable_intx_irq(struct ath10k *ar) { … } static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) { … } static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) { … } static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) { … } void ath10k_pci_rx_post(struct ath10k *ar) { … } void ath10k_pci_rx_replenish_retry(struct timer_list *t) { … } static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { … } /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. * Support to access target space below 1M for qca6174 and qca9377. * If target space is below 1M, the bit[20] of converted CE addr is 0. * Otherwise bit[20] of converted CE addr is 1. */ static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { … } static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { … } static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) { … } /* * Diagnostic read/write access is provided for startup/config/debug usage. * Caller must guarantee proper alignment, when applicable, and single user * at any moment. */ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, int nbytes) { … } static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) { … } static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, u32 src, u32 len) { … } #define ath10k_pci_diag_read_hi(ar, dest, src, len) … int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, const void *data, int nbytes) { … } static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) { … } /* Called by lower (CE) layer when a send to Target completes. */ static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) { … } static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, void (*callback)(struct ath10k *ar, struct sk_buff *skb)) { … } static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, void (*callback)(struct ath10k *ar, struct sk_buff *skb)) { … } /* Called by lower (CE) layer when data is received from the Target. */ static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { … } static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) { … } /* Called by lower (CE) layer when data is received from the Target. * Only 10.4 firmware uses separate CE to transfer pktlog data. */ static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) { … } /* Called by lower (CE) layer when a send to HTT Target completes. */ static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) { … } static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) { … } /* Called by lower (CE) layer when HTT data is received from the Target. */ static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) { … } int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, struct ath10k_hif_sg_item *items, int n_items) { … } int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, size_t buf_len) { … } u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) { … } static void ath10k_pci_dump_registers(struct ath10k *ar, struct ath10k_fw_crash_data *crash_data) { … } static int ath10k_pci_dump_memory_section(struct ath10k *ar, const struct ath10k_mem_region *mem_region, u8 *buf, size_t buf_len) { … } static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) { … } /* Always returns the length */ static int ath10k_pci_dump_memory_sram(struct ath10k *ar, const struct ath10k_mem_region *region, u8 *buf) { … } /* if an error happened returns < 0, otherwise the length */ static int ath10k_pci_dump_memory_reg(struct ath10k *ar, const struct ath10k_mem_region *region, u8 *buf) { … } /* if an error happened returns < 0, otherwise the length */ static int ath10k_pci_dump_memory_generic(struct ath10k *ar, const struct ath10k_mem_region *current_region, u8 *buf) { … } static void ath10k_pci_dump_memory(struct ath10k *ar, struct ath10k_fw_crash_data *crash_data) { … } static void ath10k_pci_fw_dump_work(struct work_struct *work) { … } static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) { … } void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, int force) { … } static void ath10k_pci_rx_retry_sync(struct ath10k *ar) { … } int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, u8 *ul_pipe, u8 *dl_pipe) { … } void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, u8 *dl_pipe) { … } void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) { … } static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) { … } static void ath10k_pci_irq_disable(struct ath10k *ar) { … } static void ath10k_pci_irq_sync(struct ath10k *ar) { … } static void ath10k_pci_irq_enable(struct ath10k *ar) { … } static int ath10k_pci_hif_start(struct ath10k *ar) { … } static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) { … } static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) { … } /* * Cleanup residual buffers for device shutdown: * buffers that were enqueued for receive * buffers that were to be sent * Note: Buffers that had completed but which were * not yet processed are on a completion queue. They * are handled when the completion thread shuts down. */ static void ath10k_pci_buffer_cleanup(struct ath10k *ar) { … } void ath10k_pci_ce_deinit(struct ath10k *ar) { … } void ath10k_pci_flush(struct ath10k *ar) { … } static void ath10k_pci_hif_stop(struct ath10k *ar) { … } int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len, void *resp, u32 *resp_len) { … } static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) { … } static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) { … } static int ath10k_pci_bmi_wait(struct ath10k *ar, struct ath10k_ce_pipe *tx_pipe, struct ath10k_ce_pipe *rx_pipe, struct bmi_xfer *xfer) { … } /* * Send an interrupt to the device to wake up the Target CPU * so it has an opportunity to notice any changed state. */ static int ath10k_pci_wake_target_cpu(struct ath10k *ar) { … } static int ath10k_pci_get_num_banks(struct ath10k *ar) { … } static int ath10k_bus_get_num_banks(struct ath10k *ar) { … } int ath10k_pci_init_config(struct ath10k *ar) { … } static void ath10k_pci_override_ce_config(struct ath10k *ar) { … } int ath10k_pci_alloc_pipes(struct ath10k *ar) { … } void ath10k_pci_free_pipes(struct ath10k *ar) { … } int ath10k_pci_init_pipes(struct ath10k *ar) { … } static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) { … } static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) { … } static bool ath10k_pci_has_device_gone(struct ath10k *ar) { … } /* this function effectively clears target memory controller assert line */ static void ath10k_pci_warm_reset_si0(struct ath10k *ar) { … } static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) { … } static void ath10k_pci_warm_reset_ce(struct ath10k *ar) { … } static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) { … } static int ath10k_pci_warm_reset(struct ath10k *ar) { … } static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) { … } static int ath10k_pci_safe_chip_reset(struct ath10k *ar) { … } static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) { … } static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) { … } static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) { … } static int ath10k_pci_chip_reset(struct ath10k *ar) { … } static int ath10k_pci_hif_power_up(struct ath10k *ar, enum ath10k_firmware_mode fw_mode) { … } void ath10k_pci_hif_power_down(struct ath10k *ar) { … } static int ath10k_pci_hif_suspend(struct ath10k *ar) { … } static int ath10k_pci_suspend(struct ath10k *ar) { … } static int ath10k_pci_hif_resume(struct ath10k *ar) { … } static int ath10k_pci_resume(struct ath10k *ar) { … } static bool ath10k_pci_validate_cal(void *data, size_t size) { … } static void ath10k_pci_enable_eeprom(struct ath10k *ar) { … } static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) { … } static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, size_t *data_len) { … } static const struct ath10k_hif_ops ath10k_pci_hif_ops = …; /* * Top-level interrupt handler for all PCI interrupts from a Target. * When a block of MSI interrupts is allocated, this top-level handler * is not used; instead, we directly call the correct sub-handler. */ static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) { … } static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) { … } static int ath10k_pci_request_irq_msi(struct ath10k *ar) { … } static int ath10k_pci_request_irq_intx(struct ath10k *ar) { … } static int ath10k_pci_request_irq(struct ath10k *ar) { … } static void ath10k_pci_free_irq(struct ath10k *ar) { … } void ath10k_pci_init_napi(struct ath10k *ar) { … } static int ath10k_pci_init_irq(struct ath10k *ar) { … } static void ath10k_pci_deinit_irq_intx(struct ath10k *ar) { … } static int ath10k_pci_deinit_irq(struct ath10k *ar) { … } int ath10k_pci_wait_for_target_init(struct ath10k *ar) { … } static int ath10k_pci_cold_reset(struct ath10k *ar) { … } static int ath10k_pci_claim(struct ath10k *ar) { … } static void ath10k_pci_release(struct ath10k *ar) { … } static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) { … } int ath10k_pci_setup_resource(struct ath10k *ar) { … } void ath10k_pci_release_resource(struct ath10k *ar) { … } static const struct ath10k_bus_ops ath10k_pci_bus_ops = …; static int ath10k_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_dev) { … } static void ath10k_pci_remove(struct pci_dev *pdev) { … } MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) { … } static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, ath10k_pci_pm_suspend, ath10k_pci_pm_resume); static struct pci_driver ath10k_pci_driver = …; static int __init ath10k_pci_init(void) { … } module_init(…) …; static void __exit ath10k_pci_exit(void) { … } module_exit(ath10k_pci_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; /* QCA988x 2.0 firmware files */ MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; /* QCA9887 1.0 firmware files */ MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; /* QCA6174 2.1 firmware files */ MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; /* QCA6174 3.1 firmware files */ MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; /* QCA9377 1.0 firmware files */ MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …;
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