/* * Copyright (c) 2013 Eugene Krasnikov <[email protected]> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef _DXE_H_ #define _DXE_H_ #include "wcn36xx.h" /* TX_LOW = DMA0 TX_HIGH = DMA4 RX_LOW = DMA1 RX_HIGH = DMA3 H2H_TEST_RX_TX = DMA2 */ /* DXE registers */ #define WCN36XX_DXE_MEM_REG … #define WCN36XX_CCU_DXE_INT_SELECT_RIVA … #define WCN36XX_CCU_DXE_INT_SELECT_PRONTO … /* Descriptor valid */ #define WCN36xx_DXE_CTRL_VLD … /* End of packet */ #define WCN36xx_DXE_CTRL_EOP … /* BD handling bit */ #define WCN36xx_DXE_CTRL_BDH … /* Source is a queue */ #define WCN36xx_DXE_CTRL_SIQ … /* Destination is a queue */ #define WCN36xx_DXE_CTRL_DIQ … /* Pointer address is a queue */ #define WCN36xx_DXE_CTRL_PIQ … /* Release PDU when done */ #define WCN36xx_DXE_CTRL_PDU_REL … /* STOP channel processing */ #define WCN36xx_DXE_CTRL_STOP … /* INT on descriptor done */ #define WCN36xx_DXE_CTRL_INT … /* Endian byte swap enable */ #define WCN36xx_DXE_CTRL_SWAP … /* Master endianness */ #define WCN36xx_DXE_CTRL_ENDIANNESS … /* Transfer type */ #define WCN36xx_DXE_CTRL_XTYPE_SHIFT … #define WCN36xx_DXE_CTRL_XTYPE_MASK … #define WCN36xx_DXE_CTRL_XTYPE_SET(x) … /* BMU Threshold select */ #define WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT … #define WCN36xx_DXE_CTRL_BTHLD_SEL_MASK … #define WCN36xx_DXE_CTRL_BTHLD_SEL_SET(x) … /* Priority */ #define WCN36xx_DXE_CTRL_PRIO_SHIFT … #define WCN36xx_DXE_CTRL_PRIO_MASK … #define WCN36xx_DXE_CTRL_PRIO_SET(x) … /* BD Template index */ #define WCN36xx_DXE_CTRL_BDT_IDX_SHIFT … #define WCN36xx_DXE_CTRL_BDT_IDX_MASK … #define WCN36xx_DXE_CTRL_BDT_IDX_SET(x) … /* Transfer types: */ /* Host to host */ #define WCN36xx_DXE_XTYPE_H2H … /* Host to BMU */ #define WCN36xx_DXE_XTYPE_H2B … /* BMU to host */ #define WCN36xx_DXE_XTYPE_B2H … #define WCN36XX_DXE_CTRL_TX_L … #define WCN36XX_DXE_CTRL_TX_H … #define WCN36XX_DXE_CTRL_RX_L … #define WCN36XX_DXE_CTRL_RX_H … #define WCN36XX_DXE_CTRL_TX_H_BD … #define WCN36XX_DXE_CTRL_TX_H_SKB … #define WCN36XX_DXE_CTRL_TX_L_BD … #define WCN36XX_DXE_CTRL_TX_L_SKB … /* TODO This must calculated properly but not hardcoded */ #define WCN36XX_DXE_WQ_TX_L(wcn) … #define WCN36XX_DXE_WQ_TX_H(wcn) … #define WCN36XX_DXE_WQ_RX_L … #define WCN36XX_DXE_WQ_RX_H … /* Channel enable or restart */ #define WCN36xx_DXE_CH_CTRL_EN … /* End of packet bit */ #define WCN36xx_DXE_CH_CTRL_EOP … /* BD Handling bit */ #define WCN36xx_DXE_CH_CTRL_BDH … /* Source is queue */ #define WCN36xx_DXE_CH_CTRL_SIQ … /* Destination is queue */ #define WCN36xx_DXE_CH_CTRL_DIQ … /* Pointer descriptor is queue */ #define WCN36xx_DXE_CH_CTRL_PIQ … /* Relase PDU when done */ #define WCN36xx_DXE_CH_CTRL_PDU_REL … /* Stop channel processing */ #define WCN36xx_DXE_CH_CTRL_STOP … /* Enable external descriptor interrupt */ #define WCN36xx_DXE_CH_CTRL_INE_ED … /* Enable channel interrupt on errors */ #define WCN36xx_DXE_CH_CTRL_INE_ERR … /* Enable Channel interrupt when done */ #define WCN36xx_DXE_CH_CTRL_INE_DONE … /* External descriptor enable */ #define WCN36xx_DXE_CH_CTRL_EDEN … /* Wait for valid bit */ #define WCN36xx_DXE_CH_CTRL_EDVEN … /* Endianness is little endian*/ #define WCN36xx_DXE_CH_CTRL_ENDIANNESS … /* Abort transfer */ #define WCN36xx_DXE_CH_CTRL_ABORT … /* Long descriptor format */ #define WCN36xx_DXE_CH_CTRL_DFMT … /* Endian byte swap enable */ #define WCN36xx_DXE_CH_CTRL_SWAP … /* Transfer type */ #define WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT … #define WCN36xx_DXE_CH_CTRL_XTYPE_MASK … #define WCN36xx_DXE_CH_CTRL_XTYPE_SET(x) … /* Channel BMU Threshold select */ #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT … #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK … #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(x) … /* Channel Priority */ #define WCN36xx_DXE_CH_CTRL_PRIO_SHIFT … #define WCN36xx_DXE_CH_CTRL_PRIO_MASK … #define WCN36xx_DXE_CH_CTRL_PRIO_SET(x) … /* Counter select */ #define WCN36xx_DXE_CH_CTRL_SEL_SHIFT … #define WCN36xx_DXE_CH_CTRL_SEL_MASK … #define WCN36xx_DXE_CH_CTRL_SEL_SET(x) … /* Channel BD template index */ #define WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT … #define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK … #define WCN36xx_DXE_CH_CTRL_BDT_IDX_SET(x) … /* DXE default control register values */ #define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L … #define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H … #define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H … #define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L … /* Common DXE registers */ #define WCN36XX_DXE_MEM_CSR … #define WCN36XX_DXE_REG_CSR_RESET … #define WCN36XX_DXE_ENCH_ADDR … #define WCN36XX_DXE_REG_CH_EN … #define WCN36XX_DXE_REG_CH_DONE … #define WCN36XX_DXE_REG_CH_ERR … #define WCN36XX_DXE_INT_MASK_REG … #define WCN36XX_DXE_INT_SRC_RAW_REG … /* #define WCN36XX_DXE_INT_CH6_MASK 0x00000040 */ /* #define WCN36XX_DXE_INT_CH5_MASK 0x00000020 */ #define WCN36XX_DXE_INT_CH4_MASK … #define WCN36XX_DXE_INT_CH3_MASK … /* #define WCN36XX_DXE_INT_CH2_MASK 0x00000004 */ #define WCN36XX_DXE_INT_CH1_MASK … #define WCN36XX_DXE_INT_CH0_MASK … #define WCN36XX_DXE_0_INT_CLR … #define WCN36XX_DXE_0_INT_ED_CLR … #define WCN36XX_DXE_0_INT_DONE_CLR … #define WCN36XX_DXE_0_INT_ERR_CLR … #define WCN36XX_CH_STAT_INT_DONE_MASK … #define WCN36XX_CH_STAT_INT_ERR_MASK … #define WCN36XX_CH_STAT_INT_ED_MASK … #define WCN36XX_DXE_0_CH0_STATUS … #define WCN36XX_DXE_0_CH1_STATUS … #define WCN36XX_DXE_0_CH2_STATUS … #define WCN36XX_DXE_0_CH3_STATUS … #define WCN36XX_DXE_0_CH4_STATUS … #define WCN36XX_DXE_REG_RESET … /* Temporary BMU Workqueue 4 */ #define WCN36XX_DXE_BMU_WQ_RX_LOW … #define WCN36XX_DXE_BMU_WQ_RX_HIGH … /* DMA channel offset */ #define WCN36XX_DXE_TX_LOW_OFFSET … #define WCN36XX_DXE_TX_HIGH_OFFSET … #define WCN36XX_DXE_RX_LOW_OFFSET … #define WCN36XX_DXE_RX_HIGH_OFFSET … /* Address of the next DXE descriptor */ #define WCN36XX_DXE_CH_NEXT_DESC_ADDR … #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L … #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H … #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L … #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H … /* DXE Descriptor source address */ #define WCN36XX_DXE_CH_SRC_ADDR … #define WCN36XX_DXE_CH_SRC_ADDR_RX_L … #define WCN36XX_DXE_CH_SRC_ADDR_RX_H … /* DXE Descriptor address destination address */ #define WCN36XX_DXE_CH_DEST_ADDR … #define WCN36XX_DXE_CH_DEST_ADDR_TX_L … #define WCN36XX_DXE_CH_DEST_ADDR_TX_H … #define WCN36XX_DXE_CH_DEST_ADDR_RX_L … #define WCN36XX_DXE_CH_DEST_ADDR_RX_H … /* Interrupt status */ #define WCN36XX_DXE_CH_STATUS_REG_ADDR … #define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L … #define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H … #define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L … #define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H … /* DXE default control register */ #define WCN36XX_DXE_REG_CTL_RX_L … #define WCN36XX_DXE_REG_CTL_RX_H … #define WCN36XX_DXE_REG_CTL_TX_H … #define WCN36XX_DXE_REG_CTL_TX_L … #define WCN36XX_SMSM_WLAN_TX_ENABLE … #define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY … /* Interrupt control channel mask */ #define WCN36XX_INT_MASK_CHAN_TX_L … #define WCN36XX_INT_MASK_CHAN_RX_L … #define WCN36XX_INT_MASK_CHAN_RX_H … #define WCN36XX_INT_MASK_CHAN_TX_H … #define WCN36XX_BD_CHUNK_SIZE … #define WCN36XX_PKT_SIZE … enum wcn36xx_dxe_ch_type { … }; /* amount of descriptors per channel */ enum wcn36xx_dxe_ch_desc_num { … }; /** * struct wcn36xx_dxe_desc - describes descriptor of one DXE buffer * * @ctrl: is a union that consists of following bits: * union { * u32 valid :1; //0 = DMA stop, 1 = DMA continue with this * //descriptor * u32 transfer_type :2; //0 = Host to Host space * u32 eop :1; //End of Packet * u32 bd_handling :1; //if transferType = Host to BMU, then 0 * // means first 128 bytes contain BD, and 1 * // means create new empty BD * u32 siq :1; // SIQ * u32 diq :1; // DIQ * u32 pdu_rel :1; //0 = don't release BD and PDUs when done, * // 1 = release them * u32 bthld_sel :4; //BMU Threshold Select * u32 prio :3; //Specifies the priority level to use for * // the transfer * u32 stop_channel :1; //1 = DMA stops processing further, channel * //requires re-enabling after this * u32 intr :1; //Interrupt on Descriptor Done * u32 rsvd :1; //reserved * u32 size :14;//14 bits used - ignored for BMU transfers, * //only used for host to host transfers? * } ctrl; */ struct wcn36xx_dxe_desc { … } __packed; /* DXE Control block */ struct wcn36xx_dxe_ctl { … }; struct wcn36xx_dxe_ch { … }; /* Memory Pool for BD headers */ struct wcn36xx_dxe_mem_pool { … }; struct wcn36xx_tx_bd; struct wcn36xx_vif; int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn); void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn); void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn); int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn); void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn); int wcn36xx_dxe_init(struct wcn36xx *wcn); void wcn36xx_dxe_deinit(struct wcn36xx *wcn); int wcn36xx_dxe_init_channels(struct wcn36xx *wcn); int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn, struct wcn36xx_vif *vif_priv, struct wcn36xx_tx_bd *bd, struct sk_buff *skb, bool is_low); int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn); void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status); #endif /* _DXE_H_ */
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