/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_HAL_H #define ATH11K_HAL_H #include "hal_desc.h" #include "rx_desc.h" struct ath11k_base; #define HAL_LINK_DESC_SIZE … #define HAL_LINK_DESC_ALIGN … #define HAL_NUM_MPDUS_PER_LINK_DESC … #define HAL_NUM_TX_MSDUS_PER_LINK_DESC … #define HAL_NUM_RX_MSDUS_PER_LINK_DESC … #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC … #define HAL_MAX_AVAIL_BLK_RES … #define HAL_RING_BASE_ALIGN … #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX … /* TODO: Check with hw team on the supported scatter buf size */ #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE … #define HAL_WBM_IDLE_SCATTER_BUF_SIZE … #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX … #define HAL_DSCP_TID_TBL_SIZE … /* calculate the register address from bar0 of shadow register x */ #define HAL_SHADOW_BASE_ADDR(ab) … #define HAL_SHADOW_NUM_REGS … #define HAL_HP_OFFSET_IN_REG_START … #define HAL_OFFSET_FROM_HP_TO_TP … #define HAL_SHADOW_REG(ab, x) … /* WCSS Relative address */ #define HAL_SEQ_WCSS_UMAC_OFFSET … #define HAL_SEQ_WCSS_UMAC_REO_REG … #define HAL_SEQ_WCSS_UMAC_TCL_REG … #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) … #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) … #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) … #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) … #define HAL_SEQ_WCSS_UMAC_WBM_REG … #define HAL_CE_WFSS_CE_REG_BASE … #define HAL_WLAON_REG_BASE … /* SW2TCL(x) R0 ring configuration address */ #define HAL_TCL1_RING_CMN_CTRL_REG … #define HAL_TCL1_RING_DSCP_TID_MAP … #define HAL_TCL1_RING_BASE_LSB(ab) … #define HAL_TCL1_RING_BASE_MSB(ab) … #define HAL_TCL1_RING_ID(ab) … #define HAL_TCL1_RING_MISC(ab) … #define HAL_TCL1_RING_TP_ADDR_LSB(ab) … #define HAL_TCL1_RING_TP_ADDR_MSB(ab) … #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) … #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) … #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) … #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) … #define HAL_TCL1_RING_MSI1_DATA(ab) … #define HAL_TCL2_RING_BASE_LSB(ab) … #define HAL_TCL_RING_BASE_LSB(ab) … #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) … #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) … #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) … #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) … #define HAL_TCL1_RING_ID_OFFSET(ab) … #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) … #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) … #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) … #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) … #define HAL_TCL1_RING_MISC_OFFSET(ab) … /* SW2TCL(x) R2 ring pointers (head/tail) address */ #define HAL_TCL1_RING_HP … #define HAL_TCL1_RING_TP … #define HAL_TCL2_RING_HP … #define HAL_TCL_RING_HP … #define HAL_TCL1_RING_TP_OFFSET … /* TCL STATUS ring address */ #define HAL_TCL_STATUS_RING_BASE_LSB(ab) … #define HAL_TCL_STATUS_RING_HP … /* REO2SW(x) R0 ring configuration address */ #define HAL_REO1_GEN_ENABLE … #define HAL_REO1_DEST_RING_CTRL_IX_0 … #define HAL_REO1_DEST_RING_CTRL_IX_1 … #define HAL_REO1_DEST_RING_CTRL_IX_2 … #define HAL_REO1_DEST_RING_CTRL_IX_3 … #define HAL_REO1_MISC_CTL(ab) … #define HAL_REO1_RING_BASE_LSB(ab) … #define HAL_REO1_RING_BASE_MSB(ab) … #define HAL_REO1_RING_ID(ab) … #define HAL_REO1_RING_MISC(ab) … #define HAL_REO1_RING_HP_ADDR_LSB(ab) … #define HAL_REO1_RING_HP_ADDR_MSB(ab) … #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) … #define HAL_REO1_RING_MSI1_BASE_LSB(ab) … #define HAL_REO1_RING_MSI1_BASE_MSB(ab) … #define HAL_REO1_RING_MSI1_DATA(ab) … #define HAL_REO2_RING_BASE_LSB(ab) … #define HAL_REO1_AGING_THRESH_IX_0(ab) … #define HAL_REO1_AGING_THRESH_IX_1(ab) … #define HAL_REO1_AGING_THRESH_IX_2(ab) … #define HAL_REO1_AGING_THRESH_IX_3(ab) … #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) … #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) … #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) … #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) … #define HAL_REO1_RING_ID_OFFSET(ab) … #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) … #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) … #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) … #define HAL_REO1_RING_MISC_OFFSET(ab) … /* REO2SW(x) R2 ring pointers (head/tail) address */ #define HAL_REO1_RING_HP(ab) … #define HAL_REO1_RING_TP(ab) … #define HAL_REO2_RING_HP(ab) … #define HAL_REO1_RING_TP_OFFSET(ab) … /* REO2TCL R0 ring configuration address */ #define HAL_REO_TCL_RING_BASE_LSB(ab) … /* REO2TCL R2 ring pointer (head/tail) address */ #define HAL_REO_TCL_RING_HP(ab) … /* REO CMD R0 address */ #define HAL_REO_CMD_RING_BASE_LSB(ab) … /* REO CMD R2 address */ #define HAL_REO_CMD_HP(ab) … /* SW2REO R0 address */ #define HAL_SW2REO_RING_BASE_LSB(ab) … /* SW2REO R2 address */ #define HAL_SW2REO_RING_HP(ab) … /* CE ring R0 address */ #define HAL_CE_DST_RING_BASE_LSB … #define HAL_CE_DST_STATUS_RING_BASE_LSB … #define HAL_CE_DST_RING_CTRL … /* CE ring R2 address */ #define HAL_CE_DST_RING_HP … #define HAL_CE_DST_STATUS_RING_HP … /* REO status address */ #define HAL_REO_STATUS_RING_BASE_LSB(ab) … #define HAL_REO_STATUS_HP(ab) … /* WBM Idle R0 address */ #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) … #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) … #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR … #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR … #define HAL_WBM_SCATTERED_RING_BASE_LSB … #define HAL_WBM_SCATTERED_RING_BASE_MSB … #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 … #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 … #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 … #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 … #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR … /* WBM Idle R2 address */ #define HAL_WBM_IDLE_LINK_RING_HP … /* SW2WBM R0 release address */ #define HAL_WBM_RELEASE_RING_BASE_LSB(x) … /* SW2WBM R2 release address */ #define HAL_WBM_RELEASE_RING_HP … /* WBM2SW R0 release address */ #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) … #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) … /* WBM2SW R2 release address */ #define HAL_WBM0_RELEASE_RING_HP … #define HAL_WBM1_RELEASE_RING_HP … /* TCL ring field mask and offset */ #define HAL_TCL1_RING_BASE_MSB_RING_SIZE … #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB … #define HAL_TCL1_RING_ID_ENTRY_SIZE … #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE … #define HAL_TCL1_RING_MISC_MSI_SWAP … #define HAL_TCL1_RING_MISC_HOST_FW_SWAP … #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP … #define HAL_TCL1_RING_MISC_SRNG_ENABLE … #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD … #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD … #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD … #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE … #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR … #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 … #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 … /* REO ring field mask and offset */ #define HAL_REO1_RING_BASE_MSB_RING_SIZE … #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB … #define HAL_REO1_RING_ID_RING_ID … #define HAL_REO1_RING_ID_ENTRY_SIZE … #define HAL_REO1_RING_MISC_MSI_SWAP … #define HAL_REO1_RING_MISC_HOST_FW_SWAP … #define HAL_REO1_RING_MISC_DATA_TLV_SWAP … #define HAL_REO1_RING_MISC_SRNG_ENABLE … #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD … #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD … #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE … #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR … #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING … #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE … #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE … #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING … /* CE ring bit field mask and shift */ #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN … #define HAL_ADDR_LSB_REG_MASK … #define HAL_ADDR_MSB_REG_SHIFT … /* WBM ring bit field mask and shift */ #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE … #define HAL_WBM_SCATTER_BUFFER_SIZE … #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST … #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 … #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG … #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 … #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 … #define BASE_ADDR_MATCH_TAG_VAL … #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE … #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE … #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE … #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE … #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE … #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE … #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE … #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE … #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE … #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE … #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE … #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE … #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE … #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE … #define HAL_RXDMA_RING_MAX_SIZE … /* IPQ5018 ce registers */ #define HAL_IPQ5018_CE_WFSS_REG_BASE … #define HAL_IPQ5018_CE_SIZE … /* Add any other errors here and return them in * ath11k_hal_rx_desc_get_err(). */ enum hal_srng_ring_id { … }; /* SRNG registers are split into two groups R0 and R2 */ #define HAL_SRNG_REG_GRP_R0 … #define HAL_SRNG_REG_GRP_R2 … #define HAL_SRNG_NUM_REG_GRP … #define HAL_SRNG_NUM_LMACS … #define HAL_SRNG_REO_EXCEPTION … #define HAL_SRNG_RINGS_PER_LMAC … #define HAL_SRNG_NUM_LMAC_RINGS … #define HAL_SRNG_RING_ID_MAX … enum hal_ring_type { … }; #define HAL_RX_MAX_BA_WINDOW … #define HAL_DEFAULT_REO_TIMEOUT_USEC … /** * enum hal_reo_cmd_type: Enum for REO command type * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked * earlier with a 'REO_FLUSH_CACHE' command * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings */ enum hal_reo_cmd_type { … }; /** * enum hal_reo_cmd_status: Enum for execution status of REO command * @HAL_REO_CMD_SUCCESS: Command has successfully executed * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue * or cache was blocked * @HAL_REO_CMD_FAILED: Command execution failed, could be due to * invalid queue desc * @HAL_REO_CMD_RESOURCE_BLOCKED: * @HAL_REO_CMD_DRAIN: */ enum hal_reo_cmd_status { … }; struct hal_wbm_idle_scatter_list { … }; struct hal_srng_params { … }; enum hal_srng_dir { … }; /* srng flags */ #define HAL_SRNG_FLAGS_MSI_SWAP … #define HAL_SRNG_FLAGS_RING_PTR_SWAP … #define HAL_SRNG_FLAGS_DATA_TLV_SWAP … #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN … #define HAL_SRNG_FLAGS_MSI_INTR … #define HAL_SRNG_FLAGS_CACHED … #define HAL_SRNG_FLAGS_LMAC_RING … #define HAL_SRNG_FLAGS_REMAP_CE_RING … #define HAL_SRNG_TLV_HDR_TAG … #define HAL_SRNG_TLV_HDR_LEN … /* Common SRNG ring structure for source and destination rings */ struct hal_srng { … }; /* Interrupt mitigation - Batch threshold in terms of number of frames */ #define HAL_SRNG_INT_BATCH_THRESHOLD_TX … #define HAL_SRNG_INT_BATCH_THRESHOLD_RX … #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER … /* Interrupt mitigation - timer threshold in us */ #define HAL_SRNG_INT_TIMER_THRESHOLD_TX … #define HAL_SRNG_INT_TIMER_THRESHOLD_RX … #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER … /* HW SRNG configuration table */ struct hal_srng_config { … }; /** * enum hal_rx_buf_return_buf_manager - manager for returned rx buffers * * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle * descriptor list. * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host * @HAL_RX_BUF_RBM_SW4_BM: For Tx completion -- returned to host */ enum hal_rx_buf_return_buf_manager { … }; #define HAL_SRNG_DESC_LOOP_CNT … #define HAL_REO_CMD_FLG_NEED_STATUS … #define HAL_REO_CMD_FLG_STATS_CLEAR … #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER … #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING … #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL … #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS … #define HAL_REO_CMD_FLG_FLUSH_ALL … #define HAL_REO_CMD_FLG_UNBLK_RESOURCE … #define HAL_REO_CMD_FLG_UNBLK_CACHE … /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM … #define HAL_REO_CMD_UPD0_VLD … #define HAL_REO_CMD_UPD0_ALDC … #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION … #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN … #define HAL_REO_CMD_UPD0_AC … #define HAL_REO_CMD_UPD0_BAR … #define HAL_REO_CMD_UPD0_RETRY … #define HAL_REO_CMD_UPD0_CHECK_2K_MODE … #define HAL_REO_CMD_UPD0_OOR_MODE … #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE … #define HAL_REO_CMD_UPD0_PN_CHECK … #define HAL_REO_CMD_UPD0_EVEN_PN … #define HAL_REO_CMD_UPD0_UNEVEN_PN … #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE … #define HAL_REO_CMD_UPD0_PN_SIZE … #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG … #define HAL_REO_CMD_UPD0_SVLD … #define HAL_REO_CMD_UPD0_SSN … #define HAL_REO_CMD_UPD0_SEQ_2K_ERR … #define HAL_REO_CMD_UPD0_PN_ERR … #define HAL_REO_CMD_UPD0_PN_VALID … #define HAL_REO_CMD_UPD0_PN … /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ #define HAL_REO_CMD_UPD1_VLD … #define HAL_REO_CMD_UPD1_ALDC … #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION … #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN … #define HAL_REO_CMD_UPD1_AC … #define HAL_REO_CMD_UPD1_BAR … #define HAL_REO_CMD_UPD1_RETRY … #define HAL_REO_CMD_UPD1_CHECK_2K_MODE … #define HAL_REO_CMD_UPD1_OOR_MODE … #define HAL_REO_CMD_UPD1_PN_CHECK … #define HAL_REO_CMD_UPD1_EVEN_PN … #define HAL_REO_CMD_UPD1_UNEVEN_PN … #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE … #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG … /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ #define HAL_REO_CMD_UPD2_SVLD … #define HAL_REO_CMD_UPD2_SSN … #define HAL_REO_CMD_UPD2_SEQ_2K_ERR … #define HAL_REO_CMD_UPD2_PN_ERR … #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP … struct ath11k_hal_reo_cmd { … }; enum hal_pn_type { … }; enum hal_ce_desc { … }; #define HAL_HASH_ROUTING_RING_TCL … #define HAL_HASH_ROUTING_RING_SW1 … #define HAL_HASH_ROUTING_RING_SW2 … #define HAL_HASH_ROUTING_RING_SW3 … #define HAL_HASH_ROUTING_RING_SW4 … #define HAL_HASH_ROUTING_RING_REL … #define HAL_HASH_ROUTING_RING_FW … struct hal_reo_status_header { … }; struct hal_reo_status_queue_stats { … }; struct hal_reo_status_flush_queue { … }; enum hal_reo_status_flush_cache_err_code { … }; struct hal_reo_status_flush_cache { … }; enum hal_reo_status_unblock_cache_type { … }; struct hal_reo_status_unblock_cache { … }; struct hal_reo_status_flush_timeout_list { … }; enum hal_reo_threshold_idx { … }; struct hal_reo_status_desc_thresh_reached { … }; struct hal_reo_status { … }; /* HAL context to be used to access SRNG APIs (currently used by data path * and transport (CE) modules) */ struct ath11k_hal { … }; u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, u32 start_seq, enum hal_pn_type type); void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, struct hal_srng *srng); void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, struct hal_wbm_idle_scatter_list *sbuf, u32 nsbufs, u32 tot_link_desc, u32 end_offset); dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, struct hal_srng *srng); dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, struct hal_srng *srng); void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, dma_addr_t paddr); u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, u8 byte_swap_data); void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); u32 ath11k_hal_ce_dst_status_get_length(void *buf); int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type); int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type); void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, struct hal_srng_params *params); u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, struct hal_srng *srng); u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, bool sync_hw_ptr); u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); u32 *ath11k_hal_srng_src_next_peek(struct ath11k_base *ab, struct hal_srng *srng); u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, struct hal_srng *srng); u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, struct hal_srng *srng); u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, struct hal_srng *srng); int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, bool sync_hw_ptr); void ath11k_hal_srng_access_begin(struct ath11k_base *ab, struct hal_srng *srng); void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, int ring_num, int mac_id, struct hal_srng_params *params); int ath11k_hal_srng_init(struct ath11k_base *ath11k); void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, u32 **cfg, u32 *len); int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, enum hal_ring_type ring_type, int ring_num); void ath11k_hal_srng_shadow_config(struct ath11k_base *ab); void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab, struct hal_srng *srng); #endif
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