/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_HAL_RX_H #define ATH11K_HAL_RX_H struct hal_rx_wbm_rel_info { … }; #define HAL_INVALID_PEERID … #define VHT_SIG_SU_NSS_MASK … #define HAL_RX_MAX_MCS … #define HAL_RX_MAX_NSS … struct hal_rx_mon_status_tlv_hdr { … }; enum hal_rx_su_mu_coding { … }; enum hal_rx_gi { … }; enum hal_rx_bw { … }; enum hal_rx_preamble { … }; enum hal_rx_reception_type { … }; #define HAL_RX_FCS_LEN … enum hal_rx_mon_status { … }; struct hal_rx_user_status { … }; #define HAL_TLV_STATUS_PPDU_NOT_DONE … #define HAL_TLV_STATUS_PPDU_DONE … #define HAL_TLV_STATUS_BUF_DONE … struct hal_sw_mon_ring_entries { … }; struct hal_rx_mon_ppdu_info { … }; #define HAL_RX_PPDU_START_INFO0_PPDU_ID … struct hal_rx_ppdu_start { … } __packed; #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR … #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK … #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID … #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID … #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID … #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE … #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX … #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL … #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL … #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_BITMAP … #define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_EOSP_BITMAP … #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_OK_BYTE_COUNT … #define HAL_RX_PPDU_END_USER_STATS_INFO9_MPDU_ERR_BYTE_COUNT … struct hal_rx_ppdu_end_user_stats { … } __packed; struct hal_rx_ppdu_end_user_stats_ext { … } __packed; #define HAL_RX_HT_SIG_INFO_INFO0_MCS … #define HAL_RX_HT_SIG_INFO_INFO0_BW … #define HAL_RX_HT_SIG_INFO_INFO1_STBC … #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING … #define HAL_RX_HT_SIG_INFO_INFO1_GI … struct hal_rx_ht_sig_info { … } __packed; #define HAL_RX_LSIG_B_INFO_INFO0_RATE … #define HAL_RX_LSIG_B_INFO_INFO0_LEN … struct hal_rx_lsig_b_info { … } __packed; #define HAL_RX_LSIG_A_INFO_INFO0_RATE … #define HAL_RX_LSIG_A_INFO_INFO0_LEN … #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE … struct hal_rx_lsig_a_info { … } __packed; #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW … #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC … #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID … #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS … #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING … #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING … #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS … #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED … struct hal_rx_vht_sig_a_info { … } __packed; enum hal_rx_vht_sig_a_gi_setting { … }; #define HAL_RX_SU_MU_CODING_LDPC … #define HE_GI_0_8 … #define HE_GI_0_4 … #define HE_GI_1_6 … #define HE_GI_3_2 … #define HE_LTF_1_X … #define HE_LTF_2_X … #define HE_LTF_4_X … #define HE_LTF_UNKNOWN … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND … struct hal_rx_he_sig_a_su_info { … } __packed; #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_CODING … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXBF … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR … #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM … struct hal_rx_he_sig_a_mu_dl_info { … } __packed; #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION … struct hal_rx_he_sig_b1_mu_info { … } __packed; #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID … #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS … #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING … #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS … struct hal_rx_he_sig_b2_mu_info { … } __packed; #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING … struct hal_rx_he_sig_b2_ofdma_info { … } __packed; #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB … #define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 … struct hal_rx_phyrx_chain_rssi { … } __packed; struct hal_rx_phyrx_rssi_legacy_info { … } __packed; #define HAL_RX_MPDU_INFO_INFO0_PEERID … #define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 … #define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN … struct hal_rx_mpdu_info_ipq8074 { … } __packed; struct hal_rx_mpdu_info_qcn9074 { … } __packed; struct hal_rx_mpdu_info_wcn6855 { … } __packed; struct hal_rx_mpdu_info { … } __packed; #define HAL_RX_PPDU_END_DURATION … struct hal_rx_ppdu_end_duration { … } __packed; struct hal_rx_rxpcu_classification_overview { … } __packed; struct hal_rx_msdu_desc_info { … }; #define HAL_RX_NUM_MSDU_DESC … struct hal_rx_msdu_list { … }; void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab, u32 *reo_desc, struct hal_reo_status *status); int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status); void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus, u32 *msdu_cookies, enum hal_rx_buf_return_buf_manager *rbm); void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc, void *link_desc, enum hal_wbm_rel_bm_act action); void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr, u32 cookie, u8 manager); void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr, u32 *cookie, u8 *rbm); int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc, dma_addr_t *paddr, u32 *desc_bank); int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc, struct hal_rx_wbm_rel_info *rel_info); void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc, dma_addr_t *paddr, u32 *desc_bank); void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, u32 *sw_cookie, void **pp_buf_addr_info, u8 *rbm, u32 *msdu_cnt); void ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc, struct hal_sw_mon_ring_entries *sw_mon_ent); enum hal_rx_mon_status ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab, struct hal_rx_mon_ppdu_info *ppdu_info, struct sk_buff *skb); #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 … #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 … #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 … #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 … #endif
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