linux/drivers/net/wireless/ath/wcn36xx/dxe.c

/*
 * Copyright (c) 2013 Eugene Krasnikov <[email protected]>
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/* DXE - DMA transfer engine
 * we have 2 channels(High prio and Low prio) for TX and 2 channels for RX.
 * through low channels data packets are transfered
 * through high channels managment packets are transfered
 */

#define pr_fmt(fmt) …

#include <linux/interrupt.h>
#include <linux/soc/qcom/smem_state.h>
#include "wcn36xx.h"
#include "txrx.h"

static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data)
{ … }

static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)
{ … }

static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
{ … }

static void wcn36xx_dxe_free_ctl_block(struct wcn36xx_dxe_ch *ch)
{ … }

static int wcn36xx_dxe_allocate_ctl_block(struct wcn36xx_dxe_ch *ch)
{ … }

int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn)
{ … }

void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn)
{ … }

static int wcn36xx_dxe_init_descs(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *wcn_ch)
{ … }

static void wcn36xx_dxe_deinit_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch)
{ … }

static void wcn36xx_dxe_init_tx_bd(struct wcn36xx_dxe_ch *ch,
				   struct wcn36xx_dxe_mem_pool *pool)
{ … }

static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
{ … }

static void wcn36xx_dxe_disable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
{ … }

static int wcn36xx_dxe_fill_skb(struct device *dev,
				struct wcn36xx_dxe_ctl *ctl,
				gfp_t gfp)
{ … }

static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn,
				    struct wcn36xx_dxe_ch *wcn_ch)
{ … }

static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,
				     struct wcn36xx_dxe_ch *wcn_ch)
{ … }

void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status)
{ … }

static void wcn36xx_dxe_tx_timer(struct timer_list *t)
{ … }

static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
{ … }

static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
{ … }

static irqreturn_t wcn36xx_irq_rx_ready(int irq, void *dev)
{ … }

static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)
{ … }

static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
				     struct wcn36xx_dxe_ch *ch,
				     u32 ctrl,
				     u32 en_mask,
				     u32 int_mask,
				     u32 status_reg)
{ … }

void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn)
{ … }

int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn)
{ … }

void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn)
{ … }

int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
			 struct wcn36xx_vif *vif_priv,
			 struct wcn36xx_tx_bd *bd,
			 struct sk_buff *skb,
			 bool is_low)
{ … }

static bool _wcn36xx_dxe_tx_channel_is_empty(struct wcn36xx_dxe_ch *ch)
{ … }

int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn)
{ … }

int wcn36xx_dxe_init(struct wcn36xx *wcn)
{ … }

void wcn36xx_dxe_deinit(struct wcn36xx *wcn)
{ … }