/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_HAL_RX_H #define ATH12K_HAL_RX_H struct hal_rx_wbm_rel_info { … }; #define HAL_INVALID_PEERID … #define VHT_SIG_SU_NSS_MASK … #define HAL_RX_MAX_MCS … #define HAL_RX_MAX_NSS … #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) … #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) … #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) … #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) … struct hal_rx_mon_status_tlv_hdr { … }; enum hal_rx_su_mu_coding { … }; enum hal_rx_gi { … }; enum hal_rx_bw { … }; enum hal_rx_preamble { … }; enum hal_rx_reception_type { … }; enum hal_rx_legacy_rate { … }; #define HAL_TLV_STATUS_PPDU_NOT_DONE … #define HAL_TLV_STATUS_PPDU_DONE … #define HAL_TLV_STATUS_BUF_DONE … #define HAL_TLV_STATUS_PPDU_NON_STD_DONE … #define HAL_RX_FCS_LEN … enum hal_rx_mon_status { … }; #define HAL_RX_MAX_MPDU … #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP … struct hal_rx_user_status { … }; #define HAL_MAX_UL_MU_USERS … struct hal_rx_mon_ppdu_info { … }; #define HAL_RX_PPDU_START_INFO0_PPDU_ID … struct hal_rx_ppdu_start { … } __packed; #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR … #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK … #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID … #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID … #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID … #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE … #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX … #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL … #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL … #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT … #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP … #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP … #define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT … #define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT … struct hal_rx_ppdu_end_user_stats { … } __packed; struct hal_rx_ppdu_end_user_stats_ext { … } __packed; #define HAL_RX_HT_SIG_INFO_INFO0_MCS … #define HAL_RX_HT_SIG_INFO_INFO0_BW … #define HAL_RX_HT_SIG_INFO_INFO1_STBC … #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING … #define HAL_RX_HT_SIG_INFO_INFO1_GI … struct hal_rx_ht_sig_info { … } __packed; #define HAL_RX_LSIG_B_INFO_INFO0_RATE … #define HAL_RX_LSIG_B_INFO_INFO0_LEN … struct hal_rx_lsig_b_info { … } __packed; #define HAL_RX_LSIG_A_INFO_INFO0_RATE … #define HAL_RX_LSIG_A_INFO_INFO0_LEN … #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE … struct hal_rx_lsig_a_info { … } __packed; #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW … #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC … #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID … #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS … #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING … #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING … #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS … #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED … struct hal_rx_vht_sig_a_info { … } __packed; enum hal_rx_vht_sig_a_gi_setting { … }; #define HE_GI_0_8 … #define HE_GI_0_4 … #define HE_GI_1_6 … #define HE_GI_3_2 … #define HE_LTF_1_X … #define HE_LTF_2_X … #define HE_LTF_4_X … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE … #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM … #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND … struct hal_rx_he_sig_a_su_info { … } __packed; #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE … #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR … #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM … struct hal_rx_he_sig_a_mu_dl_info { … } __packed; #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION … struct hal_rx_he_sig_b1_mu_info { … } __packed; #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID … #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS … #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING … #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS … struct hal_rx_he_sig_b2_mu_info { … } __packed; #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM … #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING … struct hal_rx_he_sig_b2_ofdma_info { … } __packed; enum hal_rx_ul_reception_type { … }; #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB … #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION … struct hal_rx_phyrx_rssi_legacy_info { … } __packed; #define HAL_RX_MPDU_START_INFO0_PPDU_ID … #define HAL_RX_MPDU_START_INFO1_PEERID … #define HAL_RX_MPDU_START_INFO2_MPDU_LEN … struct hal_rx_mpdu_start { … } __packed; #define HAL_RX_PPDU_END_DURATION … struct hal_rx_ppdu_end_duration { … } __packed; struct hal_rx_rxpcu_classification_overview { … } __packed; struct hal_rx_msdu_desc_info { … }; #define HAL_RX_NUM_MSDU_DESC … struct hal_rx_msdu_list { … }; #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 … #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 … #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 … #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 … struct hal_rx_frame_bitmap_ack { … } __packed; #define HAL_RX_RESP_REQ_INFO0_PPDU_ID … #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE … #define HAL_RX_RESP_REQ_INFO1_DURATION … #define HAL_RX_RESP_REQ_INFO1_RATE_MCS … #define HAL_RX_RESP_REQ_INFO1_SGI … #define HAL_RX_RESP_REQ_INFO1_STBC … #define HAL_RX_RESP_REQ_INFO1_LDPC … #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU … #define HAL_RX_RESP_REQ_INFO2_NUM_USER … #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 … #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 … #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 … #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 … struct hal_rx_resp_req_info { … } __packed; #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 … #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 … #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 … #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START … #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE … /* HE Radiotap data1 Mask */ #define HE_SU_FORMAT_TYPE … #define HE_EXT_SU_FORMAT_TYPE … #define HE_MU_FORMAT_TYPE … #define HE_TRIG_FORMAT_TYPE … #define HE_BEAM_CHANGE_KNOWN … #define HE_DL_UL_KNOWN … #define HE_MCS_KNOWN … #define HE_DCM_KNOWN … #define HE_CODING_KNOWN … #define HE_LDPC_EXTRA_SYMBOL_KNOWN … #define HE_STBC_KNOWN … #define HE_DATA_BW_RU_KNOWN … #define HE_DOPPLER_KNOWN … #define HE_BSS_COLOR_KNOWN … /* HE Radiotap data2 Mask */ #define HE_GI_KNOWN … #define HE_TXBF_KNOWN … #define HE_PE_DISAMBIGUITY_KNOWN … #define HE_TXOP_KNOWN … #define HE_LTF_SYMBOLS_KNOWN … #define HE_PRE_FEC_PADDING_KNOWN … #define HE_MIDABLE_PERIODICITY_KNOWN … /* HE radiotap data3 shift values */ #define HE_BEAM_CHANGE_SHIFT … #define HE_DL_UL_SHIFT … #define HE_TRANSMIT_MCS_SHIFT … #define HE_DCM_SHIFT … #define HE_CODING_SHIFT … #define HE_LDPC_EXTRA_SYMBOL_SHIFT … #define HE_STBC_SHIFT … /* HE radiotap data4 shift values */ #define HE_STA_ID_SHIFT … /* HE radiotap data5 */ #define HE_GI_SHIFT … #define HE_LTF_SIZE_SHIFT … #define HE_LTF_SYM_SHIFT … #define HE_TXBF_SHIFT … #define HE_PE_DISAMBIGUITY_SHIFT … #define HE_PRE_FEC_PAD_SHIFT … /* HE radiotap data6 */ #define HE_DOPPLER_SHIFT … #define HE_TXOP_SHIFT … /* HE radiotap HE-MU flags1 */ #define HE_SIG_B_MCS_KNOWN … #define HE_SIG_B_DCM_KNOWN … #define HE_SIG_B_SYM_NUM_KNOWN … #define HE_RU_0_KNOWN … #define HE_RU_1_KNOWN … #define HE_RU_2_KNOWN … #define HE_RU_3_KNOWN … #define HE_DCM_FLAG_1_SHIFT … #define HE_SPATIAL_REUSE_MU_KNOWN … #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN … /* HE radiotap HE-MU flags2 */ #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT … #define HE_BW_KNOWN … #define HE_NUM_SIG_B_SYMBOLS_SHIFT … #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN … #define HE_NUM_SIG_B_FLAG_2_SHIFT … #define HE_LTF_FLAG_2_SYMBOLS_SHIFT … #define HE_LTF_KNOWN … /* HE radiotap per_user_1 */ #define HE_STA_SPATIAL_SHIFT … #define HE_TXBF_SHIFT … #define HE_RESERVED_SET_TO_1_SHIFT … #define HE_STA_CODING_SHIFT … /* HE radiotap per_user_2 */ #define HE_STA_MCS_SHIFT … #define HE_STA_DCM_SHIFT … /* HE radiotap per user known */ #define HE_USER_FIELD_POSITION_KNOWN … #define HE_STA_ID_PER_USER_KNOWN … #define HE_STA_NSTS_KNOWN … #define HE_STA_TX_BF_KNOWN … #define HE_STA_SPATIAL_CONFIG_KNOWN … #define HE_STA_MCS_KNOWN … #define HE_STA_DCM_KNOWN … #define HE_STA_CODING_KNOWN … #define HAL_RX_MPDU_ERR_FCS … #define HAL_RX_MPDU_ERR_DECRYPT … #define HAL_RX_MPDU_ERR_TKIP_MIC … #define HAL_RX_MPDU_ERR_AMSDU_ERR … #define HAL_RX_MPDU_ERR_OVERFLOW … #define HAL_RX_MPDU_ERR_MSDU_LEN … #define HAL_RX_MPDU_ERR_MPDU_LEN … #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME … static inline enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) { … } void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, struct hal_reo_status *status); void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus, u32 *msdu_cookies, enum hal_rx_buf_return_buf_manager *rbm); void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, struct hal_wbm_release_ring *dst_desc, struct hal_wbm_release_ring *src_desc, enum hal_wbm_rel_bm_act action); void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, dma_addr_t paddr, u32 cookie, u8 manager); void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, dma_addr_t *paddr, u32 *cookie, u8 *rbm); int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab, struct hal_reo_dest_ring *desc, dma_addr_t *paddr, u32 *desc_bank); int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc, struct hal_rx_wbm_rel_info *rel_info); void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab, struct ath12k_buffer_addr *buff_addr, dma_addr_t *paddr, u32 *cookie); #endif
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