/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_HAL_TX_H #define ATH12K_HAL_TX_H #include "hal_desc.h" #include "core.h" #define HAL_TX_ADDRX_EN … #define HAL_TX_ADDRY_EN … #define HAL_TX_ADDR_SEARCH_DEFAULT … #define HAL_TX_ADDR_SEARCH_INDEX … /* TODO: check all these data can be managed with struct ath12k_tx_desc_info for perf */ struct hal_tx_info { … }; /* TODO: Check if the actual desc macros can be used instead */ #define HAL_TX_STATUS_FLAGS_FIRST_MSDU … #define HAL_TX_STATUS_FLAGS_LAST_MSDU … #define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU … #define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID … #define HAL_TX_STATUS_FLAGS_RATE_LDPC … #define HAL_TX_STATUS_FLAGS_RATE_STBC … #define HAL_TX_STATUS_FLAGS_OFDMA … #define HAL_TX_STATUS_DESC_LEN … /* Tx status parsed from srng desc */ struct hal_tx_status { … }; #define HAL_TX_PHY_DESC_INFO0_BF_TYPE … #define HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B … #define HAL_TX_PHY_DESC_INFO0_PKT_TYPE … #define HAL_TX_PHY_DESC_INFO0_BANDWIDTH … #define HAL_TX_PHY_DESC_INFO1_MCS … #define HAL_TX_PHY_DESC_INFO1_STBC … #define HAL_TX_PHY_DESC_INFO2_NSS … #define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW … #define HAL_TX_PHY_DESC_INFO3_LTF_SIZE … #define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL … struct hal_tx_phy_desc { … } __packed; #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0 … #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16 … #define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0 … #define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16 … struct hal_tx_fes_status_prot { … } __packed; #define HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION … struct hal_tx_fes_status_user_ppdu { … } __packed; #define HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32 … #define HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32 … struct hal_tx_fes_status_start_prot { … } __packed; #define HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE … struct hal_tx_fes_status_start { … } __packed; #define HAL_TX_Q_EXT_INFO0_FRAME_CTRL … #define HAL_TX_Q_EXT_INFO0_QOS_CTRL … #define HAL_TX_Q_EXT_INFO1_AMPDU_FLAG … struct hal_tx_queue_exten { … } __packed; #define HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS … struct hal_tx_fes_setup { … } __packed; #define HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE … #define HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0 … #define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32 … #define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0 … #define HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16 … #define HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0 … #define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32 … #define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0 … #define HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16 … struct hal_tx_pcu_ppdu_setup_init { … } __packed; #define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0 … #define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16 … struct hal_tx_fes_status_end { … } __packed; #define HAL_TX_BANK_CONFIG_EPD … #define HAL_TX_BANK_CONFIG_ENCAP_TYPE … #define HAL_TX_BANK_CONFIG_ENCRYPT_TYPE … #define HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP … #define HAL_TX_BANK_CONFIG_LINK_META_SWAP … #define HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN … #define HAL_TX_BANK_CONFIG_ADDRX_EN … #define HAL_TX_BANK_CONFIG_ADDRY_EN … #define HAL_TX_BANK_CONFIG_MESH_EN … #define HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN … #define HAL_TX_BANK_CONFIG_PMAC_ID … /* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */ #define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID … void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab, struct hal_tcl_data_cmd *tcl_cmd, struct hal_tx_info *ti); void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id); int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, enum hal_reo_cmd_type type, struct ath12k_hal_reo_cmd *cmd); void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config, u8 bank_id); #endif
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