/* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "core.h" #ifndef ATH12K_HAL_DESC_H #define ATH12K_HAL_DESC_H #define BUFFER_ADDR_INFO0_ADDR … #define BUFFER_ADDR_INFO1_ADDR … #define BUFFER_ADDR_INFO1_RET_BUF_MGR … #define BUFFER_ADDR_INFO1_SW_COOKIE … struct ath12k_buffer_addr { … } __packed; /* ath12k_buffer_addr * * buffer_addr_31_0 * Address (lower 32 bits) of the MSDU buffer or MSDU_EXTENSION * descriptor or Link descriptor * * buffer_addr_39_32 * Address (upper 8 bits) of the MSDU buffer or MSDU_EXTENSION * descriptor or Link descriptor * * return_buffer_manager (RBM) * Consumer: WBM * Producer: SW/FW * Indicates to which buffer manager the buffer or MSDU_EXTENSION * descriptor or link descriptor that is being pointed to shall be * returned after the frame has been processed. It is used by WBM * for routing purposes. * * Values are defined in enum %HAL_RX_BUF_RBM_ * * sw_buffer_cookie * Cookie field exclusively used by SW. HW ignores the contents, * accept that it passes the programmed value on to other * descriptors together with the physical address. * * Field can be used by SW to for example associate the buffers * physical address with the virtual address. * * NOTE1: * The three most significant bits can have a special meaning * in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, * and field transmit_bw_restriction is set * * In case of NON punctured transmission: * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only * Sw_buffer_cookie[19:18] = 2'b11: reserved * * In case of punctured transmission: * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only * Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only * Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only * Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only * Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only * Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only * Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only * Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only * Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only * Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only * Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only * Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only * Sw_buffer_cookie[19:18] = 2'b11: reserved * * Note: a punctured transmission is indicated by the presence * of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV * * Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS control * field * * Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field * indicates MPDUs with a QoS control field. * */ enum hal_tlv_tag { … }; #define HAL_TLV_HDR_TAG … #define HAL_TLV_HDR_LEN … #define HAL_TLV_USR_ID … #define HAL_TLV_ALIGN … struct hal_tlv_hdr { … } __packed; #define HAL_TLV_64_HDR_TAG … #define HAL_TLV_64_HDR_LEN … struct hal_tlv_64_hdr { … } __packed; #define RX_MPDU_DESC_INFO0_MSDU_COUNT … #define RX_MPDU_DESC_INFO0_FRAG_FLAG … #define RX_MPDU_DESC_INFO0_MPDU_RETRY … #define RX_MPDU_DESC_INFO0_AMPDU_FLAG … #define RX_MPDU_DESC_INFO0_BAR_FRAME … #define RX_MPDU_DESC_INFO0_VALID_PN … #define RX_MPDU_DESC_INFO0_RAW_MPDU … #define RX_MPDU_DESC_INFO0_MORE_FRAG_FLAG … #define RX_MPDU_DESC_INFO0_SRC_INFO … #define RX_MPDU_DESC_INFO0_MPDU_QOS_CTRL_VALID … #define RX_MPDU_DESC_INFO0_TID … /* Peer Metadata classification */ /* Version 0 */ #define RX_MPDU_DESC_META_DATA_V0_PEER_ID … #define RX_MPDU_DESC_META_DATA_V0_VDEV_ID … /* Version 1 */ #define RX_MPDU_DESC_META_DATA_V1_PEER_ID … #define RX_MPDU_DESC_META_DATA_V1_LOGICAL_LINK_ID … #define RX_MPDU_DESC_META_DATA_V1_VDEV_ID … #define RX_MPDU_DESC_META_DATA_V1_LMAC_ID … #define RX_MPDU_DESC_META_DATA_V1_DEVICE_ID … /* Version 1A */ #define RX_MPDU_DESC_META_DATA_V1A_PEER_ID … #define RX_MPDU_DESC_META_DATA_V1A_VDEV_ID … #define RX_MPDU_DESC_META_DATA_V1A_LOGICAL_LINK_ID … #define RX_MPDU_DESC_META_DATA_V1A_DEVICE_ID … /* Version 1B */ #define RX_MPDU_DESC_META_DATA_V1B_PEER_ID … #define RX_MPDU_DESC_META_DATA_V1B_VDEV_ID … #define RX_MPDU_DESC_META_DATA_V1B_HW_LINK_ID … #define RX_MPDU_DESC_META_DATA_V1B_DEVICE_ID … struct rx_mpdu_desc { … } __packed; /* rx_mpdu_desc * Producer: RXDMA * Consumer: REO/SW/FW * * msdu_count * The number of MSDUs within the MPDU * * fragment_flag * When set, this MPDU is a fragment and REO should forward this * fragment MPDU to the REO destination ring without any reorder * checks, pn checks or bitmap update. This implies that REO is * forwarding the pointer to the MSDU link descriptor. * * mpdu_retry_bit * The retry bit setting from the MPDU header of the received frame * * ampdu_flag * Indicates the MPDU was received as part of an A-MPDU. * * bar_frame * Indicates the received frame is a BAR frame. After processing, * this frame shall be pushed to SW or deleted. * * valid_pn * When not set, REO will not perform a PN sequence number check. * * raw_mpdu * Field only valid when first_msdu_in_mpdu_flag is set. Indicates * the contents in the MSDU buffer contains a 'RAW' MPDU. This * 'RAW' MPDU might be spread out over multiple MSDU buffers. * * more_fragment_flag * The More Fragment bit setting from the MPDU header of the * received frame * * src_info * Source (Virtual) device/interface info associated with this peer. * This field gets passed on by REO to PPE in the EDMA descriptor. * * mpdu_qos_control_valid * When set, the MPDU has a QoS control field * * tid * Field only valid when mpdu_qos_control_valid is set */ enum hal_rx_msdu_desc_reo_dest_ind { … }; #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU … #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU … #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION … #define RX_MSDU_DESC_INFO0_MSDU_LENGTH … #define RX_MSDU_DESC_INFO0_MSDU_DROP … #define RX_MSDU_DESC_INFO0_VALID_SA … #define RX_MSDU_DESC_INFO0_VALID_DA … #define RX_MSDU_DESC_INFO0_DA_MCBC … #define RX_MSDU_DESC_INFO0_L3_HDR_PAD_MSB … #define RX_MSDU_DESC_INFO0_TCP_UDP_CHKSUM_FAIL … #define RX_MSDU_DESC_INFO0_IP_CHKSUM_FAIL … #define RX_MSDU_DESC_INFO0_FROM_DS … #define RX_MSDU_DESC_INFO0_TO_DS … #define RX_MSDU_DESC_INFO0_INTRA_BSS … #define RX_MSDU_DESC_INFO0_DST_CHIP_ID … #define RX_MSDU_DESC_INFO0_DECAP_FORMAT … #define HAL_RX_MSDU_PKT_LENGTH_GET(val) … struct rx_msdu_desc { … } __packed; /* rx_msdu_desc * * first_msdu_in_mpdu * Indicates first msdu in mpdu. * * last_msdu_in_mpdu * Indicates last msdu in mpdu. This flag can be true only when * 'Msdu_continuation' set to 0. This implies that when an msdu * is spread out over multiple buffers and thus msdu_continuation * is set, only for the very last buffer of the msdu, can the * 'last_msdu_in_mpdu' be set. * * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, * the MPDU that this MSDU belongs to only contains a single MSDU. * * msdu_continuation * When set, this MSDU buffer was not able to hold the entire MSDU. * The next buffer will therefore contain additional information * related to this MSDU. * * msdu_length * Field is only valid in combination with the 'first_msdu_in_mpdu' * being set. Full MSDU length in bytes after decapsulation. This * field is still valid for MPDU frames without A-MSDU. It still * represents MSDU length after decapsulation Or in case of RAW * MPDUs, it indicates the length of the entire MPDU (without FCS * field). * * msdu_drop * Indicates that REO shall drop this MSDU and not forward it to * any other ring. * * valid_sa * Indicates OLE found a valid SA entry for this MSDU. * * valid_da * When set, OLE found a valid DA entry for this MSDU. * * da_mcbc * Field Only valid if valid_da is set. Indicates the DA address * is a Multicast or Broadcast address for this MSDU. * * l3_header_padding_msb * Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as * the LSB is always zero). Number of bytes padded to make sure * that the L3 header will always start of a Dword boundary * * tcp_udp_checksum_fail * Passed on from 'RX_ATTENTION' TLV * Indicates that the computed checksum did not match the checksum * in the TCP/UDP header. * * ip_checksum_fail * Passed on from 'RX_ATTENTION' TLV * Indicates that the computed checksum did not match the checksum * in the IP header. * * from_DS * Set if the 'from DS' bit is set in the frame control. * * to_DS * Set if the 'to DS' bit is set in the frame control. * * intra_bss * This packet needs intra-BSS routing by SW as the 'vdev_id' * for the destination is the same as the 'vdev_id' that this * MSDU was got in. * * dest_chip_id * If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' * to support intra-BSS routing with multi-chip multi-link operation. * This indicates into which chip's TCL the packet should be queued. * * decap_format * Indicates the format after decapsulation: */ #define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND … #define RX_MSDU_EXT_DESC_INFO0_SERVICE_CODE … #define RX_MSDU_EXT_DESC_INFO0_PRIORITY_VALID … #define RX_MSDU_EXT_DESC_INFO0_DATA_OFFSET … #define RX_MSDU_EXT_DESC_INFO0_SRC_LINK_ID … struct rx_msdu_ext_desc { … } __packed; /* rx_msdu_ext_desc * * reo_destination_indication * The ID of the REO exit ring where the MSDU frame shall push * after (MPDU level) reordering has finished. * * service_code * Opaque service code between PPE and Wi-Fi * * priority_valid * * data_offset * The offset to Rx packet data within the buffer (including * Rx DMA offset programming and L3 header padding inserted * by Rx OLE). * * src_link_id * Set to the link ID of the PMAC that received the frame */ enum hal_reo_dest_ring_buffer_type { … }; enum hal_reo_dest_ring_push_reason { … }; enum hal_reo_dest_ring_error_code { … }; #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE … #define HAL_REO_DEST_RING_INFO0_PUSH_REASON … #define HAL_REO_DEST_RING_INFO0_ERROR_CODE … #define HAL_REO_DEST_RING_INFO0_MSDU_DATA_SIZE … #define HAL_REO_DEST_RING_INFO0_SW_EXCEPTION … #define HAL_REO_DEST_RING_INFO0_SRC_LINK_ID … #define HAL_REO_DEST_RING_INFO0_SIGNATURE … #define HAL_REO_DEST_RING_INFO0_RING_ID … #define HAL_REO_DEST_RING_INFO0_LOOPING_COUNT … struct hal_reo_dest_ring { … } __packed; /* hal_reo_dest_ring * * Producer: RXDMA * Consumer: REO/SW/FW * * buf_addr_info * Details of the physical address of a buffer or MSDU * link descriptor. * * rx_mpdu_info * General information related to the MPDU that is passed * on from REO entrance ring to the REO destination ring. * * rx_msdu_info * General information related to the MSDU that is passed * on from RXDMA all the way to the REO destination ring. * * buf_va_lo * Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address * Lower 32 bits of the 64-bit virtual address corresponding * to Buf_or_link_desc_addr_info * * buf_va_hi * Address (upper 32 bits) of the REO queue descriptor. * Upper 32 bits of the 64-bit virtual address corresponding * to Buf_or_link_desc_addr_info * * buffer_type * Indicates the type of address provided in the buf_addr_info. * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. * * push_reason * Reason for pushing this frame to this exit ring. Values are * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. * * error_code * Valid only when 'push_reason' is set. All error codes are * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. * * captured_msdu_data_size * The number of following REO_DESTINATION STRUCTs that have * been replaced with msdu_data extracted from the msdu_buffer * and copied into the ring for easy FW/SW access. * * sw_exception * This field has the same setting as the SW_exception field * in the corresponding REO_entrance_ring descriptor. * When set, the REO entrance descriptor is generated by FW, * and the MPDU was processed in the following way: * - NO re-order function is needed. * - MPDU delinking is determined by the setting of Entrance * ring field: SW_excection_mpdu_delink * - Destination ring selection is based on the setting of * the Entrance ring field SW_exception_destination _ring_valid * * src_link_id * Set to the link ID of the PMAC that received the frame * * signature * Set to value 0x8 when msdu capture mode is enabled for this ring * * ring_id * The buffer pointer ring id. * 0 - Idle ring * 1 - N refers to other rings. * * looping_count * Indicates the number of times the producer of entries into * this ring has looped around the ring. */ #define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH … #define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET … #define HAL_REO_TO_PPE_RING_INFO0_POOL_ID … #define HAL_REO_TO_PPE_RING_INFO0_PREHEADER … #define HAL_REO_TO_PPE_RING_INFO0_TSO_EN … #define HAL_REO_TO_PPE_RING_INFO0_MORE … struct hal_reo_to_ppe_ring { … } __packed; /* hal_reo_to_ppe_ring * * Producer: REO * Consumer: PPE * * buf_addr_info * Details of the physical address of a buffer or MSDU * link descriptor. * * data_length * Length of valid data in bytes * * data_offset * Offset to the data from buffer pointer. Can be used to * strip header in the data for tunnel termination etc. * * pool_id * REO has global configuration register for this field. * It may have several free buffer pools, each * RX-Descriptor ring can fetch free buffer from specific * buffer pool; pool id will indicate which pool the buffer * will be released to; POOL_ID Zero returned to SW * * preheader * Disabled: 0 (Default) * Enabled: 1 * * tso_en * Disabled: 0 (Default) * Enabled: 1 * * more * More Segments followed */ enum hal_reo_entr_rxdma_push_reason { … }; enum hal_reo_entr_rxdma_ecode { … }; enum hal_rx_reo_dest_ring { … }; #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI … #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT … #define HAL_REO_ENTR_RING_INFO0_DEST_IND … #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR … #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON … #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE … #define HAL_REO_ENTR_RING_INFO1_MPDU_FRAG_NUM … #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION … #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPT_MPDU_DELINK … #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING_VLD … #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING … #define HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM … #define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID … #define HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID … #define HAL_REO_ENTR_RING_INFO2_RING_ID … #define HAL_REO_ENTR_RING_INFO2_LOOPING_COUNT … struct hal_reo_entrance_ring { … } __packed; /* hal_reo_entrance_ring * * Producer: RXDMA * Consumer: REO * * buf_addr_info * Details of the physical address of a buffer or MSDU * link descriptor. * * rx_mpdu_info * General information related to the MPDU that is passed * on from REO entrance ring to the REO destination ring. * * queue_addr_lo * Address (lower 32 bits) of the REO queue descriptor. * * queue_addr_hi * Address (upper 8 bits) of the REO queue descriptor. * * mpdu_byte_count * An approximation of the number of bytes received in this MPDU. * Used to keeps stats on the amount of data flowing * through a queue. * * reo_destination_indication * The id of the reo exit ring where the msdu frame shall push * after (MPDU level) reordering has finished. Values are defined * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. * * frameless_bar * Indicates that this REO entrance ring struct contains BAR info * from a multi TID BAR frame. The original multi TID BAR frame * itself contained all the REO info for the first TID, but all * the subsequent TID info and their linkage to the REO descriptors * is passed down as 'frameless' BAR info. * * The only fields valid in this descriptor when this bit is set * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, * bar_frame and peer_meta_data. * * rxdma_push_reason * Reason for pushing this frame to this exit ring. Values are * defined in enum %HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_. * * rxdma_error_code * Valid only when 'push_reason' is set. All error codes are * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. * * mpdu_fragment_number * Field only valid when Reo_level_mpdu_frame_info. * Rx_mpdu_desc_info_details.Fragment_flag is set. * * sw_exception * When not set, REO is performing all its default MPDU processing * operations, * When set, this REO entrance descriptor is generated by FW, and * should be processed as an exception. This implies: * NO re-order function is needed. * MPDU delinking is determined by the setting of field * SW_excection_mpdu_delink * * sw_exception_mpdu_delink * Field only valid when SW_exception is set. * 1'b0: REO should NOT delink the MPDU, and thus pass this * MPDU on to the destination ring as is. This implies that * in the REO_DESTINATION_RING struct field * Buf_or_link_desc_addr_info should point to an MSDU link * descriptor * 1'b1: REO should perform the normal MPDU delink into MSDU operations. * * sw_exception_dest_ring * Field only valid when fields SW_exception and SW * exception_destination_ring_valid are set. values are defined * in %HAL_RX_REO_DEST_RING_. * * mpdu_seq_number * The field can have two different meanings based on the setting * of sub-field Reo level mpdu frame info. * Rx_mpdu_desc_info_details. BAR_frame * 'BAR_frame' is NOT set: * The MPDU sequence number of the received frame. * 'BAR_frame' is set. * The MPDU Start sequence number from the BAR frame * * phy_ppdu_id * A PPDU counter value that PHY increments for every PPDU received * * src_link_id * Set to the link ID of the PMAC that received the frame * * ring_id * The buffer pointer ring id. * 0 - Idle ring * 1 - N refers to other rings. * * looping_count * Indicates the number of times the producer of entries into * this ring has looped around the ring. */ #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER … #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED … struct hal_reo_cmd_hdr { … } __packed; #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI … #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS … struct hal_reo_get_queue_stats { … } __packed; /* hal_reo_get_queue_stats * Producer: SW * Consumer: REO * * cmd * Details for command execution tracking purposes. * * queue_addr_lo * Address (lower 32 bits) of the REO queue descriptor. * * queue_addr_hi * Address (upper 8 bits) of the REO queue descriptor. * * clear_stats * Clear stats settings. When set, Clear the stats after * generating the status. * * Following stats will be cleared. * Timeout_count * Forward_due_to_bar_count * Duplicate_count * Frames_in_order_count * BAR_received_count * MPDU_Frames_processed_count * MSDU_Frames_processed_count * Total_processed_byte_count * Late_receive_MPDU_count * window_jump_2k * Hole_count */ #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI … #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR … #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX … struct hal_reo_flush_queue { … } __packed; #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI … #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS … #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX … #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX … #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE … #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE … #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL … struct hal_reo_flush_cache { … } __packed; #define HAL_TCL_DATA_CMD_INFO0_CMD_TYPE … #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE … #define HAL_TCL_DATA_CMD_INFO0_BANK_ID … #define HAL_TCL_DATA_CMD_INFO0_TX_NOTIFY_FRAME … #define HAL_TCL_DATA_CMD_INFO0_HDR_LEN_READ_SEL … #define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP … #define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP_VLD … #define HAL_TCL_DATA_CMD_INFO1_CMD_NUM … #define HAL_TCL_DATA_CMD_INFO2_DATA_LEN … #define HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN … #define HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN … #define HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN … #define HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN … #define HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN … #define HAL_TCL_DATA_CMD_INFO2_TO_FW … #define HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET … #define HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE … #define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE_EN … #define HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL … #define HAL_TCL_DATA_CMD_INFO3_TID … #define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE … #define HAL_TCL_DATA_CMD_INFO3_PMAC_ID … #define HAL_TCL_DATA_CMD_INFO3_MSDU_COLOR … #define HAL_TCL_DATA_CMD_INFO3_VDEV_ID … #define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX … #define HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM … #define HAL_TCL_DATA_CMD_INFO4_IDX_LOOKUP_OVERRIDE … #define HAL_TCL_DATA_CMD_INFO5_RING_ID … #define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT … enum hal_encrypt_type { … }; enum hal_tcl_encap_type { … }; enum hal_tcl_desc_type { … }; enum hal_wbm_htt_tx_comp_status { … }; struct hal_tcl_data_cmd { … } __packed; /* hal_tcl_data_cmd * * buf_addr_info * Details of the physical address of a buffer or MSDU * link descriptor. * * tcl_cmd_type * used to select the type of TCL Command descriptor * * desc_type * Indicates the type of address provided in the buf_addr_info. * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. * * bank_id * used to select one of the TCL register banks for fields removed * from 'TCL_DATA_CMD' that do not change often within one virtual * device or a set of virtual devices: * * tx_notify_frame * TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame. * * hdr_length_read_sel * used to select the per 'encap_type' register set for MSDU header * read length * * buffer_timestamp * buffer_timestamp_valid * Frame system entrance timestamp. It shall be filled by first * module (SW, TCL or TQM) that sees the frames first. * * cmd_num * This number can be used to match against status. * * data_length * MSDU length in case of direct descriptor. Length of link * extension descriptor in case of Link extension descriptor. * * *_checksum_en * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. * * to_fw * Forward packet to FW along with classification result. The * packet will not be forward to TQM when this bit is set. * 1'b0: Use classification result to forward the packet. * 1'b1: Override classification result & forward packet only to fw * * packet_offset * Packet offset from Metadata in case of direct buffer descriptor. * * hlos_tid_overwrite * * When set, TCL shall ignore the IP DSCP and VLAN PCP * fields and use HLOS_TID as the final TID. Otherwise TCL * shall consider the DSCP and PCP fields as well as HLOS_TID * and choose a final TID based on the configured priority * * flow_override_enable * TCL uses this to select the flow pointer from the peer table, * which can be overridden by SW for pre-encrypted raw WiFi packets * that cannot be parsed for UDP or for other MLO * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4 * or IPv6 header. * 1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and * flow_override fields to select the flow-pointer * * who_classify_info_sel * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. * This field is used to select one of the 'WHO_CLASSIFY_INFO's in the * peer table in case more than 2 flows are mapped to a single TID. * 0: To choose Flow 0 and 1 of any TID use this value. * 1: To choose Flow 2 and 3 of any TID use this value. * 2: To choose Flow 4 and 5 of any TID use this value. * 3: To choose Flow 6 and 7 of any TID use this value. * * If who_classify_info sel is not in sync with the num_tx_classify_info * field from address search, then TCL will set 'who_classify_info_sel' * to 0 use flows 0 and 1. * * hlos_tid * HLOS MSDU priority * Field is used when HLOS_TID_overwrite is set. * * flow_override * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE * TCL uses this to select the flow pointer from the peer table, * which can be overridden by SW for pre-encrypted raw WiFi packets * that cannot be parsed for UDP or for other MLO * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0) * 1 - FP_USE_UDP: Use the UDP flow pointer (flow 1) * * pmac_id * TCL uses this PMAC_ID in address search, i.e, while * finding matching entry for the packet in AST corresponding * to given PMAC_ID * * If PMAC ID is all 1s (=> value 3), it indicates wildcard * match for any PMAC * * vdev_id * Virtual device ID to check against the address search entry to * avoid security issues from transmitting packets from an incorrect * virtual device * * search_index * The index that will be used for index based address or * flow search. The field is valid when 'search_type' is 1 or 2. * * cache_set_num * * Cache set number that should be used to cache the index * based search results, for address and flow search. This * value should be equal to LSB four bits of the hash value of * match data, in case of search index points to an entry which * may be used in content based search also. The value can be * anything when the entry pointed by search index will not be * used for content based search. * * index_loop_override * When set, address search and packet routing is forced to use * 'search_index' instead of following the register configuration * selected by Bank_id. * * ring_id * The buffer pointer ring ID. * 0 refers to the IDLE ring * 1 - N refers to other rings * * looping_count * * A count value that indicates the number of times the * producer of entries into the Ring has looped around the * ring. * * At initialization time, this value is set to 0. On the * first loop, this value is set to 1. After the max value is * reached allowed by the number of bits for this field, the * count value continues with 0 again. * * In case SW is the consumer of the ring entries, it can * use this field to figure out up to where the producer of * entries has created new entries. This eliminates the need to * check where the head pointer' of the ring is located once * the SW starts processing an interrupt indicating that new * entries have been put into this ring... * * Also note that SW if it wants only needs to look at the * LSB bit of this count value. */ #define HAL_TCL_DESC_LEN … #define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO … #define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI … #define HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE … #define HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE … #define HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE … #define HAL_TX_MSDU_EXT_INFO1_BUF_LEN … struct hal_tx_msdu_ext_desc { … }; struct hal_tcl_gse_cmd { … } __packed; /* hal_tcl_gse_cmd * * ctrl_buf_addr_lo, ctrl_buf_addr_hi * Address of a control buffer containing additional info needed * for this command execution. * * meta_data * Meta data to be returned in the status descriptor */ enum hal_tcl_cache_op_res { … }; struct hal_tcl_status_ring { … } __packed; /* hal_tcl_status_ring * * msdu_cnt * msdu_byte_count * MSDU count of Entry and MSDU byte count for entry 1. * */ #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI … #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN … #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP … #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP … #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER … #define HAL_CE_SRC_DESC_ADDR_INFO_LEN … #define HAL_CE_SRC_DESC_META_INFO_DATA … #define HAL_CE_SRC_DESC_FLAGS_RING_ID … #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT … struct hal_ce_srng_src_desc { … } __packed; /* hal_ce_srng_src_desc * * buffer_addr_lo * LSB 32 bits of the 40 Bit Pointer to the source buffer * * buffer_addr_hi * MSB 8 bits of the 40 Bit Pointer to the source buffer * * toeplitz_en * Enable generation of 32-bit Toeplitz-LFSR hash for * data transfer. In case of gather field in first source * ring entry of the gather copy cycle in taken into account. * * src_swap * Treats source memory organization as big-endian. For * each dword read (4 bytes), the byte 0 is swapped with byte 3 * and byte 1 is swapped with byte 2. * In case of gather field in first source ring entry of * the gather copy cycle in taken into account. * * dest_swap * Treats destination memory organization as big-endian. * For each dword write (4 bytes), the byte 0 is swapped with * byte 3 and byte 1 is swapped with byte 2. * In case of gather field in first source ring entry of * the gather copy cycle in taken into account. * * gather * Enables gather of multiple copy engine source * descriptors to one destination. * * ce_res_0 * Reserved * * * length * Length of the buffer in units of octets of the current * descriptor * * fw_metadata * Meta data used by FW. * In case of gather field in first source ring entry of * the gather copy cycle in taken into account. * * ce_res_1 * Reserved * * ce_res_2 * Reserved * * ring_id * The buffer pointer ring ID. * 0 refers to the IDLE ring * 1 - N refers to other rings * Helps with debugging when dumping ring contents. * * looping_count * A count value that indicates the number of times the * producer of entries into the Ring has looped around the * ring. * * At initialization time, this value is set to 0. On the * first loop, this value is set to 1. After the max value is * reached allowed by the number of bits for this field, the * count value continues with 0 again. * * In case SW is the consumer of the ring entries, it can * use this field to figure out up to where the producer of * entries has created new entries. This eliminates the need to * check where the head pointer' of the ring is located once * the SW starts processing an interrupt indicating that new * entries have been put into this ring... * * Also note that SW if it wants only needs to look at the * LSB bit of this count value. */ #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI … #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID … #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT … struct hal_ce_srng_dest_desc { … } __packed; /* hal_ce_srng_dest_desc * * dst_buffer_low * LSB 32 bits of the 40 Bit Pointer to the Destination * buffer * * dst_buffer_high * MSB 8 bits of the 40 Bit Pointer to the Destination * buffer * * ce_res_4 * Reserved * * ring_id * The buffer pointer ring ID. * 0 refers to the IDLE ring * 1 - N refers to other rings * Helps with debugging when dumping ring contents. * * looping_count * A count value that indicates the number of times the * producer of entries into the Ring has looped around the * ring. * * At initialization time, this value is set to 0. On the * first loop, this value is set to 1. After the max value is * reached allowed by the number of bits for this field, the * count value continues with 0 again. * * In case SW is the consumer of the ring entries, it can * use this field to figure out up to where the producer of * entries has created new entries. This eliminates the need to * check where the head pointer' of the ring is located once * the SW starts processing an interrupt indicating that new * entries have been put into this ring... * * Also note that SW if it wants only needs to look at the * LSB bit of this count value. */ #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN … #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP … #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP … #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER … #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN … #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA … #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID … #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT … struct hal_ce_srng_dst_status_desc { … } __packed; /* hal_ce_srng_dst_status_desc * * ce_res_5 * Reserved * * toeplitz_en * * src_swap * Source memory buffer swapped * * dest_swap * Destination memory buffer swapped * * gather * Gather of multiple copy engine source descriptors to one * destination enabled * * ce_res_6 * Reserved * * length * Sum of all the Lengths of the source descriptor in the * gather chain * * toeplitz_hash_0 * 32 LS bits of 64 bit Toeplitz LFSR hash result * * toeplitz_hash_1 * 32 MS bits of 64 bit Toeplitz LFSR hash result * * fw_metadata * Meta data used by FW * In case of gather field in first source ring entry of * the gather copy cycle in taken into account. * * ce_res_7 * Reserved * * ring_id * The buffer pointer ring ID. * 0 refers to the IDLE ring * 1 - N refers to other rings * Helps with debugging when dumping ring contents. * * looping_count * A count value that indicates the number of times the * producer of entries into the Ring has looped around the * ring. * * At initialization time, this value is set to 0. On the * first loop, this value is set to 1. After the max value is * reached allowed by the number of bits for this field, the * count value continues with 0 again. * * In case SW is the consumer of the ring entries, it can * use this field to figure out up to where the producer of * entries has created new entries. This eliminates the need to * check where the head pointer' of the ring is located once * the SW starts processing an interrupt indicating that new * entries have been put into this ring... * * Also note that SW if it wants only needs to look at the * LSB bit of this count value. */ #define HAL_TX_RATE_STATS_INFO0_VALID … #define HAL_TX_RATE_STATS_INFO0_BW … #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE … #define HAL_TX_RATE_STATS_INFO0_STBC … #define HAL_TX_RATE_STATS_INFO0_LDPC … #define HAL_TX_RATE_STATS_INFO0_SGI … #define HAL_TX_RATE_STATS_INFO0_MCS … #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX … #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU … enum hal_tx_rate_stats_bw { … }; enum hal_tx_rate_stats_pkt_type { … }; enum hal_tx_rate_stats_sgi { … }; struct hal_tx_rate_stats { … } __packed; struct hal_wbm_link_desc { … } __packed; /* hal_wbm_link_desc * * Producer: WBM * Consumer: WBM * * buf_addr_info * Details of the physical address of a buffer or MSDU * link descriptor. */ enum hal_wbm_rel_src_module { … }; enum hal_wbm_rel_desc_type { … }; /* hal_wbm_rel_desc_type * * msdu_buffer * The address points to an MSDU buffer * * msdu_link_descriptor * The address points to an Tx MSDU link descriptor * * mpdu_link_descriptor * The address points to an MPDU link descriptor * * msdu_ext_descriptor * The address points to an MSDU extension descriptor * * queue_ext_descriptor * The address points to an TQM queue extension descriptor. WBM should * treat this is the same way as a link descriptor. */ enum hal_wbm_rel_bm_act { … }; /* hal_wbm_rel_bm_act * * put_in_idle_list * Put the buffer or descriptor back in the idle list. In case of MSDU or * MDPU link descriptor, BM does not need to check to release any * individual MSDU buffers. * * release_msdu_list * This BM action can only be used in combination with desc_type being * msdu_link_descriptor. Field first_msdu_index points out which MSDU * pointer in the MSDU link descriptor is the first of an MPDU that is * released. BM shall release all the MSDU buffers linked to this first * MSDU buffer pointer. All related MSDU buffer pointer entries shall be * set to value 0, which represents the 'NULL' pointer. When all MSDU * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link * descriptor itself shall also be released. */ #define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE … #define HAL_WBM_COMPL_RX_INFO0_BM_ACTION … #define HAL_WBM_COMPL_RX_INFO0_DESC_TYPE … #define HAL_WBM_COMPL_RX_INFO0_RBM … #define HAL_WBM_COMPL_RX_INFO0_RXDMA_PUSH_REASON … #define HAL_WBM_COMPL_RX_INFO0_RXDMA_ERROR_CODE … #define HAL_WBM_COMPL_RX_INFO0_REO_PUSH_REASON … #define HAL_WBM_COMPL_RX_INFO0_REO_ERROR_CODE … #define HAL_WBM_COMPL_RX_INFO0_WBM_INTERNAL_ERROR … #define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI … #define HAL_WBM_COMPL_RX_INFO1_SW_COOKIE … #define HAL_WBM_COMPL_RX_INFO1_LOOPING_COUNT … struct hal_wbm_completion_ring_rx { … } __packed; #define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE … #define HAL_WBM_COMPL_TX_INFO0_DESC_TYPE … #define HAL_WBM_COMPL_TX_INFO0_RBM … #define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON … #define HAL_WBM_COMPL_TX_INFO0_RBM_OVERRIDE_VLD … #define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO … #define HAL_WBM_COMPL_TX_INFO0_CC_DONE … #define HAL_WBM_COMPL_TX_INFO0_WBM_INTERNAL_ERROR … #define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER … #define HAL_WBM_COMPL_TX_INFO1_TRANSMIT_COUNT … #define HAL_WBM_COMPL_TX_INFO1_SW_REL_DETAILS_VALID … #define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI … #define HAL_WBM_COMPL_TX_INFO2_FIRST_MSDU … #define HAL_WBM_COMPL_TX_INFO2_LAST_MSDU … #define HAL_WBM_COMPL_TX_INFO2_FW_TX_NOTIF_FRAME … #define HAL_WBM_COMPL_TX_INFO2_BUFFER_TIMESTAMP … #define HAL_WBM_COMPL_TX_INFO3_PEER_ID … #define HAL_WBM_COMPL_TX_INFO3_TID … #define HAL_WBM_COMPL_TX_INFO3_SW_COOKIE_HI … #define HAL_WBM_COMPL_TX_INFO3_LOOPING_COUNT … struct hal_wbm_completion_ring_tx { … } __packed; #define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE … #define HAL_WBM_RELEASE_TX_INFO0_BM_ACTION … #define HAL_WBM_RELEASE_TX_INFO0_DESC_TYPE … #define HAL_WBM_RELEASE_TX_INFO0_FIRST_MSDU_IDX … #define HAL_WBM_RELEASE_TX_INFO0_TQM_RELEASE_REASON … #define HAL_WBM_RELEASE_TX_INFO0_RBM_OVERRIDE_VLD … #define HAL_WBM_RELEASE_TX_INFO0_SW_BUFFER_COOKIE_11_0 … #define HAL_WBM_RELEASE_TX_INFO0_WBM_INTERNAL_ERROR … #define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER … #define HAL_WBM_RELEASE_TX_INFO1_TRANSMIT_COUNT … #define HAL_WBM_RELEASE_TX_INFO1_SW_REL_DETAILS_VALID … #define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI … #define HAL_WBM_RELEASE_TX_INFO2_FIRST_MSDU … #define HAL_WBM_RELEASE_TX_INFO2_LAST_MSDU … #define HAL_WBM_RELEASE_TX_INFO2_FW_TX_NOTIF_FRAME … #define HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP … #define HAL_WBM_RELEASE_TX_INFO3_PEER_ID … #define HAL_WBM_RELEASE_TX_INFO3_TID … #define HAL_WBM_RELEASE_TX_INFO3_SW_BUFFER_COOKIE_19_12 … #define HAL_WBM_RELEASE_TX_INFO3_LOOPING_COUNT … struct hal_wbm_release_ring_tx { … } __packed; #define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE … #define HAL_WBM_RELEASE_RX_INFO0_BM_ACTION … #define HAL_WBM_RELEASE_RX_INFO0_DESC_TYPE … #define HAL_WBM_RELEASE_RX_INFO0_FIRST_MSDU_IDX … #define HAL_WBM_RELEASE_RX_INFO0_CC_STATUS … #define HAL_WBM_RELEASE_RX_INFO0_RXDMA_PUSH_REASON … #define HAL_WBM_RELEASE_RX_INFO0_RXDMA_ERROR_CODE … #define HAL_WBM_RELEASE_RX_INFO0_REO_PUSH_REASON … #define HAL_WBM_RELEASE_RX_INFO0_REO_ERROR_CODE … #define HAL_WBM_RELEASE_RX_INFO0_WBM_INTERNAL_ERROR … #define HAL_WBM_RELEASE_RX_INFO2_RING_ID … #define HAL_WBM_RELEASE_RX_INFO2_LOOPING_COUNT … struct hal_wbm_release_ring_rx { … } __packed; #define HAL_WBM_RELEASE_RX_CC_INFO0_RBM … #define HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE … /* Used when hw cc is success */ struct hal_wbm_release_ring_cc_rx { … } __packed; #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE … #define HAL_WBM_RELEASE_INFO0_BM_ACTION … #define HAL_WBM_RELEASE_INFO0_DESC_TYPE … #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON … #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE … #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON … #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE … #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR … #define HAL_WBM_RELEASE_INFO3_FIRST_MSDU … #define HAL_WBM_RELEASE_INFO3_LAST_MSDU … #define HAL_WBM_RELEASE_INFO3_CONTINUATION … #define HAL_WBM_RELEASE_INFO5_LOOPING_COUNT … struct hal_wbm_release_ring { … } __packed; /* hal_wbm_release_ring * * Producer: SW/TQM/RXDMA/REO/SWITCH * Consumer: WBM/SW/FW * * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 * for software based completions. * * buf_addr_info * Details of the physical address of the buffer or link descriptor. * * release_source_module * Indicates which module initiated the release of this buffer/descriptor. * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. * * buffer_or_desc_type * Field only valid when WBM is marked as the return_buffer_manager in * the Released_Buffer_address_info. Indicates that type of buffer or * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. * * wbm_internal_error * Is set when WBM got a buffer pointer but the action was to push it to * the idle link descriptor ring or do link related activity OR * Is set when WBM got a link buffer pointer but the action was to push it * to the buffer descriptor ring. * * looping_count * A count value that indicates the number of times the * producer of entries into the Buffer Manager Ring has looped * around the ring. * * At initialization time, this value is set to 0. On the * first loop, this value is set to 1. After the max value is * reached allowed by the number of bits for this field, the * count value continues with 0 again. * * In case SW is the consumer of the ring entries, it can * use this field to figure out up to where the producer of * entries has created new entries. This eliminates the need to * check where the head pointer' of the ring is located once * the SW starts processing an interrupt indicating that new * entries have been put into this ring... * * Also note that SW if it wants only needs to look at the * LSB bit of this count value. */ /** * enum hal_wbm_tqm_rel_reason - TQM release reason code * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus * initiated by sw. * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus * initiated by sw. * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or * mpdus. * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by * fw with fw_reason1. * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by * fw with fw_reason2. * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by * fw with fw_reason3. * @HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE: Remove command initiated by * fw with disable queue. * @HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING: Remove command initiated by * fw to remove all mpdu until 1st non-match. * @HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: Dropped due to drop threshold * criteria * @HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL: Dropped due to link desc * not available * @HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU: Dropped due drop bit set or * null flow * @HAL_WBM_TQM_REL_REASON_MULTICAST_DROP: Dropped due mcast drop set for VDEV * @HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP: Dropped due to being set with * 'TCL_drop_reason' */ enum hal_wbm_tqm_rel_reason { … }; struct hal_wbm_buffer_ring { … }; enum hal_mon_end_reason { … }; #define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON … #define HAL_SW_MONITOR_RING_INFO0_RXDMA_ERROR_CODE … #define HAL_SW_MONITOR_RING_INFO0_MPDU_FRAGMENT_NUMBER … #define HAL_SW_MONITOR_RING_INFO0_FRAMELESS_BAR … #define HAL_SW_MONITOR_RING_INFO0_STATUS_BUF_COUNT … #define HAL_SW_MONITOR_RING_INFO0_END_OF_PPDU … #define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID … #define HAL_SW_MONITOR_RING_INFO1_RING_ID … #define HAL_SW_MONITOR_RING_INFO1_LOOPING_COUNT … struct hal_sw_monitor_ring { … } __packed; /* hal_sw_monitor_ring * * Producer: RXDMA * Consumer: REO/SW/FW * buf_addr_info * Details of the physical address of a buffer or MSDU * link descriptor. * * rx_mpdu_info * Details related to the MPDU being pushed to SW, valid * only if end_of_ppdu is set to 0. * * status_buff_addr_info * Details of the physical address of the first status * buffer used for the PPDU (either the PPDU that included the * MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU * whose end is indicated through end_of_ppdu = 1) * * rxdma_push_reason * Indicates why RXDMA pushed the frame to this ring * * <enum 0 rxdma_error_detected> RXDMA detected an error an * pushed this frame to this queue * * <enum 1 rxdma_routing_instruction> RXDMA pushed the * frame to this queue per received routing instructions. No * error within RXDMA was detected * * <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a * result the MSDU link descriptor might not have the * last_msdu_in_mpdu_flag set, but instead WBM might just see a * NULL pointer in the MSDU link descriptor. This is to be * considered a normal condition for this scenario. * * rxdma_error_code * Field only valid when rxdma_push_reason is set to * 'rxdma_error_detected.' * * <enum 0 rxdma_overflow_err>MPDU frame is not complete * due to a FIFO overflow error in RXPCU. * * <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete * due to receiving incomplete MPDU from the PHY * * <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption * error or CRYPTO received an encrypted frame, but did not get * a valid corresponding key id in the peer entry. * * <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC * error * * <enum 5 rxdma_unecrypted_err>CRYPTO reported an * unencrypted frame error when encrypted was expected * * <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU * length error * * <enum 7 rxdma_msdu_limit_err>RX OLE reported that max * number of MSDUs allowed in an MPDU got exceeded * * <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing * error * * <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU * parsing error * * <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout * during SA search * * <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout * during DA search * * <enum 12 rxdma_flow_timeout_err>RX OLE reported a * timeout during flow search * * <enum 13 rxdma_flush_request>RXDMA received a flush * request * * <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU * present as well as a fragmented MPDU. * * mpdu_fragment_number * Field only valid when Reo_level_mpdu_frame_info. * Rx_mpdu_desc_info_details.Fragment_flag is set and * end_of_ppdu is set to 0. * * The fragment number from the 802.11 header. * * Note that the sequence number is embedded in the field: * Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. * Mpdu_sequence_number * * frameless_bar * When set, this SW monitor ring struct contains BAR info * from a multi TID BAR frame. The original multi TID BAR frame * itself contained all the REO info for the first TID, but all * the subsequent TID info and their linkage to the REO * descriptors is passed down as 'frameless' BAR info. * * The only fields valid in this descriptor when this bit * is within the * * Reo_level_mpdu_frame_info: * Within Rx_mpdu_desc_info_details: * Mpdu_Sequence_number * BAR_frame * Peer_meta_data * All other fields shall be set to 0. * * status_buf_count * A count of status buffers used so far for the PPDU * (either the PPDU that included the MPDU being pushed to SW * if end_of_ppdu = 0, or the PPDU whose end is indicated * through end_of_ppdu = 1) * * end_of_ppdu * Some hw RXDMA can be configured to generate a separate * 'SW_MONITOR_RING' descriptor at the end of a PPDU (either * through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to * demarcate PPDUs. * * For such a descriptor, this bit is set to 1 and fields * Reo_level_mpdu_frame_info, mpdu_fragment_number and * Frameless_bar are all set to 0. * * Otherwise this bit is set to 0. * * phy_ppdu_id * A PPDU counter value that PHY increments for every PPDU * received * * The counter value wraps around. Some hw RXDMA can be * configured to copy this from the RX_PPDU_START TLV for every * output descriptor. * * ring_id * For debugging. * This field is filled in by the SRNG module. * It help to identify the ring that is being looked * * looping_count * For debugging. * This field is filled in by the SRNG module. * * A count value that indicates the number of times the * producer of entries into this Ring has looped around the * ring. * At initialization time, this value is set to 0. On the * first loop, this value is set to 1. After the max value is * reached allowed by the number of bits for this field, the * count value continues with 0 again. * * In case SW is the consumer of the ring entries, it can * use this field to figure out up to where the producer of * entries has created new entries. This eliminates the need to * check where the head pointer' of the ring is located once * the SW starts processing an interrupt indicating that new * entries have been put into this ring... */ enum hal_desc_owner { … }; enum hal_desc_buf_type { … }; #define HAL_DESC_REO_OWNED … #define HAL_DESC_REO_QUEUE_DESC … #define HAL_DESC_REO_QUEUE_EXT_DESC … #define HAL_DESC_REO_NON_QOS_TID … #define HAL_DESC_HDR_INFO0_OWNER … #define HAL_DESC_HDR_INFO0_BUF_TYPE … #define HAL_DESC_HDR_INFO0_DBG_RESERVED … struct hal_desc_header { … } __packed; struct hal_rx_mpdu_link_ptr { … } __packed; struct hal_rx_msdu_details { … } __packed; #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER … #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK … struct hal_rx_msdu_link { … } __packed; struct hal_rx_reo_queue_ext { … } __packed; /* hal_rx_reo_queue_ext * Consumer: REO * Producer: REO * * descriptor_header * Details about which module owns this struct. * * mpdu_link * Pointer to the next MPDU_link descriptor in the MPDU queue. */ enum hal_rx_reo_queue_pn_size { … }; #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER … #define HAL_RX_REO_QUEUE_INFO0_VLD … #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER … #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION … #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN … #define HAL_RX_REO_QUEUE_INFO0_AC … #define HAL_RX_REO_QUEUE_INFO0_BAR … #define HAL_RX_REO_QUEUE_INFO0_RETRY … #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE … #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE … #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE … #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK … #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN … #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN … #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE … #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE … #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG … #define HAL_RX_REO_QUEUE_INFO1_SVLD … #define HAL_RX_REO_QUEUE_INFO1_SSN … #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX … #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR … #define HAL_RX_REO_QUEUE_INFO1_PN_ERR … #define HAL_RX_REO_QUEUE_INFO1_PN_VALID … #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT … #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT … #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT … #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT … #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT … #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT … #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT … #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT … #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K … #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT … struct hal_rx_reo_queue { … } __packed; /* hal_rx_reo_queue * * descriptor_header * Details about which module owns this struct. Note that sub field * Buffer_type shall be set to receive_reo_queue_descriptor. * * receive_queue_number * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. * * vld * Valid bit indicating a session is established and the queue descriptor * is valid. * associated_link_descriptor_counter * Indicates which of the 3 link descriptor counters shall be incremented * or decremented when link descriptors are added or removed from this * flow queue. * disable_duplicate_detection * When set, do not perform any duplicate detection. * soft_reorder_enable * When set, REO has been instructed to not perform the actual re-ordering * of frames for this queue, but just to insert the reorder opcodes. * ac * Indicates the access category of the queue descriptor. * bar * Indicates if BAR has been received. * retry * Retry bit is checked if this bit is set. * chk_2k_mode * Indicates what type of operation is expected from Reo when the received * frame SN falls within the 2K window. * oor_mode * Indicates what type of operation is expected when the received frame * falls within the OOR window. * ba_window_size * Indicates the negotiated (window size + 1). Max of 256 bits. * * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA * session, with window size of 0). The 3 values here are the main values * validated, but other values should work as well. * * A BA window size of 0 (=> one frame entry bitmat), means that there is * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, * pn_size * REO shall perform the PN increment check, even number check, uneven * number check, PN error check and size of the PN field check. * ignore_ampdu_flag * REO shall ignore the ampdu_flag on entrance descriptor for this queue. * * svld * Sequence number in next field is valid one. * ssn * Starting Sequence number of the session. * current_index * Points to last forwarded packet * seq_2k_error_detected_flag * REO has detected a 2k error jump in the sequence number and from that * moment forward, all new frames are forwarded directly to FW, without * duplicate detect, reordering, etc. * pn_error_detected_flag * REO has detected a PN error. */ #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID … #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN … #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER … #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD … #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER … #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION … #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN … #define HAL_REO_UPD_RX_QUEUE_INFO1_AC … #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR … #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY … #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE … #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE … #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK … #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN … #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN … #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE … #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG … #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE … #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE … #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD … #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN … #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR … #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR … #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID … struct hal_reo_update_rx_queue { … } __packed; struct hal_rx_reo_queue_1k { … } __packed; #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE … #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX … struct hal_reo_unblock_cache { … } __packed; enum hal_reo_exec_status { … }; #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM … #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME … #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS … struct hal_reo_status_hdr { … } __packed; /* hal_reo_status_hdr * Producer: REO * Consumer: SW * * status_num * The value in this field is equal to value of the reo command * number. This field helps to correlate the statuses with the REO * commands. * * execution_time (in us) * The amount of time REO took to execute the command. Note that * this time does not include the duration of the command waiting * in the command ring, before the execution started. * * execution_status * Execution status of the command. Values are defined in * enum %HAL_REO_EXEC_STATUS_. */ #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT … #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT … struct hal_reo_get_queue_stats_status { … } __packed; /* hal_reo_get_queue_stats_status * Producer: REO * Consumer: SW * * status_hdr * Details that can link this status with the original command. It * also contains info on how long REO took to execute this command. * * ssn * Starting Sequence number of the session, this changes whenever * window moves (can be filled by SW then maintained by REO). * * current_index * Points to last forwarded packet. * * pn * Bits of the PN number. * * last_rx_enqueue_timestamp * last_rx_dequeue_timestamp * Timestamp of arrival of the last MPDU for this queue and * Timestamp of forwarding an MPDU accordingly. * * rx_bitmap * When a bit is set, the corresponding frame is currently held * in the re-order queue. The bitmap is Fully managed by HW. * * current_mpdu_count * current_msdu_count * The number of MPDUs and MSDUs in the queue. * * timeout_count * The number of times REO started forwarding frames even though * there is a hole in the bitmap. Forwarding reason is timeout. * * forward_due_to_bar_count * The number of times REO started forwarding frames even though * there is a hole in the bitmap. Fwd reason is reception of BAR. * * duplicate_count * The number of duplicate frames that have been detected. * * frames_in_order_count * The number of frames that have been received in order (without * a hole that prevented them from being forwarded immediately). * * bar_received_count * The number of times a BAR frame is received. * * mpdu_frames_processed_count * msdu_frames_processed_count * The total number of MPDU/MSDU frames that have been processed. * * total_bytes * An approximation of the number of bytes received for this queue. * * late_receive_mpdu_count * The number of MPDUs received after the window had already moved * on. The 'late' sequence window is defined as * (Window SSN - 256) - (Window SSN - 1). * * window_jump_2k * The number of times the window moved more than 2K * * hole_count * The number of times a hole was created in the receive bitmap. * * looping_count * A count value that indicates the number of times the producer of * entries into this Ring has looped around the ring. */ #define HAL_REO_STATUS_LOOP_CNT … #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED … #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD … #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD … struct hal_reo_flush_queue_status { … } __packed; /* hal_reo_flush_queue_status * Producer: REO * Consumer: SW * * status_hdr * Details that can link this status with the original command. It * also contains info on how long REO took to execute this command. * * error_detected * Status of blocking resource * * 0 - No error has been detected while executing this command * 1 - Error detected. The resource to be used for blocking was * already in use. * * looping_count * A count value that indicates the number of times the producer of * entries into this Ring has looped around the ring. */ #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR … #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE … #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT … #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE … #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID … #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR … #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT … struct hal_reo_flush_cache_status { … } __packed; /* hal_reo_flush_cache_status * Producer: REO * Consumer: SW * * status_hdr * Details that can link this status with the original command. It * also contains info on how long REO took to execute this command. * * error_detected * Status for blocking resource handling * * 0 - No error has been detected while executing this command * 1 - An error in the blocking resource management was detected * * block_error_details * only valid when error_detected is set * * 0 - No blocking related errors found * 1 - Blocking resource is already in use * 2 - Resource requested to be unblocked, was not blocked * * cache_controller_flush_status_hit * The status that the cache controller returned on executing the * flush command. * * 0 - miss; 1 - hit * * cache_controller_flush_status_desc_type * Flush descriptor type * * cache_controller_flush_status_client_id * Module who made the flush request * * In REO, this is always 0 * * cache_controller_flush_status_error * Error condition * * 0 - No error found * 1 - HW interface is still busy * 2 - Line currently locked. Used for one line flush command * 3 - At least one line is still locked. * Used for cache flush command. * * cache_controller_flush_count * The number of lines that were actually flushed out * * looping_count * A count value that indicates the number of times the producer of * entries into this Ring has looped around the ring. */ #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR … #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE … struct hal_reo_unblock_cache_status { … } __packed; /* hal_reo_unblock_cache_status * Producer: REO * Consumer: SW * * status_hdr * Details that can link this status with the original command. It * also contains info on how long REO took to execute this command. * * error_detected * 0 - No error has been detected while executing this command * 1 - The blocking resource was not in use, and therefore it could * not be unblocked. * * unblock_type * Reference to the type of unblock command * 0 - Unblock a blocking resource * 1 - The entire cache usage is unblock * * looping_count * A count value that indicates the number of times the producer of * entries into this Ring has looped around the ring. */ #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR … #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY … #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT … #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT … struct hal_reo_flush_timeout_list_status { … } __packed; /* hal_reo_flush_timeout_list_status * Producer: REO * Consumer: SW * * status_hdr * Details that can link this status with the original command. It * also contains info on how long REO took to execute this command. * * error_detected * 0 - No error has been detected while executing this command * 1 - Command not properly executed and returned with error * * timeout_list_empty * When set, REO has depleted the timeout list and all entries are * gone. * * release_desc_count * Producer: SW; Consumer: REO * The number of link descriptor released * * forward_buf_count * Producer: SW; Consumer: REO * The number of buffers forwarded to the REO destination rings * * looping_count * A count value that indicates the number of times the producer of * entries into this Ring has looped around the ring. */ #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX … #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 … #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 … #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 … #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM … struct hal_reo_desc_thresh_reached_status { … } __packed; /* hal_reo_desc_thresh_reached_status * Producer: REO * Consumer: SW * * status_hdr * Details that can link this status with the original command. It * also contains info on how long REO took to execute this command. * * threshold_index * The index of the threshold register whose value got reached * * link_descriptor_counter0 * link_descriptor_counter1 * link_descriptor_counter2 * link_descriptor_counter_sum * Value of the respective counters at generation of this message * * looping_count * A count value that indicates the number of times the producer of * entries into this Ring has looped around the ring. */ #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L4_CSUM_STATUS … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L3_CSUM_STATUS … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_QDISC … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MULTICAST … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MORE … #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_VALID_TOGGLE … struct hal_tcl_entrance_from_ppe_ring { … } __packed; struct hal_mon_buf_ring { … }; /* hal_mon_buf_ring * Producer : SW * Consumer : Monitor * * paddr_lo * Lower 32-bit physical address of the buffer pointer from the source ring. * paddr_hi * bit range 7-0 : upper 8 bit of the physical address. * bit range 31-8 : reserved. * cookie * Consumer: RxMon/TxMon 64 bit cookie of the buffers. */ #define HAL_MON_DEST_COOKIE_BUF_ID … #define HAL_MON_DEST_INFO0_END_OFFSET … #define HAL_MON_DEST_INFO0_FLUSH_DETECTED … #define HAL_MON_DEST_INFO0_END_OF_PPDU … #define HAL_MON_DEST_INFO0_INITIATOR … #define HAL_MON_DEST_INFO0_EMPTY_DESC … #define HAL_MON_DEST_INFO0_RING_ID … #define HAL_MON_DEST_INFO0_LOOPING_COUNT … struct hal_mon_dest_desc { … }; /* hal_mon_dest_ring * Producer : TxMon/RxMon * Consumer : SW * cookie * bit 0 -17 buf_id to track the skb's vaddr. * ppdu_id * Phy ppdu_id * end_offset * The offset into status buffer where DMA ended, ie., offset to the last * TLV + last TLV size. * flush_detected * Indicates whether 'tx_flush' or 'rx_flush' occurred. * end_of_ppdu * Indicates end of ppdu. * pmac_id * Indicates PMAC that received from frame. * empty_descriptor * This descriptor is written on flush or end of ppdu or end of status * buffer. * ring_id * updated by SRNG. * looping_count * updated by SRNG. */ #define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG … #define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE … #define HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL … struct hal_tx_msdu_metadata { … } __packed; /* hal_tx_msdu_metadata * valid_encrypt_type * if set, encrypt type is valid * encrypt_type * 0 = NO_ENCRYPT, * 1 = ENCRYPT, * 2 ~ 3 - Reserved * host_tx_desc_pool * If set, Firmware allocates tx_descriptors * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead * of WAL_BUFFERID_TX_TCL_DATA_EXP. * Use cases: * Any time firmware uses TQM-BYPASS for Data * TID, firmware expect host to set this bit. */ #endif /* ATH12K_HAL_DESC_H */
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