/* SPDX-License-Identifier: GPL-2.0-only */ /****************************************************************************** Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved. Contact Information: Intel Linux Wireless <[email protected]> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 ******************************************************************************/ #ifndef __ipw2200_h__ #define __ipw2200_h__ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/interrupt.h> #include <linux/mutex.h> #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/ethtool.h> #include <linux/skbuff.h> #include <linux/etherdevice.h> #include <linux/delay.h> #include <linux/random.h> #include <linux/dma-mapping.h> #include <linux/firmware.h> #include <linux/wireless.h> #include <linux/jiffies.h> #include <asm/io.h> #include <net/lib80211.h> #include <net/ieee80211_radiotap.h> #define DRV_NAME … #include <linux/workqueue.h> #include "libipw.h" /* Authentication and Association States */ enum connection_manager_assoc_states { … }; #define IPW_WAIT … #define IPW_QUIET … #define IPW_ROAMING … #define IPW_POWER_MODE_CAM … #define IPW_POWER_INDEX_1 … #define IPW_POWER_INDEX_2 … #define IPW_POWER_INDEX_3 … #define IPW_POWER_INDEX_4 … #define IPW_POWER_INDEX_5 … #define IPW_POWER_AC … #define IPW_POWER_BATTERY … #define IPW_POWER_LIMIT … #define IPW_POWER_MASK … #define IPW_POWER_ENABLED … #define IPW_POWER_LEVEL(x) … #define IPW_CMD_HOST_COMPLETE … #define IPW_CMD_POWER_DOWN … #define IPW_CMD_SYSTEM_CONFIG … #define IPW_CMD_MULTICAST_ADDRESS … #define IPW_CMD_SSID … #define IPW_CMD_ADAPTER_ADDRESS … #define IPW_CMD_PORT_TYPE … #define IPW_CMD_RTS_THRESHOLD … #define IPW_CMD_FRAG_THRESHOLD … #define IPW_CMD_POWER_MODE … #define IPW_CMD_WEP_KEY … #define IPW_CMD_TGI_TX_KEY … #define IPW_CMD_SCAN_REQUEST … #define IPW_CMD_ASSOCIATE … #define IPW_CMD_SUPPORTED_RATES … #define IPW_CMD_SCAN_ABORT … #define IPW_CMD_TX_FLUSH … #define IPW_CMD_QOS_PARAMETERS … #define IPW_CMD_SCAN_REQUEST_EXT … #define IPW_CMD_DINO_CONFIG … #define IPW_CMD_RSN_CAPABILITIES … #define IPW_CMD_RX_KEY … #define IPW_CMD_CARD_DISABLE … #define IPW_CMD_SEED_NUMBER … #define IPW_CMD_TX_POWER … #define IPW_CMD_COUNTRY_INFO … #define IPW_CMD_AIRONET_INFO … #define IPW_CMD_AP_TX_POWER … #define IPW_CMD_CCKM_INFO … #define IPW_CMD_CCX_VER_INFO … #define IPW_CMD_SET_CALIBRATION … #define IPW_CMD_SENSITIVITY_CALIB … #define IPW_CMD_RETRY_LIMIT … #define IPW_CMD_IPW_PRE_POWER_DOWN … #define IPW_CMD_VAP_BEACON_TEMPLATE … #define IPW_CMD_VAP_DTIM_PERIOD … #define IPW_CMD_EXT_SUPPORTED_RATES … #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT … #define IPW_CMD_VAP_QUIET_INTERVALS … #define IPW_CMD_VAP_CHANNEL_SWITCH … #define IPW_CMD_VAP_MANDATORY_CHANNELS … #define IPW_CMD_VAP_CELL_PWR_LIMIT … #define IPW_CMD_VAP_CF_PARAM_SET … #define IPW_CMD_VAP_SET_BEACONING_STATE … #define IPW_CMD_MEASUREMENT … #define IPW_CMD_POWER_CAPABILITY … #define IPW_CMD_SUPPORTED_CHANNELS … #define IPW_CMD_TPC_REPORT … #define IPW_CMD_WME_INFO … #define IPW_CMD_PRODUCTION_COMMAND … #define IPW_CMD_LINKSYS_EOU_INFO … #define RFD_SIZE … #define NUM_TFD_CHUNKS … #define TX_QUEUE_SIZE … #define RX_QUEUE_SIZE … #define DINO_CMD_WEP_KEY … #define DINO_CMD_TX … #define DCT_ANTENNA_A … #define DCT_ANTENNA_B … #define IPW_A_MODE … #define IPW_B_MODE … #define IPW_G_MODE … /* * TX Queue Flag Definitions */ /* tx wep key definition */ #define DCT_WEP_KEY_NOT_IMMIDIATE … #define DCT_WEP_KEY_64Bit … #define DCT_WEP_KEY_128Bit … #define DCT_WEP_KEY_128bitIV … #define DCT_WEP_KEY_SIZE_MASK … #define DCT_WEP_KEY_INDEX_MASK … #define DCT_WEP_INDEX_USE_IMMEDIATE … /* abort attempt if mgmt frame is rx'd */ #define DCT_FLAG_ABORT_MGMT … /* require CTS */ #define DCT_FLAG_CTS_REQUIRED … /* use short preamble */ #define DCT_FLAG_LONG_PREAMBLE … #define DCT_FLAG_SHORT_PREAMBLE … /* RTS/CTS first */ #define DCT_FLAG_RTS_REQD … /* dont calculate duration field */ #define DCT_FLAG_DUR_SET … /* even if MAC WEP set (allows pre-encrypt) */ #define DCT_FLAG_NO_WEP … /* overwrite TSF field */ #define DCT_FLAG_TSF_REQD … /* ACK rx is expected to follow */ #define DCT_FLAG_ACK_REQD … /* TX flags extension */ #define DCT_FLAG_EXT_MODE_CCK … #define DCT_FLAG_EXT_MODE_OFDM … #define DCT_FLAG_EXT_SECURITY_WEP … #define DCT_FLAG_EXT_SECURITY_NO … #define DCT_FLAG_EXT_SECURITY_CKIP … #define DCT_FLAG_EXT_SECURITY_CCM … #define DCT_FLAG_EXT_SECURITY_TKIP … #define DCT_FLAG_EXT_SECURITY_MASK … #define DCT_FLAG_EXT_QOS_ENABLED … #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS … #define DCT_FLAG_EXT_HC_SIFS … #define DCT_FLAG_EXT_HC_PIFS … #define TX_RX_TYPE_MASK … #define TX_FRAME_TYPE … #define TX_HOST_COMMAND_TYPE … #define RX_FRAME_TYPE … #define RX_HOST_NOTIFICATION_TYPE … #define RX_HOST_CMD_RESPONSE_TYPE … #define RX_TX_FRAME_RESPONSE_TYPE … #define TFD_NEED_IRQ_MASK … #define HOST_CMD_DINO_CONFIG … #define HOST_NOTIFICATION_STATUS_ASSOCIATED … #define HOST_NOTIFICATION_STATUS_AUTHENTICATE … #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT … #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED … #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH … #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION … #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE … #define HOST_NOTIFICATION_STATUS_BEACON_STATE … #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY … #define HOST_NOTIFICATION_TX_STATUS … #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS … #define HOST_NOTIFICATION_MEASUREMENT_STARTED … #define HOST_NOTIFICATION_MEASUREMENT_ENDED … #define HOST_NOTIFICATION_CHANNEL_SWITCHED … #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD … #define HOST_NOTIFICATION_NOISE_STATS … #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED … #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED … #define HOST_NOTIFICATION_STATUS_BEACON_MISSING … #define IPW_MB_SCAN_CANCEL_THRESHOLD … #define IPW_MB_ROAMING_THRESHOLD_MIN … #define IPW_MB_ROAMING_THRESHOLD_DEFAULT … #define IPW_MB_ROAMING_THRESHOLD_MAX … #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT … #define IPW_REAL_RATE_RX_PACKET_THRESHOLD … #define MACADRR_BYTE_LEN … #define DCR_TYPE_AP … #define DCR_TYPE_WLAP … #define DCR_TYPE_MU_ESS … #define DCR_TYPE_MU_IBSS … #define DCR_TYPE_MU_PIBSS … #define DCR_TYPE_SNIFFER … #define DCR_TYPE_MU_BSS … /* QoS definitions */ #define CW_MIN_OFDM … #define CW_MAX_OFDM … #define CW_MIN_CCK … #define CW_MAX_CCK … #define QOS_TX0_CW_MIN_OFDM … #define QOS_TX1_CW_MIN_OFDM … #define QOS_TX2_CW_MIN_OFDM … #define QOS_TX3_CW_MIN_OFDM … #define QOS_TX0_CW_MIN_CCK … #define QOS_TX1_CW_MIN_CCK … #define QOS_TX2_CW_MIN_CCK … #define QOS_TX3_CW_MIN_CCK … #define QOS_TX0_CW_MAX_OFDM … #define QOS_TX1_CW_MAX_OFDM … #define QOS_TX2_CW_MAX_OFDM … #define QOS_TX3_CW_MAX_OFDM … #define QOS_TX0_CW_MAX_CCK … #define QOS_TX1_CW_MAX_CCK … #define QOS_TX2_CW_MAX_CCK … #define QOS_TX3_CW_MAX_CCK … #define QOS_TX0_AIFS … #define QOS_TX1_AIFS … #define QOS_TX2_AIFS … #define QOS_TX3_AIFS … #define QOS_TX0_ACM … #define QOS_TX1_ACM … #define QOS_TX2_ACM … #define QOS_TX3_ACM … #define QOS_TX0_TXOP_LIMIT_CCK … #define QOS_TX1_TXOP_LIMIT_CCK … #define QOS_TX2_TXOP_LIMIT_CCK … #define QOS_TX3_TXOP_LIMIT_CCK … #define QOS_TX0_TXOP_LIMIT_OFDM … #define QOS_TX1_TXOP_LIMIT_OFDM … #define QOS_TX2_TXOP_LIMIT_OFDM … #define QOS_TX3_TXOP_LIMIT_OFDM … #define DEF_TX0_CW_MIN_OFDM … #define DEF_TX1_CW_MIN_OFDM … #define DEF_TX2_CW_MIN_OFDM … #define DEF_TX3_CW_MIN_OFDM … #define DEF_TX0_CW_MIN_CCK … #define DEF_TX1_CW_MIN_CCK … #define DEF_TX2_CW_MIN_CCK … #define DEF_TX3_CW_MIN_CCK … #define DEF_TX0_CW_MAX_OFDM … #define DEF_TX1_CW_MAX_OFDM … #define DEF_TX2_CW_MAX_OFDM … #define DEF_TX3_CW_MAX_OFDM … #define DEF_TX0_CW_MAX_CCK … #define DEF_TX1_CW_MAX_CCK … #define DEF_TX2_CW_MAX_CCK … #define DEF_TX3_CW_MAX_CCK … #define DEF_TX0_AIFS … #define DEF_TX1_AIFS … #define DEF_TX2_AIFS … #define DEF_TX3_AIFS … #define DEF_TX0_ACM … #define DEF_TX1_ACM … #define DEF_TX2_ACM … #define DEF_TX3_ACM … #define DEF_TX0_TXOP_LIMIT_CCK … #define DEF_TX1_TXOP_LIMIT_CCK … #define DEF_TX2_TXOP_LIMIT_CCK … #define DEF_TX3_TXOP_LIMIT_CCK … #define DEF_TX0_TXOP_LIMIT_OFDM … #define DEF_TX1_TXOP_LIMIT_OFDM … #define DEF_TX2_TXOP_LIMIT_OFDM … #define DEF_TX3_TXOP_LIMIT_OFDM … #define QOS_QOS_SETS … #define QOS_PARAM_SET_ACTIVE … #define QOS_PARAM_SET_DEF_CCK … #define QOS_PARAM_SET_DEF_OFDM … #define CTRL_QOS_NO_ACK … #define IPW_TX_QUEUE_1 … #define IPW_TX_QUEUE_2 … #define IPW_TX_QUEUE_3 … #define IPW_TX_QUEUE_4 … /* QoS sturctures */ struct ipw_qos_info { … }; /**************************************************************/ /** * Generic queue structure * * Contains common data for Rx and Tx queues */ struct clx2_queue { … } __packed; /* XXX */ struct machdr32 { … } __packed; struct machdr30 { … } __packed; struct machdr26 { … } __packed; struct machdr24 { … } __packed; // TX TFD with 32 byte MAC Header struct tx_tfd_32 { … } __packed; // TX TFD with 30 byte MAC Header struct tx_tfd_30 { … } __packed; // tx tfd with 26 byte mac header struct tx_tfd_26 { … } __packed; // tx tfd with 24 byte mac header struct tx_tfd_24 { … } __packed; #define DCT_WEP_KEY_FIELD_LENGTH … struct tfd_command { … } __packed; struct tfd_data { … } __packed; struct txrx_control_flags { … } __packed; #define TFD_SIZE … #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH … struct tfd_frame { … } __packed; destructor_func; /** * Tx Queue for DMA. Queue consists of circular buffer of * BD's and required locking structures. */ struct clx2_tx_queue { … }; /* * RX related structures and functions */ #define RX_FREE_BUFFERS … #define RX_LOW_WATERMARK … #define SUP_RATE_11A_MAX_NUM_CHANNELS … #define SUP_RATE_11B_MAX_NUM_CHANNELS … #define SUP_RATE_11G_MAX_NUM_CHANNELS … // Used for passing to driver number of successes and failures per rate struct rate_histogram { … } __packed; /* statistics command response */ struct ipw_cmd_stats { … } __packed; struct notif_channel_result { … } __packed; #define SCAN_COMPLETED_STATUS_COMPLETE … #define SCAN_COMPLETED_STATUS_ABORTED … struct notif_scan_complete { … } __packed; struct notif_frag_length { … } __packed; struct notif_beacon_state { … } __packed; struct notif_tgi_tx_key { … } __packed; #define SILENCE_OVER_THRESH … #define SILENCE_UNDER_THRESH … struct notif_link_deterioration { … } __packed; struct notif_association { … } __packed; struct notif_authenticate { … } __packed; struct notif_calibration { … } __packed; struct notif_noise { … } __packed; struct ipw_rx_notification { … } __packed; struct ipw_rx_frame { … } __packed; struct ipw_rx_header { … } __packed; struct ipw_rx_packet { … } __packed; #define IPW_RX_NOTIFICATION_SIZE … #define IPW_RX_FRAME_SIZE … struct ipw_rx_mem_buffer { … }; /* Not transferred over network, so not __packed */ struct ipw_rx_queue { … }; /* Not transferred over network, so not __packed */ struct alive_command_responce { … } __packed; #define IPW_MAX_RATES … struct ipw_rates { … } __packed; struct command_block { … } __packed; #define CB_NUMBER_OF_ELEMENTS_SMALL … struct fw_image_desc { … }; struct ipw_sys_config { … } __packed; struct ipw_multicast_addr { … } __packed; #define DCW_WEP_KEY_INDEX_MASK … #define DCW_WEP_KEY_SEC_TYPE_MASK … #define DCW_WEP_KEY_SEC_TYPE_WEP … #define DCW_WEP_KEY_SEC_TYPE_CCM … #define DCW_WEP_KEY_SEC_TYPE_TKIP … #define DCW_WEP_KEY_INVALID_SIZE … #define DCW_WEP_KEY64Bit_SIZE … #define DCW_WEP_KEY128Bit_SIZE … #define DCW_CCM_KEY128Bit_SIZE … //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */ struct ipw_wep_key { … } __packed; struct ipw_tgi_tx_key { … } __packed; #define IPW_SCAN_CHANNELS … struct ipw_scan_request { … } __packed; enum { … }; struct ipw_scan_request_ext { … } __packed; static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index) { … } static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan, u8 index, u8 scan_type) { … } struct ipw_associate { … } __packed; struct ipw_supported_rates { … } __packed; struct ipw_rts_threshold { … } __packed; struct ipw_frag_threshold { … } __packed; struct ipw_retry_limit { … } __packed; struct ipw_dino_config { … } __packed; struct ipw_aironet_info { … } __packed; struct ipw_rx_key { … } __packed; struct ipw_country_channel_info { … } __packed; struct ipw_country_info { … } __packed; struct ipw_channel_tx_power { … } __packed; #define SCAN_ASSOCIATED_INTERVAL … #define SCAN_INTERVAL … #define MAX_A_CHANNELS … #define MAX_B_CHANNELS … struct ipw_tx_power { … } __packed; struct ipw_rsn_capabilities { … } __packed; struct ipw_sensitivity_calib { … } __packed; /** * Host command structure. * * On input, the following fields should be filled: * - cmd * - len * - status_len * - param (if needed) * * On output, * - \a status contains status; * - \a param filled with status parameters. */ struct ipw_cmd { … } __packed; #define STATUS_HCMD_ACTIVE … #define STATUS_INT_ENABLED … #define STATUS_RF_KILL_HW … #define STATUS_RF_KILL_SW … #define STATUS_RF_KILL_MASK … #define STATUS_INIT … #define STATUS_AUTH … #define STATUS_ASSOCIATED … #define STATUS_STATE_MASK … #define STATUS_ASSOCIATING … #define STATUS_DISASSOCIATING … #define STATUS_ROAMING … #define STATUS_EXIT_PENDING … #define STATUS_DISASSOC_PENDING … #define STATUS_STATE_PENDING … #define STATUS_DIRECT_SCAN_PENDING … #define STATUS_SCAN_PENDING … #define STATUS_SCANNING … #define STATUS_SCAN_ABORTING … #define STATUS_SCAN_FORCED … #define STATUS_LED_LINK_ON … #define STATUS_LED_ACT_ON … #define STATUS_INDIRECT_BYTE … #define STATUS_INDIRECT_DWORD … #define STATUS_DIRECT_DWORD … #define STATUS_SECURITY_UPDATED … #define CFG_STATIC_CHANNEL … #define CFG_STATIC_ESSID … #define CFG_STATIC_BSSID … #define CFG_CUSTOM_MAC … #define CFG_PREAMBLE_LONG … #define CFG_ADHOC_PERSIST … #define CFG_ASSOCIATE … #define CFG_FIXED_RATE … #define CFG_ADHOC_CREATE … #define CFG_NO_LED … #define CFG_BACKGROUND_SCAN … #define CFG_SPEED_SCAN … #define CFG_NET_STATS … #define CAP_SHARED_KEY … #define CAP_PRIVACY_ON … #define MAX_STATIONS … #define IPW_INVALID_STATION … struct ipw_station_entry { … }; #define AVG_ENTRIES … struct average { … }; #define MAX_SPEED_SCAN … #define IPW_IBSS_MAC_HASH_SIZE … struct ipw_ibss_seq { … }; struct ipw_error_elem { … }; struct ipw_event { … } __packed; struct ipw_fw_error { … } __packed; #ifdef CONFIG_IPW2200_PROMISCUOUS enum ipw_prom_filter { … }; struct ipw_priv; struct ipw_prom_priv { … }; #endif #if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS) /* Magic struct that slots into the radiotap header -- no reason * to build this manually element by element, we can write it much * more efficiently than we can parse it. ORDER MATTERS HERE * * When sent to us via the simulated Rx interface in sysfs, the entire * structure is provided regardless of any bits unset. */ struct ipw_rt_hdr { … } __packed; #endif struct ipw_priv { … }; /*ipw_priv */ /* debug macros */ /* Debug and printf string expansion helpers for printing bitfields */ #define BIT_FMT8 … #define BIT_FMT16 … #define BIT_FMT32 … #define BITC(x,y) … #define BIT_ARG8(x) … #define BIT_ARG16(x) … #define BIT_ARG32(x) … #define IPW_DEBUG(level, fmt, args...) … #ifdef CONFIG_IPW2200_DEBUG #define IPW_LL_DEBUG(level, fmt, args...) … #else #define IPW_LL_DEBUG … #endif /* CONFIG_IPW2200_DEBUG */ /* * To use the debug system; * * If you are defining a new debug classification, simply add it to the #define * list here in the form of: * * #define IPW_DL_xxxx VALUE * * shifting value to the left one bit from the previous entry. xxxx should be * the name of the classification (for example, WEP) * * You then need to either add a IPW_xxxx_DEBUG() macro definition for your * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want * to send output to that classification. * * To add your debug level to the list of levels seen when you perform * * % cat /proc/net/ipw/debug_level * * you simply need to add your entry to the ipw_debug_levels array. * * If you do not see debug_level in /proc/net/ipw then you do not have * CONFIG_IPW2200_DEBUG defined in your kernel configuration * */ #define IPW_DL_ERROR … #define IPW_DL_WARNING … #define IPW_DL_INFO … #define IPW_DL_WX … #define IPW_DL_HOST_COMMAND … #define IPW_DL_STATE … #define IPW_DL_NOTIF … #define IPW_DL_SCAN … #define IPW_DL_ASSOC … #define IPW_DL_DROP … #define IPW_DL_IOCTL … #define IPW_DL_MANAGE … #define IPW_DL_FW … #define IPW_DL_RF_KILL … #define IPW_DL_FW_ERRORS … #define IPW_DL_LED … #define IPW_DL_ORD … #define IPW_DL_FRAG … #define IPW_DL_WEP … #define IPW_DL_TX … #define IPW_DL_RX … #define IPW_DL_ISR … #define IPW_DL_FW_INFO … #define IPW_DL_IO … #define IPW_DL_TRACE … #define IPW_DL_STATS … #define IPW_DL_MERGE … #define IPW_DL_QOS … #define IPW_ERROR(f, a...) … #define IPW_WARNING(f, a...) … #define IPW_DEBUG_INFO(f, a...) … #define IPW_DEBUG_WX(f, a...) … #define IPW_DEBUG_SCAN(f, a...) … #define IPW_DEBUG_TRACE(f, a...) … #define IPW_DEBUG_RX(f, a...) … #define IPW_DEBUG_TX(f, a...) … #define IPW_DEBUG_ISR(f, a...) … #define IPW_DEBUG_MANAGEMENT(f, a...) … #define IPW_DEBUG_LED(f, a...) … #define IPW_DEBUG_WEP(f, a...) … #define IPW_DEBUG_HC(f, a...) … #define IPW_DEBUG_FRAG(f, a...) … #define IPW_DEBUG_FW(f, a...) … #define IPW_DEBUG_RF_KILL(f, a...) … #define IPW_DEBUG_DROP(f, a...) … #define IPW_DEBUG_IO(f, a...) … #define IPW_DEBUG_ORD(f, a...) … #define IPW_DEBUG_FW_INFO(f, a...) … #define IPW_DEBUG_NOTIF(f, a...) … #define IPW_DEBUG_STATE(f, a...) … #define IPW_DEBUG_ASSOC(f, a...) … #define IPW_DEBUG_STATS(f, a...) … #define IPW_DEBUG_MERGE(f, a...) … #define IPW_DEBUG_QOS(f, a...) … #include <linux/ctype.h> /* * Register bit definitions */ #define IPW_INTA_RW … #define IPW_INTA_MASK_R … #define IPW_INDIRECT_ADDR … #define IPW_INDIRECT_DATA … #define IPW_AUTOINC_ADDR … #define IPW_AUTOINC_DATA … #define IPW_RESET_REG … #define IPW_GP_CNTRL_RW … #define IPW_READ_INT_REGISTER … #define IPW_GP_CNTRL_BIT_INIT_DONE … #define IPW_REGISTER_DOMAIN1_END … #define IPW_SRAM_READ_INT_REGISTER … #define IPW_SHARED_LOWER_BOUND … #define IPW_INTERRUPT_AREA_LOWER_BOUND … #define IPW_NIC_SRAM_LOWER_BOUND … #define IPW_NIC_SRAM_UPPER_BOUND … #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER … #define IPW_GP_CNTRL_BIT_CLOCK_READY … #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY … /* * RESET Register Bit Indexes */ #define CBD_RESET_REG_PRINCETON_RESET … #define IPW_START_STANDBY … #define IPW_ACTIVITY_LED … #define IPW_ASSOCIATED_LED … #define IPW_OFDM_LED … #define IPW_RESET_REG_SW_RESET … #define IPW_RESET_REG_MASTER_DISABLED … #define IPW_RESET_REG_STOP_MASTER … #define IPW_GATE_ODMA … #define IPW_GATE_IDMA … #define IPW_ARC_KESHET_CONFIG … #define IPW_GATE_ADMA … #define IPW_CSR_CIS_UPPER_BOUND … #define IPW_DOMAIN_0_END … #define CLX_MEM_BAR_SIZE … /* Dino/baseband control registers bits */ #define DINO_ENABLE_SYSTEM … #define DINO_ENABLE_CS … #define DINO_RXFIFO_DATA … #define IPW_BASEBAND_CONTROL_STATUS … #define IPW_BASEBAND_TX_FIFO_WRITE … #define IPW_BASEBAND_RX_FIFO_READ … #define IPW_BASEBAND_CONTROL_STORE … #define IPW_INTERNAL_CMD_EVENT … #define IPW_BASEBAND_POWER_DOWN … #define IPW_MEM_HALT_AND_RESET … /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */ #define IPW_BIT_HALT_RESET_ON … #define IPW_BIT_HALT_RESET_OFF … #define CB_LAST_VALID … #define CB_INT_ENABLED … #define CB_VALID … #define CB_SRC_LE … #define CB_DEST_LE … #define CB_SRC_AUTOINC … #define CB_SRC_IO_GATED … #define CB_DEST_AUTOINC … #define CB_SRC_SIZE_LONG … #define CB_DEST_SIZE_LONG … /* DMA DEFINES */ #define DMA_CONTROL_SMALL_CB_CONST_VALUE … #define DMA_CB_STOP_AND_ABORT … #define DMA_CB_START … #define IPW_SHARED_SRAM_SIZE … #define IPW_SHARED_SRAM_DMA_CONTROL … #define CB_MAX_LENGTH … #define IPW_HOST_EEPROM_DATA_SRAM_SIZE … #define IPW_EEPROM_IMAGE_SIZE … /* DMA defs */ #define IPW_DMA_I_CURRENT_CB … #define IPW_DMA_O_CURRENT_CB … #define IPW_DMA_I_DMA_CONTROL … #define IPW_DMA_I_CB_BASE … #define IPW_TX_CMD_QUEUE_BD_BASE … #define IPW_TX_CMD_QUEUE_BD_SIZE … #define IPW_TX_QUEUE_0_BD_BASE … #define IPW_TX_QUEUE_0_BD_SIZE … #define IPW_TX_QUEUE_1_BD_BASE … #define IPW_TX_QUEUE_1_BD_SIZE … #define IPW_TX_QUEUE_2_BD_BASE … #define IPW_TX_QUEUE_2_BD_SIZE … #define IPW_TX_QUEUE_3_BD_BASE … #define IPW_TX_QUEUE_3_BD_SIZE … #define IPW_RX_BD_BASE … #define IPW_RX_BD_SIZE … #define IPW_RFDS_TABLE_LOWER … #define IPW_TX_CMD_QUEUE_READ_INDEX … #define IPW_TX_QUEUE_0_READ_INDEX … #define IPW_TX_QUEUE_1_READ_INDEX … #define IPW_TX_QUEUE_2_READ_INDEX … #define IPW_TX_QUEUE_3_READ_INDEX … #define IPW_RX_READ_INDEX … #define IPW_TX_CMD_QUEUE_WRITE_INDEX … #define IPW_TX_QUEUE_0_WRITE_INDEX … #define IPW_TX_QUEUE_1_WRITE_INDEX … #define IPW_TX_QUEUE_2_WRITE_INDEX … #define IPW_TX_QUEUE_3_WRITE_INDEX … #define IPW_RX_WRITE_INDEX … /* * EEPROM Related Definitions */ #define IPW_EEPROM_DATA_SRAM_ADDRESS … #define IPW_EEPROM_DATA_SRAM_SIZE … #define IPW_EEPROM_LOAD_DISABLE … #define IPW_EEPROM_DATA … #define IPW_EEPROM_UPPER_ADDRESS … #define IPW_STATION_TABLE_LOWER … #define IPW_STATION_TABLE_UPPER … #define IPW_REQUEST_ATIM … #define IPW_ATIM_SENT … #define IPW_WHO_IS_AWAKE … #define IPW_DURING_ATIM_WINDOW … #define MSB … #define LSB … #define WORD_TO_BYTE(_word) … #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) … /* EEPROM access by BYTE */ #define EEPROM_PME_CAPABILITY … #define EEPROM_MAC_ADDRESS … #define EEPROM_VERSION … #define EEPROM_NIC_TYPE … #define EEPROM_SKU_CAPABILITY … #define EEPROM_COUNTRY_CODE … #define EEPROM_IBSS_CHANNELS_BG … #define EEPROM_IBSS_CHANNELS_A … #define EEPROM_BSS_CHANNELS_BG … #define EEPROM_HW_VERSION … /* NIC type as found in the one byte EEPROM_NIC_TYPE offset */ #define EEPROM_NIC_TYPE_0 … #define EEPROM_NIC_TYPE_1 … #define EEPROM_NIC_TYPE_2 … #define EEPROM_NIC_TYPE_3 … #define EEPROM_NIC_TYPE_4 … /* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */ #define EEPROM_SKU_CAP_BT_CHANNEL_SIG … #define EEPROM_SKU_CAP_BT_PRIORITY … #define EEPROM_SKU_CAP_BT_OOB … #define FW_MEM_REG_LOWER_BOUND … #define FW_MEM_REG_EEPROM_ACCESS … #define IPW_EVENT_REG … #define EEPROM_BIT_SK … #define EEPROM_BIT_CS … #define EEPROM_BIT_DI … #define EEPROM_BIT_DO … #define EEPROM_CMD_READ … /* Interrupts masks */ #define IPW_INTA_NONE … #define IPW_INTA_BIT_RX_TRANSFER … #define IPW_INTA_BIT_STATUS_CHANGE … #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED … //Inta Bits for CF #define IPW_INTA_BIT_TX_CMD_QUEUE … #define IPW_INTA_BIT_TX_QUEUE_1 … #define IPW_INTA_BIT_TX_QUEUE_2 … #define IPW_INTA_BIT_TX_QUEUE_3 … #define IPW_INTA_BIT_TX_QUEUE_4 … #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE … #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN … #define IPW_INTA_BIT_POWER_DOWN … #define IPW_INTA_BIT_FW_INITIALIZATION_DONE … #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE … #define IPW_INTA_BIT_RF_KILL_DONE … #define IPW_INTA_BIT_FATAL_ERROR … #define IPW_INTA_BIT_PARITY_ERROR … /* Interrupts enabled at init time. */ #define IPW_INTA_MASK_ALL … /* FW event log definitions */ #define EVENT_ELEM_SIZE … #define EVENT_START_OFFSET … /* FW error log definitions */ #define ERROR_ELEM_SIZE … #define ERROR_START_OFFSET … /* TX power level (dbm) */ #define IPW_TX_POWER_MIN … #define IPW_TX_POWER_MAX … #define IPW_TX_POWER_DEFAULT … enum { … }; #define AUTH_OPEN … #define AUTH_SHARED_KEY … #define AUTH_LEAP … #define AUTH_IGNORE … #define HC_ASSOCIATE … #define HC_REASSOCIATE … #define HC_DISASSOCIATE … #define HC_IBSS_START … #define HC_IBSS_RECONF … #define HC_DISASSOC_QUIET … #define HC_QOS_SUPPORT_ASSOC … #define IPW_RATE_CAPABILITIES … #define IPW_RATE_CONNECT … /* * Rate values and masks */ #define IPW_TX_RATE_1MB … #define IPW_TX_RATE_2MB … #define IPW_TX_RATE_5MB … #define IPW_TX_RATE_6MB … #define IPW_TX_RATE_9MB … #define IPW_TX_RATE_11MB … #define IPW_TX_RATE_12MB … #define IPW_TX_RATE_18MB … #define IPW_TX_RATE_24MB … #define IPW_TX_RATE_36MB … #define IPW_TX_RATE_48MB … #define IPW_TX_RATE_54MB … #define IPW_ORD_TABLE_ID_MASK … #define IPW_ORD_TABLE_VALUE_MASK … #define IPW_ORD_TABLE_0_MASK … #define IPW_ORD_TABLE_1_MASK … #define IPW_ORD_TABLE_2_MASK … #define IPW_ORD_TABLE_3_MASK … #define IPW_ORD_TABLE_4_MASK … #define IPW_ORD_TABLE_5_MASK … #define IPW_ORD_TABLE_6_MASK … #define IPW_ORD_TABLE_7_MASK … /* * Table 0 Entries (all entries are 32 bits) */ enum { … }; #define IPW_RSSI_TO_DBM … /* Table 1 Entries */ enum { … }; /* * Table 2 Entries * * FW_VERSION: 16 byte string * FW_DATE: 16 byte string (only 14 bytes used) * UCODE_VERSION: 4 byte version code * UCODE_DATE: 5 bytes code code * ADDAPTER_MAC: 6 byte MAC address * RTC: 4 byte clock */ enum { … }; /* Table 3 */ enum { … }; /* Table 4 */ enum { … }; /* Table 5 */ enum { … }; /* Table 6 */ enum { … }; /* Table 7 */ enum { … }; #define IPW_ERROR_LOG … #define IPW_EVENT_LOG … #define IPW_ORDINALS_TABLE_LOWER … #define IPW_ORDINALS_TABLE_0 … #define IPW_ORDINALS_TABLE_1 … #define IPW_ORDINALS_TABLE_2 … #define IPW_MEM_FIXED_OVERRIDE … struct ipw_fixed_rate { … } __packed; #define IPW_INDIRECT_ADDR_MASK … struct host_cmd { … } __packed; /* XXX */ struct cmdlog_host_cmd { … } __packed; struct ipw_cmd_log { … }; /* SysConfig command parameters ... */ /* bt_coexistence param */ #define CFG_BT_COEXISTENCE_SIGNAL_CHNL … #define CFG_BT_COEXISTENCE_DEFER … #define CFG_BT_COEXISTENCE_KILL … #define CFG_BT_COEXISTENCE_WME_OVER_BT … #define CFG_BT_COEXISTENCE_OOB … /* clear-to-send to self param */ #define CFG_CTS_TO_ITSELF_ENABLED_MIN … #define CFG_CTS_TO_ITSELF_ENABLED_MAX … #define CFG_CTS_TO_ITSELF_ENABLED_DEF … /* Antenna diversity param (h/w can select best antenna, based on signal) */ #define CFG_SYS_ANTENNA_BOTH … #define CFG_SYS_ANTENNA_A … #define CFG_SYS_ANTENNA_B … #define CFG_SYS_ANTENNA_SLOW_DIV … #define IPW_MAX_CONFIG_RETRIES … #endif /* __ipw2200_h__ */
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