#ifndef __il_3945_h__
#define __il_3945_h__
#include <linux/pci.h>
#include <linux/kernel.h>
#include <net/ieee80211_radiotap.h>
extern const struct pci_device_id il3945_hw_card_ids[];
#include "common.h"
extern const struct il_ops il3945_ops;
#define IL3945_UCODE_API_MAX …
#define IL3945_UCODE_API_MIN …
#define IL3945_FW_PRE …
#define _IL3945_MODULE_FIRMWARE(api) …
#define IL3945_MODULE_FIRMWARE(api) …
#define IL_NOISE_MEAS_NOT_AVAILABLE …
extern struct il_mod_params il3945_mod_params;
struct il3945_rate_scale_data { … };
struct il3945_rs_sta { … };
struct il3945_sta_priv { … };
enum il3945_antenna { … };
#define DEFAULT_RTS_THRESHOLD …
#define MIN_RTS_THRESHOLD …
#define MAX_RTS_THRESHOLD …
#define MAX_MSDU_SIZE …
#define MAX_MPDU_SIZE …
#define DEFAULT_BEACON_INTERVAL …
#define DEFAULT_SHORT_RETRY_LIMIT …
#define DEFAULT_LONG_RETRY_LIMIT …
#define IL_TX_FIFO_AC0 …
#define IL_TX_FIFO_AC1 …
#define IL_TX_FIFO_AC2 …
#define IL_TX_FIFO_AC3 …
#define IL_TX_FIFO_HCCA_1 …
#define IL_TX_FIFO_HCCA_2 …
#define IL_TX_FIFO_NONE …
#define IEEE80211_DATA_LEN …
#define IEEE80211_4ADDR_LEN …
#define IEEE80211_HLEN …
#define IEEE80211_FRAME_LEN …
struct il3945_frame { … };
#define SUP_RATE_11A_MAX_NUM_CHANNELS …
#define SUP_RATE_11B_MAX_NUM_CHANNELS …
#define SUP_RATE_11G_MAX_NUM_CHANNELS …
#define IL_SUPPORTED_RATES_IE_LEN …
#define SCAN_INTERVAL …
#define MAX_TID_COUNT …
#define IL_INVALID_RATE …
#define IL_INVALID_VALUE …
#define STA_PS_STATUS_WAKE …
#define STA_PS_STATUS_SLEEP …
struct il3945_ibss_seq { … };
#define IL_RX_HDR(x) …
#define IL_RX_END(x) …
#define IL_RX_STATS(x) …
#define IL_RX_DATA(x) …
int il3945_calc_db_from_ratio(int sig_ratio);
void il3945_rx_replenish(void *data);
void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
unsigned int il3945_fill_beacon_frame(struct il_priv *il,
struct ieee80211_hdr *hdr, int left);
int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, char **buf,
bool display);
void il3945_dump_nic_error_log(struct il_priv *il);
void il3945_hw_handler_setup(struct il_priv *il);
void il3945_hw_setup_deferred_work(struct il_priv *il);
void il3945_hw_cancel_deferred_work(struct il_priv *il);
int il3945_hw_rxq_stop(struct il_priv *il);
int il3945_hw_set_hw_params(struct il_priv *il);
int il3945_hw_nic_init(struct il_priv *il);
int il3945_hw_nic_stop_master(struct il_priv *il);
void il3945_hw_txq_ctx_free(struct il_priv *il);
void il3945_hw_txq_ctx_stop(struct il_priv *il);
int il3945_hw_nic_reset(struct il_priv *il);
int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
dma_addr_t addr, u16 len, u8 reset, u8 pad);
void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
int il3945_hw_get_temperature(struct il_priv *il);
int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
struct il3945_frame *frame, u8 rate);
void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
struct ieee80211_tx_info *info,
struct ieee80211_hdr *hdr, int sta_id);
int il3945_hw_reg_send_txpower(struct il_priv *il);
int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);
void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
void il3945_disable_events(struct il_priv *il);
int il4965_get_temperature(const struct il_priv *il);
void il3945_post_associate(struct il_priv *il);
void il3945_config_ap(struct il_priv *il);
int il3945_commit_rxon(struct il_priv *il);
u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid);
__le32 il3945_get_antenna_flags(const struct il_priv *il);
int il3945_init_hw_rate_table(struct il_priv *il);
void il3945_reg_txpower_periodic(struct il_priv *il);
int il3945_txpower_set_from_eeprom(struct il_priv *il);
int il3945_rs_next_rate(struct il_priv *il, int rate);
int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
void il3945_post_scan(struct il_priv *il);
extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];
#define IL39_RSSI_OFFSET …
#define EEPROM_SKU_CAP_OP_MODE_MRC …
struct il3945_eeprom_txpower_sample { … } __packed;
struct il3945_eeprom_txpower_group { … } __packed;
struct il3945_eeprom_temperature_corr { … } __packed;
struct il3945_eeprom { … } __packed;
#define IL3945_EEPROM_IMG_SIZE …
#define PCI_CFG_REV_ID_BIT_BASIC_SKU …
#define PCI_CFG_REV_ID_BIT_RTP …
#define IL39_NUM_QUEUES …
#define IL39_CMD_QUEUE_NUM …
#define IL_DEFAULT_TX_RETRY …
#define RFD_SIZE …
#define NUM_TFD_CHUNKS …
#define TFD_CTL_COUNT_SET(n) …
#define TFD_CTL_COUNT_GET(ctl) …
#define TFD_CTL_PAD_SET(n) …
#define TFD_CTL_PAD_GET(ctl) …
#define IL39_RTC_INST_LOWER_BOUND …
#define IL39_RTC_INST_UPPER_BOUND …
#define IL39_RTC_DATA_LOWER_BOUND …
#define IL39_RTC_DATA_UPPER_BOUND …
#define IL39_RTC_INST_SIZE …
#define IL39_RTC_DATA_SIZE …
#define IL39_MAX_INST_SIZE …
#define IL39_MAX_DATA_SIZE …
#define IL39_MAX_BSM_SIZE …
static inline int
il3945_hw_valid_rtc_data_addr(u32 addr)
{ … }
struct il3945_shared { … } __packed;
#define FH39_MEM_LOWER_BOUND …
#define FH39_MEM_UPPER_BOUND …
#define FH39_CBCC_TBL …
#define FH39_TFDB_TBL …
#define FH39_RCSR_TBL …
#define FH39_RSSR_TBL …
#define FH39_TCSR_TBL …
#define FH39_TSSR_TBL …
#define FH39_TFDB(_ch, buf) …
#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) …
#define FH39_CBCC(_ch) …
#define FH39_CBCC_CTRL(_ch) …
#define FH39_CBCC_BASE(_ch) …
#define FH39_RCSR(_ch) …
#define FH39_RCSR_CONFIG(_ch) …
#define FH39_RCSR_RBD_BASE(_ch) …
#define FH39_RCSR_WPTR(_ch) …
#define FH39_RCSR_RPTR_ADDR(_ch) …
#define FH39_RSCSR_CHNL0_WPTR …
#define FH39_RSSR_CTRL …
#define FH39_RSSR_STATUS …
#define FH39_TCSR(_ch) …
#define FH39_TCSR_CONFIG(_ch) …
#define FH39_TCSR_CREDIT(_ch) …
#define FH39_TCSR_BUFF_STTS(_ch) …
#define FH39_TSSR_CBB_BASE …
#define FH39_TSSR_MSG_CONFIG …
#define FH39_TSSR_TX_STATUS …
#define FH39_SRVC_CHNL …
#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE …
#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH …
#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN …
#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE …
#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE …
#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 …
#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST …
#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH …
#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF …
#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER …
#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL …
#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL …
#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD …
#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT …
#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE …
#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE …
#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID …
#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH …
#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH …
#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) …
#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) …
#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) …
#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE …
struct il3945_tfd_tb { … } __packed;
struct il3945_tfd { … } __packed;
#ifdef CONFIG_IWLEGACY_DEBUGFS
extern const struct il_debugfs_ops il3945_debugfs_ops;
#endif
#endif