/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (C) 2005-2014, 2018-2024 Intel Corporation * Copyright (C) 2013-2014 Intel Mobile Communications GmbH * Copyright (C) 2016 Intel Deutschland GmbH */ #ifndef __iwl_csr_h__ #define __iwl_csr_h__ /* * CSR (control and status registers) * * CSR registers are mapped directly into PCI bus space, and are accessible * whenever platform supplies power to device, even when device is in * low power states due to driver-invoked device resets * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. * * Use iwl_write32() and iwl_read32() family to access these registers; * these provide simple PCI bus access, without waking up the MAC. * Do not use iwl_write_direct32() family for these registers; * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. * The MAC (uCode processor, etc.) does not need to be powered up for accessing * the CSR registers. * * NOTE: Device does need to be awake in order to read this memory * via CSR_EEPROM and CSR_OTP registers */ #define CSR_BASE … #define CSR_HW_IF_CONFIG_REG … #define CSR_INT_COALESCING … #define CSR_INT … #define CSR_INT_MASK … #define CSR_FH_INT_STATUS … #define CSR_GPIO_IN … #define CSR_RESET … #define CSR_GP_CNTRL … #define CSR_FUNC_SCRATCH … /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ #define CSR_INT_PERIODIC_REG … /* * Hardware revision info * Bit fields: * 31-16: Reserved * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D * 1-0: "Dash" (-) value, as in A-1, etc. */ #define CSR_HW_REV … /* * RF ID revision info * Bit fields: * 31:24: Reserved (set to 0x0) * 23:12: Type * 11:8: Step (A - 0x0, B - 0x1, etc) * 7:4: Dash * 3:0: Flavor */ #define CSR_HW_RF_ID … /* * EEPROM and OTP (one-time-programmable) memory reads * * NOTE: Device must be awake, initialized via apm_ops.init(), * in order to read. */ #define CSR_EEPROM_REG … #define CSR_EEPROM_GP … #define CSR_OTP_GP_REG … #define CSR_GIO_REG … #define CSR_GP_UCODE_REG … #define CSR_GP_DRIVER_REG … /* * UCODE-DRIVER GP (general purpose) mailbox registers. * SET/CLR registers set/clear bit(s) if "1" is written. */ #define CSR_UCODE_DRV_GP1 … #define CSR_UCODE_DRV_GP1_SET … #define CSR_UCODE_DRV_GP1_CLR … #define CSR_UCODE_DRV_GP2 … #define CSR_MBOX_SET_REG … #define CSR_LED_REG … #define CSR_DRAM_INT_TBL_REG … #define CSR_MAC_SHADOW_REG_CTRL … #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE … #define CSR_MAC_SHADOW_REG_CTL2 … #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE … /* LTR control (since IWL_DEVICE_FAMILY_22000) */ #define CSR_LTR_LONG_VAL_AD … #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ … #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE … #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL … #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ … #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE … #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL … #define CSR_LTR_LONG_VAL_AD_SCALE_USEC … #define CSR_LTR_LAST_MSG … /* GIO Chicken Bits (PCI Express bus link power management) */ #define CSR_GIO_CHICKEN_BITS … #define CSR_IPC_SLEEP_CONTROL … #define CSR_IPC_SLEEP_CONTROL_SUSPEND … #define CSR_IPC_SLEEP_CONTROL_RESUME … /* Doorbell - since Bz * connected to UREG_DOORBELL_TO_ISR6 (lower 16 bits only) */ #define CSR_DOORBELL_VECTOR … /* host chicken bits */ #define CSR_HOST_CHICKEN … #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME … /* Analog phase-lock-loop configuration */ #define CSR_ANA_PLL_CFG … /* * CSR HW resources monitor registers */ #define CSR_MONITOR_CFG_REG … #define CSR_MONITOR_STATUS_REG … #define CSR_MONITOR_XTAL_RESOURCES … /* * CSR Hardware Revision Workaround Register. Indicates hardware rev; * "step" determines CCK backoff for txpower calculation. * See also CSR_HW_REV register. * Bit fields: * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step * 1-0: "Dash" (-) value, as in C-1, etc. */ #define CSR_HW_REV_WA_REG … #define CSR_DBG_HPET_MEM_REG … #define CSR_DBG_LINK_PWR_MGMT_REG … /* * Scratch register initial configuration - this is set on init, and read * during a error FW error. */ #define CSR_FUNC_SCRATCH_INIT_VALUE … /* Bits for CSR_HW_IF_CONFIG_REG */ #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH … #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM … #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER … #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI … #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI … #define CSR_HW_IF_CONFIG_REG_D3_DEBUG … #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE … #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH … #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP … #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH … #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP … #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER … #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE … #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH … #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP … #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A … #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM … #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY … #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE … #define CSR_HW_IF_CONFIG_REG_PREPARE … #define CSR_HW_IF_CONFIG_REG_ENABLE_PME … #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE … #define CSR_MBOX_SET_REG_OS_ALIVE … #define CSR_INT_PERIODIC_DIS … #define CSR_INT_PERIODIC_ENA … /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), * acknowledged (reset) by host writing "1" to flagged bits. */ #define CSR_INT_BIT_FH_RX … #define CSR_INT_BIT_HW_ERR … #define CSR_INT_BIT_RX_PERIODIC … #define CSR_INT_BIT_FH_TX … #define CSR_INT_BIT_SCD … #define CSR_INT_BIT_SW_ERR … #define CSR_INT_BIT_RF_KILL … #define CSR_INT_BIT_CT_KILL … #define CSR_INT_BIT_SW_RX … #define CSR_INT_BIT_WAKEUP … #define CSR_INT_BIT_ALIVE … #define CSR_INI_SET_MASK … /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ #define CSR_FH_INT_BIT_ERR … #define CSR_FH_INT_BIT_HI_PRIOR … #define CSR_FH_INT_BIT_RX_CHNL1 … #define CSR_FH_INT_BIT_RX_CHNL0 … #define CSR_FH_INT_BIT_TX_CHNL1 … #define CSR_FH_INT_BIT_TX_CHNL0 … #define CSR_FH_INT_RX_MASK … #define CSR_FH_INT_TX_MASK … /* GPIO */ #define CSR_GPIO_IN_BIT_AUX_POWER … #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC … #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC … /* RESET */ #define CSR_RESET_REG_FLAG_NEVO_RESET … #define CSR_RESET_REG_FLAG_FORCE_NMI … #define CSR_RESET_REG_FLAG_SW_RESET … #define CSR_RESET_REG_FLAG_MASTER_DISABLED … #define CSR_RESET_REG_FLAG_STOP_MASTER … #define CSR_RESET_LINK_PWR_MGMT_DISABLED … /* * GP (general purpose) CONTROL REGISTER * Bit fields: * 27: HW_RF_KILL_SW * Indicates state of (platform's) hardware RF-Kill switch * 26-24: POWER_SAVE_TYPE * Indicates current power-saving mode: * 000 -- No power saving * 001 -- MAC power-down * 010 -- PHY (radio) power-down * 011 -- Error * 10: XTAL ON request * 9-6: SYS_CONFIG * Indicates current system configuration, reflecting pins on chip * as forced high/low by device circuit board. * 4: GOING_TO_SLEEP * Indicates MAC is entering a power-saving sleep power-down. * Not a good time to access device-internal resources. * 3: MAC_ACCESS_REQ * Host sets this to request and maintain MAC wakeup, to allow host * access to device-internal resources. Host must wait for * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR * device registers. * 2: INIT_DONE * Host sets this to put device into fully operational D0 power mode. * Host resets this after SW_RESET to put device into low power mode. * 0: MAC_CLOCK_READY * Indicates MAC (ucode processor, etc.) is powered up and can run. * Internal resources are accessible. * NOTE: This does not indicate that the processor is actually running. * NOTE: This does not indicate that device has completed * init or post-power-down restore of internal SRAM memory. * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that * SRAM is restored and uCode is in normal operation mode. * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and * do not need to save/restore it. * NOTE: After device reset, this bit remains "0" until host sets * INIT_DONE */ #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY … #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE … #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ … #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP … #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON … #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN … #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE … #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN … #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW … /* From Bz we use these instead during init/reset flow */ #define CSR_GP_CNTRL_REG_FLAG_MAC_INIT … #define CSR_GP_CNTRL_REG_FLAG_ROM_START … #define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS … #define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ … #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS … #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ … #define CSR_GP_CNTRL_REG_FLAG_SW_RESET … /* HW REV */ #define CSR_HW_REV_STEP_DASH(_val) … #define CSR_HW_REV_TYPE(_val) … /* HW RFID */ #define CSR_HW_RFID_FLAVOR(_val) … #define CSR_HW_RFID_DASH(_val) … #define CSR_HW_RFID_STEP(_val) … #define CSR_HW_RFID_TYPE(_val) … #define CSR_HW_RFID_IS_CDB(_val) … #define CSR_HW_RFID_IS_JACKET(_val) … /* hw_rev values */ enum { … }; #define CSR_HW_REV_TYPE_MSK … #define CSR_HW_REV_TYPE_5300 … #define CSR_HW_REV_TYPE_5350 … #define CSR_HW_REV_TYPE_5100 … #define CSR_HW_REV_TYPE_5150 … #define CSR_HW_REV_TYPE_1000 … #define CSR_HW_REV_TYPE_6x00 … #define CSR_HW_REV_TYPE_6x50 … #define CSR_HW_REV_TYPE_6150 … #define CSR_HW_REV_TYPE_6x05 … #define CSR_HW_REV_TYPE_6x30 … #define CSR_HW_REV_TYPE_6x35 … #define CSR_HW_REV_TYPE_2x30 … #define CSR_HW_REV_TYPE_2x00 … #define CSR_HW_REV_TYPE_105 … #define CSR_HW_REV_TYPE_135 … #define CSR_HW_REV_TYPE_3160 … #define CSR_HW_REV_TYPE_7265D … #define CSR_HW_REV_TYPE_NONE … #define CSR_HW_REV_TYPE_QNJ … #define CSR_HW_REV_TYPE_QNJ_B0 … #define CSR_HW_REV_TYPE_QU_B0 … #define CSR_HW_REV_TYPE_QU_C0 … #define CSR_HW_REV_TYPE_QUZ … #define CSR_HW_REV_TYPE_HR_CDB … #define CSR_HW_REV_TYPE_SO … #define CSR_HW_REV_TYPE_TY … /* RF_ID value */ #define CSR_HW_RF_ID_TYPE_JF … #define CSR_HW_RF_ID_TYPE_HR … #define CSR_HW_RF_ID_TYPE_HR1 … #define CSR_HW_RF_ID_TYPE_HRCDB … #define CSR_HW_RF_ID_TYPE_GF … #define CSR_HW_RF_ID_TYPE_GF4 … #define CSR_HW_RF_ID_TYPE_MS … #define CSR_HW_RF_ID_TYPE_FM … #define CSR_HW_RF_ID_TYPE_WP … /* HW_RF CHIP STEP */ #define CSR_HW_RF_STEP(_val) … /* EEPROM REG */ #define CSR_EEPROM_REG_READ_VALID_MSK … #define CSR_EEPROM_REG_BIT_CMD … #define CSR_EEPROM_REG_MSK_ADDR … #define CSR_EEPROM_REG_MSK_DATA … /* EEPROM GP */ #define CSR_EEPROM_GP_VALID_MSK … #define CSR_EEPROM_GP_IF_OWNER_MSK … #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP … #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP … #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K … #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K … /* One-time-programmable memory general purpose reg */ #define CSR_OTP_GP_REG_DEVICE_SELECT … #define CSR_OTP_GP_REG_OTP_ACCESS_MODE … #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK … #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK … /* GP REG */ #define CSR_GP_REG_POWER_SAVE_STATUS_MSK … #define CSR_GP_REG_NO_POWER_SAVE … #define CSR_GP_REG_MAC_POWER_SAVE … #define CSR_GP_REG_PHY_POWER_SAVE … #define CSR_GP_REG_POWER_SAVE_ERROR … /* CSR GIO */ #define CSR_GIO_REG_VAL_L0S_DISABLED … /* * UCODE-DRIVER GP (general purpose) mailbox register 1 * Host driver and uCode write and/or read this register to communicate with * each other. * Bit fields: * 4: UCODE_DISABLE * Host sets this to request permanent halt of uCode, same as * sending CARD_STATE command with "halt" bit set. * 3: CT_KILL_EXIT * Host sets this to request exit from CT_KILL state, i.e. host thinks * device temperature is low enough to continue normal operation. * 2: CMD_BLOCKED * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) * to release uCode to clear all Tx and command queues, enter * unassociated mode, and power down. * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. * 1: SW_BIT_RFKILL * Host sets this when issuing CARD_STATE command to request * device sleep. * 0: MAC_SLEEP * uCode sets this when preparing a power-saving power-down. * uCode resets this when power-up is complete and SRAM is sane. * NOTE: device saves internal SRAM data to host when powering down, * and must restore this data after powering back up. * MAC_SLEEP is the best indication that restore is complete. * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and * do not need to save/restore it. */ #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP … #define CSR_UCODE_SW_BIT_RFKILL … #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED … #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT … #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE … /* GP Driver */ #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK … #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB … #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB … #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA … #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 … #define CSR_GP_DRIVER_REG_BIT_6050_1x2 … #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER … /* GIO Chicken Bits (PCI Express bus link power management) */ #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX … #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER … /* LED */ #define CSR_LED_BSM_CTRL_MSK … #define CSR_LED_REG_TURN_ON … #define CSR_LED_REG_TURN_OFF … /* ANA_PLL */ #define CSR50_ANA_PLL_CFG_VAL … /* HPET MEM debug */ #define CSR_DBG_HPET_MEM_REG_VAL … /* DRAM INT TABLE */ #define CSR_DRAM_INT_TBL_ENABLE … #define CSR_DRAM_INIT_TBL_WRITE_POINTER … #define CSR_DRAM_INIT_TBL_WRAP_CHECK … /* * SHR target access (Shared block memory space) * * Shared internal registers can be accessed directly from PCI bus through SHR * arbiter without need for the MAC HW to be powered up. This is possible due to * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. * * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW * need not be powered up so no "grab inc access" is required. */ /* * Registers for accessing shared registers (e.g. SHR_APMG_GP1, * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), * first, write to the control register: * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. * * To write the register, first, write to the data register * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) */ #define HEEP_CTRL_WRD_PCIEX_CTRL_REG … #define HEEP_CTRL_WRD_PCIEX_DATA_REG … /* * HBUS (Host-side Bus) * * HBUS registers are mapped directly into PCI bus space, but are used * to indirectly access device's internal memory or registers that * may be powered-down. * * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ * to make sure the MAC (uCode processor, etc.) is powered up for accessing * internal resources. * * Do not use iwl_write32()/iwl_read32() family to access these registers; * these provide only simple PCI bus access, without waking up the MAC. */ #define HBUS_BASE … /* * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM * structures, error log, event log, verifying uCode load). * First write to address register, then read from or write to data register * to complete the job. Once the address register is set up, accesses to * data registers auto-increment the address by one dword. * Bit usage for address registers (read or write): * 0-31: memory address within device */ #define HBUS_TARG_MEM_RADDR … #define HBUS_TARG_MEM_WADDR … #define HBUS_TARG_MEM_WDAT … #define HBUS_TARG_MEM_RDAT … /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ #define HBUS_TARG_MBX_C … #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED … /* * Registers for accessing device's internal peripheral registers * (e.g. SCD, BSM, etc.). First write to address register, * then read from or write to data register to complete the job. * Bit usage for address registers (read or write): * 0-15: register address (offset) within device * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) */ #define HBUS_TARG_PRPH_WADDR … #define HBUS_TARG_PRPH_RADDR … #define HBUS_TARG_PRPH_WDAT … #define HBUS_TARG_PRPH_RDAT … /* Used to enable DBGM */ #define HBUS_TARG_TEST_REG … /* * Per-Tx-queue write pointer (index, really!) * Indicates index to next TFD that driver will fill (1 past latest filled). * Bit usage: * 0-7: queue write index * 11-8: queue selector */ #define HBUS_TARG_WRPTR … /* This register is common for Tx and Rx, Rx queues start from 512 */ #define HBUS_TARG_WRPTR_Q_SHIFT … #define HBUS_TARG_WRPTR_RX_Q(q) … /********************************************************** * CSR values **********************************************************/ /* * host interrupt timeout value * used with setting interrupt coalescing timer * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit * * default interrupt coalescing timer is 64 x 32 = 2048 usecs */ #define IWL_HOST_INT_TIMEOUT_MAX … #define IWL_HOST_INT_TIMEOUT_DEF … #define IWL_HOST_INT_TIMEOUT_MIN … #define IWL_HOST_INT_OPER_MODE … /***************************************************************************** * 7000/3000 series SHR DTS addresses * *****************************************************************************/ /* Diode Results Register Structure: */ enum dtd_diode_reg { … }; /***************************************************************************** * MSIX related registers * *****************************************************************************/ #define CSR_MSIX_BASE … #define CSR_MSIX_FH_INT_CAUSES_AD … #define CSR_MSIX_FH_INT_MASK_AD … #define CSR_MSIX_HW_INT_CAUSES_AD … #define CSR_MSIX_HW_INT_MASK_AD … #define CSR_MSIX_AUTOMASK_ST_AD … #define CSR_MSIX_RX_IVAR_AD_REG … #define CSR_MSIX_IVAR_AD_REG … #define CSR_MSIX_PENDING_PBA_AD … #define CSR_MSIX_RX_IVAR(cause) … #define CSR_MSIX_IVAR(cause) … #define MSIX_FH_INT_CAUSES_Q(q) … /* * Causes for the FH register interrupts */ enum msix_fh_int_causes { … }; /* The low 16 bits are for rx data queue indication */ #define MSIX_FH_INT_CAUSES_DATA_QUEUE … /* * Causes for the HW register interrupts */ enum msix_hw_int_causes { … }; #define MSIX_MIN_INTERRUPT_VECTORS … #define MSIX_AUTO_CLEAR_CAUSE … #define MSIX_NON_AUTO_CLEAR_CAUSE … /***************************************************************************** * HW address related registers * *****************************************************************************/ #define CSR_ADDR_BASE(trans) … #define CSR_MAC_ADDR0_OTP(trans) … #define CSR_MAC_ADDR1_OTP(trans) … #define CSR_MAC_ADDR0_STRAP(trans) … #define CSR_MAC_ADDR1_STRAP(trans) … #endif /* !__iwl_csr_h__ */
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