/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (C) 2005-2014, 2018-2024 Intel Corporation * Copyright (C) 2013-2015 Intel Mobile Communications GmbH * Copyright (C) 2016 Intel Deutschland GmbH */ #ifndef __iwl_prph_h__ #define __iwl_prph_h__ #include <linux/bitfield.h> /* * Registers in this file are internal, not PCI bus memory mapped. * Driver accesses these via HBUS_TARG_PRPH_* registers. */ #define PRPH_BASE … #define PRPH_END … /* APMG (power management) constants */ #define APMG_BASE … #define APMG_CLK_CTRL_REG … #define APMG_CLK_EN_REG … #define APMG_CLK_DIS_REG … #define APMG_PS_CTRL_REG … #define APMG_PCIDEV_STT_REG … #define APMG_RFKILL_REG … #define APMG_RTC_INT_STT_REG … #define APMG_RTC_INT_MSK_REG … #define APMG_DIGITAL_SVR_REG … #define APMG_ANALOG_SVR_REG … #define APMS_CLK_VAL_MRB_FUNC_MODE … #define APMG_CLK_VAL_DMA_CLK_RQT … #define APMG_CLK_VAL_BSM_CLK_RQT … #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS … #define APMG_PS_CTRL_VAL_RESET_REQ … #define APMG_PS_CTRL_MSK_PWR_SRC … #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN … #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX … #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK … #define APMG_SVR_DIGITAL_VOLTAGE_1_32 … #define APMG_PCIDEV_STT_VAL_PERSIST_DIS … #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS … #define APMG_PCIDEV_STT_VAL_WAKE_ME … #define APMG_RTC_INT_STT_RFKILL … /* Device system time */ #define DEVICE_SYSTEM_TIME_REG … /* Device NMI register and value for 8000 family and lower hw's */ #define DEVICE_SET_NMI_REG … #define DEVICE_SET_NMI_VAL_DRV … /* Device NMI register and value for 9000 family and above hw's */ #define UREG_NIC_SET_NMI_DRIVER … #define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER … #define UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE … /* Shared registers (0x0..0x3ff, via target indirect or periphery */ #define SHR_BASE … /* Shared GP1 register */ #define SHR_APMG_GP1_REG … #define SHR_APMG_GP1_REG_PRPH … #define SHR_APMG_GP1_WF_XTAL_LP_EN … #define SHR_APMG_GP1_CHICKEN_BIT_SELECT … /* Shared DL_CFG register */ #define SHR_APMG_DL_CFG_REG … #define SHR_APMG_DL_CFG_REG_PRPH … #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK … #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL … #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP … /* Shared APMG_XTAL_CFG register */ #define SHR_APMG_XTAL_CFG_REG … #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ … /* * Device reset for family 8000 * write to bit 24 in order to reset the CPU */ #define RELEASE_CPU_RESET … #define RELEASE_CPU_RESET_BIT … /***************************************************************************** * 7000/3000 series SHR DTS addresses * *****************************************************************************/ #define SHR_MISC_WFM_DTS_EN … #define DTSC_CFG_MODE … #define DTSC_VREF_AVG … #define DTSC_VREF5_AVG … #define DTSC_CFG_MODE_PERIODIC … #define DTSC_PTAT_AVG … /* * Tx Scheduler * * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in * host DRAM. It steers each frame's Tx command (which contains the frame * data) into one of up to 7 prioritized Tx DMA FIFO channels within the * device. A queue maps to only one (selectable by driver) Tx DMA channel, * but one DMA channel may take input from several queues. * * Tx DMA FIFOs have dedicated purposes. * * For 5000 series and up, they are used differently * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): * * 0 -- EDCA BK (background) frames, lowest priority * 1 -- EDCA BE (best effort) frames, normal priority * 2 -- EDCA VI (video) frames, higher priority * 3 -- EDCA VO (voice) and management frames, highest priority * 4 -- unused * 5 -- unused * 6 -- unused * 7 -- Commands * * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. * In addition, driver can map the remaining queues to Tx DMA/FIFO * channels 0-3 to support 11n aggregation via EDCA DMA channels. * * The driver sets up each queue to work in one of two modes: * * 1) Scheduler-Ack, in which the scheduler automatically supports a * block-ack (BA) window of up to 64 TFDs. In this mode, each queue * contains TFDs for a unique combination of Recipient Address (RA) * and Traffic Identifier (TID), that is, traffic of a given * Quality-Of-Service (QOS) priority, destined for a single station. * * In scheduler-ack mode, the scheduler keeps track of the Tx status of * each frame within the BA window, including whether it's been transmitted, * and whether it's been acknowledged by the receiving station. The device * automatically processes block-acks received from the receiving STA, * and reschedules un-acked frames to be retransmitted (successful * Tx completion may end up being out-of-order). * * The driver must maintain the queue's Byte Count table in host DRAM * for this mode. * This mode does not support fragmentation. * * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. * The device may automatically retry Tx, but will retry only one frame * at a time, until receiving ACK from receiving station, or reaching * retry limit and giving up. * * The command queue (#4/#9) must use this mode! * This mode does not require use of the Byte Count table in host DRAM. * * Driver controls scheduler operation via 3 means: * 1) Scheduler registers * 2) Shared scheduler data base in internal SRAM * 3) Shared data in host DRAM * * Initialization: * * When loading, driver should allocate memory for: * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory * (1024 bytes for each queue). * * After receiving "Alive" response from uCode, driver must initialize * the scheduler (especially for queue #4/#9, the command queue, otherwise * the driver can't issue commands!): */ #define SCD_MEM_LOWER_BOUND … /* * Max Tx window size is the max number of contiguous TFDs that the scheduler * can keep track of at one time when creating block-ack chains of frames. * Note that "64" matches the number of ack bits in a block-ack packet. */ #define SCD_WIN_SIZE … #define SCD_FRAME_LIMIT … #define SCD_TXFIFO_POS_TID … #define SCD_TXFIFO_POS_RA … #define SCD_QUEUE_RA_TID_MAP_RATID_MSK … /* agn SCD */ #define SCD_QUEUE_STTS_REG_POS_TXF … #define SCD_QUEUE_STTS_REG_POS_ACTIVE … #define SCD_QUEUE_STTS_REG_POS_WSL … #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN … #define SCD_QUEUE_STTS_REG_MSK … #define SCD_QUEUE_CTX_REG1_CREDIT … #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT … #define SCD_QUEUE_CTX_REG1_VAL(_n, _v) … #define SCD_QUEUE_CTX_REG2_WIN_SIZE … #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT … #define SCD_QUEUE_CTX_REG2_VAL(_n, _v) … #define SCD_GP_CTRL_ENABLE_31_QUEUES … #define SCD_GP_CTRL_AUTO_ACTIVE_MODE … /* Context Data */ #define SCD_CONTEXT_MEM_LOWER_BOUND … #define SCD_CONTEXT_MEM_UPPER_BOUND … /* Tx status */ #define SCD_TX_STTS_MEM_LOWER_BOUND … #define SCD_TX_STTS_MEM_UPPER_BOUND … /* Translation Data */ #define SCD_TRANS_TBL_MEM_LOWER_BOUND … #define SCD_TRANS_TBL_MEM_UPPER_BOUND … #define SCD_CONTEXT_QUEUE_OFFSET(x) … #define SCD_TX_STTS_QUEUE_OFFSET(x) … #define SCD_TRANS_TBL_OFFSET_QUEUE(x) … #define SCD_BASE … #define SCD_SRAM_BASE_ADDR … #define SCD_DRAM_BASE_ADDR … #define SCD_AIT … #define SCD_TXFACT … #define SCD_ACTIVE … #define SCD_QUEUECHAIN_SEL … #define SCD_CHAINEXT_EN … #define SCD_AGGR_SEL … #define SCD_INTERRUPT_MASK … #define SCD_GP_CTRL … #define SCD_EN_CTRL … /*********************** END TX SCHEDULER *************************************/ /* Oscillator clock */ #define OSC_CLK … #define OSC_CLK_FORCE_CONTROL … #define FH_UCODE_LOAD_STATUS … /* * Replacing FH_UCODE_LOAD_STATUS * This register is writen by driver and is read by uCode during boot flow. * Note this address is cleared after MAC reset. */ #define UREG_UCODE_LOAD_STATUS … #define UREG_CPU_INIT_RUN … #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR … #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR … #define LMPM_SECURE_CPU1_HDR_MEM_SPACE … #define LMPM_SECURE_CPU2_HDR_MEM_SPACE … #define LMAC2_PRPH_OFFSET … /* Rx FIFO */ #define RXF_SIZE_ADDR … #define RXF_RD_D_SPACE … #define RXF_RD_WR_PTR … #define RXF_RD_RD_PTR … #define RXF_RD_FENCE_PTR … #define RXF_SET_FENCE_MODE … #define RXF_LD_WR2FENCE … #define RXF_FIFO_RD_FENCE_INC … #define RXF_SIZE_BYTE_CND_POS … #define RXF_SIZE_BYTE_CNT_MSK … #define RXF_DIFF_FROM_PREV … #define RXF2C_DIFF_FROM_PREV … #define RXF_LD_FENCE_OFFSET_ADDR … #define RXF_FIFO_RD_FENCE_ADDR … /* Tx FIFO */ #define TXF_FIFO_ITEM_CNT … #define TXF_WR_PTR … #define TXF_RD_PTR … #define TXF_FENCE_PTR … #define TXF_LOCK_FENCE … #define TXF_LARC_NUM … #define TXF_READ_MODIFY_DATA … #define TXF_READ_MODIFY_ADDR … /* UMAC Internal Tx Fifo */ #define TXF_CPU2_FIFO_ITEM_CNT … #define TXF_CPU2_WR_PTR … #define TXF_CPU2_RD_PTR … #define TXF_CPU2_FENCE_PTR … #define TXF_CPU2_LOCK_FENCE … #define TXF_CPU2_NUM … #define TXF_CPU2_READ_MODIFY_DATA … #define TXF_CPU2_READ_MODIFY_ADDR … /* Radio registers access */ #define RSP_RADIO_CMD … #define RSP_RADIO_RDDAT … #define RADIO_RSP_ADDR_POS … #define RADIO_RSP_RD_CMD … /* LTR control (Qu only) */ #define HPM_MAC_LTR_CSR … #define HPM_MAC_LRT_ENABLE_ALL … /* also uses CSR_LTR_* for values */ #define HPM_UMAC_LTR … /* FW monitor */ #define MON_BUFF_SAMPLE_CTL … #define MON_BUFF_BASE_ADDR … #define MON_BUFF_END_ADDR … #define MON_BUFF_WRPTR … #define MON_BUFF_CYCLE_CNT … /* FW monitor family 8000 and on */ #define MON_BUFF_BASE_ADDR_VER2 … #define MON_BUFF_END_ADDR_VER2 … #define MON_BUFF_WRPTR_VER2 … #define MON_BUFF_CYCLE_CNT_VER2 … #define MON_BUFF_SHIFT_VER2 … /* FW monitor familiy AX210 and on */ #define DBGC_CUR_DBGBUF_BASE_ADDR_LSB … #define DBGC_CUR_DBGBUF_BASE_ADDR_MSB … #define DBGC_CUR_DBGBUF_STATUS … #define DBGC_DBGBUF_WRAP_AROUND … #define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK … #define DBGC_CUR_DBGBUF_STATUS_IDX_MSK … #define MON_DMARB_RD_CTL_ADDR … #define MON_DMARB_RD_DATA_ADDR … #define DBGC_IN_SAMPLE … #define DBGC_OUT_CTRL … /* M2S registers */ #define LDBG_M2S_BUF_WPTR … #define LDBG_M2S_BUF_WRAP_CNT … #define LDBG_M2S_BUF_WPTR_VAL_MSK … #define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK … /* enable the ID buf for read */ #define WFPM_PS_CTL_CLR … #define WFMP_MAC_ADDR_0 … #define WFMP_MAC_ADDR_1 … #define LMPM_PMG_EN … #define RADIO_REG_SYS_MANUAL_DFT_0 … #define RFIC_REG_RD … #define WFPM_CTRL_REG … #define WFPM_OTP_CFG1_ADDR … #define WFPM_OTP_CFG1_IS_JACKET_BIT … #define WFPM_OTP_CFG1_IS_CDB_BIT … #define WFPM_OTP_BZ_BNJ_JACKET_BIT … #define WFPM_OTP_BZ_BNJ_CDB_BIT … #define WFPM_OTP_CFG1_IS_JACKET(_val) … #define WFPM_OTP_CFG1_IS_CDB(_val) … #define WFPM_GP2 … /* DBGI SRAM Register details */ #define DBGI_SRAM_TARGET_ACCESS_RDATA_LSB … #define DBGI_SRAM_TARGET_ACCESS_RDATA_MSB … #define DBGI_SRAM_FIFO_POINTERS … #define DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK … enum { … }; #define CNVI_AUX_MISC_CHIP … #define CNVI_AUX_MISC_CHIP_MAC_STEP(_val) … #define CNVI_AUX_MISC_CHIP_PROD_TYPE(_val) … #define CNVI_AUX_MISC_CHIP_PROD_TYPE_GL … #define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U … #define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_I … #define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_W … #define CNVR_AUX_MISC_CHIP … #define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM … #define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR … #define CNVI_SCU_SEQ_DATA_DW9 … #define CNVI_PMU_STEP_FLOW … #define CNVI_PMU_STEP_FLOW_FORCE_URM … #define PREG_AUX_BUS_WPROT_0 … /* device family 9000 WPROT register */ #define PREG_PRPH_WPROT_9000 … /* device family 22000 WPROT register */ #define PREG_PRPH_WPROT_22000 … #define SB_MODIFY_CFG_FLAG … #define SB_CFG_RESIDES_IN_ROM … #define SB_CPU_1_STATUS … #define SB_CPU_2_STATUS … #define UMAG_SB_CPU_1_STATUS … #define UMAG_SB_CPU_2_STATUS … #define UMAG_GEN_HW_STATUS … #define UREG_UMAC_CURRENT_PC … #define UREG_LMAC1_CURRENT_PC … #define UREG_LMAC2_CURRENT_PC … #define WFPM_LMAC1_PD_NOTIFICATION … #define WFPM_ARC1_PD_NOTIFICATION … #define HPM_SECONDARY_DEVICE_STATE … #define WFPM_MAC_OTP_CFG7_ADDR … #define WFPM_MAC_OTP_CFG7_DATA … /* For UMAG_GEN_HW_STATUS reg check */ enum { … }; /* FW chicken bits */ #define LMPM_CHICK … enum { … }; /* FW chicken bits */ #define LMPM_PAGE_PASS_NOTIF … enum { … }; /* * CRF ID register * * type: bits 0-11 * reserved: bits 12-18 * slave_exist: bit 19 * dash: bits 20-23 * step: bits 24-27 * flavor: bits 28-31 */ #define REG_CRF_ID_TYPE(val) … #define REG_CRF_ID_SLAVE(val) … #define REG_CRF_ID_DASH(val) … #define REG_CRF_ID_STEP(val) … #define REG_CRF_ID_FLAVOR(val) … #define UREG_CHICK … #define UREG_CHICK_MSI_ENABLE … #define UREG_CHICK_MSIX_ENABLE … #define SD_REG_VER … #define SD_REG_VER_GEN2 … #define REG_CRF_ID_TYPE_JF_1 … #define REG_CRF_ID_TYPE_JF_2 … #define REG_CRF_ID_TYPE_HR_CDB … #define REG_CRF_ID_TYPE_HR_NONE_CDB … #define REG_CRF_ID_TYPE_HR_NONE_CDB_1X1 … #define REG_CRF_ID_TYPE_HR_NONE_CDB_CCP … #define REG_CRF_ID_TYPE_GF … #define REG_CRF_ID_TYPE_FM … #define REG_CRF_ID_TYPE_WHP … #define HPM_DEBUG … #define PERSISTENCE_BIT … #define PREG_WFPM_ACCESS … #define HPM_HIPM_GEN_CFG … #define HPM_HIPM_GEN_CFG_CR_PG_EN … #define HPM_HIPM_GEN_CFG_CR_SLP_EN … #define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE … #define UREG_DOORBELL_TO_ISR6 … #define UREG_DOORBELL_TO_ISR6_NMI_BIT … #define UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE … #define UREG_DOORBELL_TO_ISR6_SUSPEND … #define UREG_DOORBELL_TO_ISR6_RESUME … #define UREG_DOORBELL_TO_ISR6_PNVM … /* * From BZ family driver triggers this bit for suspend and resume * The driver should update CSR_IPC_SLEEP_CONTROL before triggering * this interrupt with suspend/resume value */ #define UREG_DOORBELL_TO_ISR6_SLEEP_CTRL … #define CNVI_MBOX_C … #define FSEQ_ERROR_CODE … #define FSEQ_TOP_INIT_VERSION … #define FSEQ_CNVIO_INIT_VERSION … #define FSEQ_OTP_VERSION … #define FSEQ_TOP_CONTENT_VERSION … #define FSEQ_ALIVE_TOKEN … #define FSEQ_CNVI_ID … #define FSEQ_CNVR_ID … #define FSEQ_PREV_CNVIO_INIT_VERSION … #define FSEQ_WIFI_FSEQ_VERSION … #define FSEQ_BT_FSEQ_VERSION … #define FSEQ_CLASS_TP_VERSION … #define IWL_D3_SLEEP_STATUS_SUSPEND … #define IWL_D3_SLEEP_STATUS_RESUME … #define WMAL_INDRCT_RD_CMD1_OPMOD_POS … #define WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK … #define WMAL_CMD_READ_BURST_ACCESS … #define WMAL_MRSPF_1 … #define WMAL_INDRCT_RD_CMD1 … #define WMAL_INDRCT_CMD1 … #define WMAL_INDRCT_CMD(addr) … #define WFPM_LMAC1_PS_CTL_RW … #define WFPM_LMAC2_PS_CTL_RW … #define WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK … #define WFPM_PHYRF_STATE_ON … #define HBUS_TIMEOUT … #define WFPM_DPHY_OFF … #define REG_OTP_MINOR … #define WFPM_LMAC2_PD_NOTIFICATION … #define WFPM_LMAC2_PD_RE_READ … #define DPHYIP_INDIRECT … #define DPHYIP_INDIRECT_RD_MSK … #define DPHYIP_INDIRECT_RD_SHIFT … #endif /* __iwl_prph_h__ */
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